add chunk size & mvin type

Author: YunSunny00

mlir/test/lib/Conversion/MemRefToGemmini/TestMemRefToGemminiConversion.cpp

@@ -95,11 +95,12 @@ struct DmaStartOpLowering : public ConvertOpToLLVMPattern<memref::DmaStartOp> {
     Value DstPtr = getStridedElementPtr(loc, dstMemRefType, DstMemref, dst_indices, rewriter);
     Value main_mem_stride = op.getStride();
     int64_t main_mem_stride_val = extractConstantIntValue(main_mem_stride) * elen / 8;
-    Value num_elt = op.getNumElementsPerStride();
-    int num_elt_val = extractConstantIntValue(num_elt);
-    int is_transpose = 0;
-    if (num_elt_val == 1) // num_elt = 1 means transposed
-      is_transpose = 1;
+    Value num_elt_per_stride = op.getNumElementsPerStride();
+    int chunk_size = extractConstantIntValue(num_elt_per_stride);
+    bool is_transpose = chunk_size % 2;
+    chunk_size = chunk_size / 2;
+    Value numElements = op.getNumElements();
+    int mvin_type = extractConstantIntValue(numElements);
     unsigned SrcAddressSpace =
         *getTypeConverter()->getMemRefAddressSpace(srcMemRefType);
     unsigned DstAddressSpace =
@@ -121,6 +122,10 @@ struct DmaStartOpLowering : public ConvertOpToLLVMPattern<memref::DmaStartOp> {
     } else {
       return rewriter.notifyMatchFailure(op, "Unsupported DMA operation");
     }
+    // rs1 = mvin_type << 62 | main memory address
+    Value shift62 = rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI64Type(), rewriter.getI64IntegerAttr(62));
+    rs1 = rewriter.create<LLVM::ShlOp>(loc, rewriter.getI64Type(), rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI64Type(), rewriter.getI64IntegerAttr(mvin_type)), shift62);
+    rs1 = rewriter.create<LLVM::OrOp>(loc, rs1, rewriter.create<LLVM::PtrToIntOp>(loc, rewriter.getI64Type(), SrcPtr));
     Value rows;
     Value cols;
     if (tile_shape.size() == 2) {
@@ -151,11 +156,14 @@ struct DmaStartOpLowering : public ConvertOpToLLVMPattern<memref::DmaStartOp> {
         OpBuilder::InsertionGuard guard(rewriter);
         rewriter.setInsertionPointToStart(&outerBlock);
         // config_rs1 = main memory stride
-        // config_rs2 = is_transpose << 32 | element size
-        
+        // config_rs2 = chunk-size << 32 | mvin_type << 17 | is_transpose << 16 | element size
+
         Value config_rs1 = rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI64Type(), rewriter.getI64IntegerAttr(main_mem_stride_val));
+        Value config_shift16 = rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI64Type(), rewriter.getI64IntegerAttr(16));
         Value config_shift32 = rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI64Type(), rewriter.getI64IntegerAttr(32));
-        Value config_rs2 = rewriter.create<LLVM::ShlOp>(loc, rewriter.getI64Type(), rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI64Type(), rewriter.getI64IntegerAttr(is_transpose)), config_shift32);
+        Value config_rs2 = rewriter.create<LLVM::ShlOp>(loc, rewriter.getI64Type(), rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI64Type(), rewriter.getI64IntegerAttr(chunk_size)), config_shift32);
+        config_rs2 = rewriter.create<LLVM::OrOp>(loc, config_rs2, rewriter.create<LLVM::ShlOp>(loc, rewriter.getI64Type(), rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI64Type(), rewriter.getI64IntegerAttr(mvin_type)), config_shift16));
+        config_rs2 = rewriter.create<LLVM::OrOp>(loc, config_rs2, rewriter.create<LLVM::ShlOp>(loc, rewriter.getI64Type(), rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI64Type(), rewriter.getI64IntegerAttr(is_transpose)), config_shift16));
         config_rs2 = rewriter.create<LLVM::OrOp>(loc, config_rs2, rewriter.create<LLVM::ConstantOp>(loc, rewriter.getI64Type(), rewriter.getI64IntegerAttr(int(elen/8)))); // element size [bytes]
         rewriter.create<LLVM::InlineAsmOp>(
             loc,