Develop hierarchical space-time circuits, device mapping, and timed scheduling

[qciaran]

Summary

Connect QEC-aware artifacts to physical-qubit mapping, target-native lowering, and timed scheduling while preserving QEC provenance and dependencies.

Parent: #509
Architectural discussion: #508

Motivation

PECOS already contains platform/QIS lowering and runtime timing support, including explicit idles. The QEC stack needs a well-defined bridge into that infrastructure so placement, routing, decomposition, measurement latency, and feedback scheduling do not erase code/protocol semantics.

Scope

• Define target capability inputs:
  • physical-qubit topology and resource constraints;
  • native gate/measurement/reset operations;
  • durations and concurrency restrictions;
  • classical-feedback and decoder latency;
  • optional calibration/noise metadata.
• Define where logical/code geometry ends and device placement begins.
• Map data, ancilla, flag, and temporary qubits to physical resources.
• Route and lower hardware-independent operations to the native gate set.
• Produce a timed schedule with explicit idles and classical dependencies.
• Preserve source/provenance links back to protocol phases, checks, and logical operations.
• Validate connectivity, resource conflicts, timing, and feedback constraints.

Non-goals

• Replacing existing QIS/HUGR/platform lowering.
• Defining pulse-level control in the first iteration.
• Baking one vendor's topology or calibration schema into QEC core types.

Acceptance criteria

• One synthesized QEC circuit can be placed and lowered through an existing PECOS target/runtime path.
• The result includes native operations, timing/idles, and a complete source map back to QEC semantic entities.
• Invalid connectivity or overlapping resource use fails with actionable diagnostics.
• Measurement and decoder-feedback dependencies are represented explicitly.
• The boundary between reusable QEC implementation and target-specific mapping is documented.

[qciaran]

Design update: hierarchical SpaceTimeCircuit / SpaceTimeDesign

Introduce and evaluate a hierarchical space-time representation between DagCircuit and the fully flattened TickCircuit/native schedule.

Core model

A SpaceTimeVolume should contain or reference:

• semantic operation/contract;
• typed quantum and classical ports;
• resource footprint and coordinate system;
• fixed, symbolic, bounded, or target-dependent duration;
• child volumes;
• relative placement and scheduling constraints;
• implementation choice and target requirements;
• metadata, provenance, and verification results.

Leaf volumes may be native gates with physical duration on specified device resources. Composite volumes may represent gadgets, check measurements, syndrome rounds, lattice-surgery operations, factories, protocols, or complete logical circuits.

Placement vocabulary

Prefer constraint-based composition over requiring absolute coordinates at higher levels. Candidate relations include:

• after(a, b) / precedence;
• parallel(a, b);
• align_start(a, b) and align_end(a, b);
• adjacent(a.port, b.port);
• inside(child, parent);
• reserve(region, interval);
• no_overlap(a, b);
• explicit synchronization with measurements, decoders, and classical feedback.

The model must distinguish abstract qubit resources, device qubit IDs, geometric coordinates, code patches/tiles, and routing or communication regions. A multi-qubit gate occupies particular ports and may require a connecting resource; a scalar "space" size is insufficient.

Relationship to existing representations

• DagCircuit remains the dependency and qubit-wire representation.
• SpaceTimeDesign adds hierarchy, physical/logical geometry, duration, placement, and occupied resources.
• TickCircuit is a useful discrete flattened projection after resource assignment, conflict resolution, duration quantization, and substantial hierarchy lowering.
• The native device schedule remains the final target-specific artifact.

Avoid forcing these into an inheritance hierarchy. Conversions, views, and verified lowering passes may be clearer than a single universal circuit type.

Additional acceptance criteria

• A nested QEC gadget can be represented without flattening its semantic hierarchy.
• The same gadget can have at least two implementations with different footprint/duration tradeoffs.
• Placement detects spatial, temporal, port, connectivity, and classical-feedback conflicts.
• A resolved design lowers to existing DagCircuit/TickCircuit or native scheduling paths with provenance intact.
• Durations and placements may remain symbolic until a target or implementation choice resolves them.