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61 Open 354 Closed
61 Open 354 Closed
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Issues list

Wrong mstatus, mtval value when Xiangshan executes an illegal instruction. bug report Bugs to be confirmed
#3860 opened Nov 11, 2024 by ha0lyu
4 tasks done
5
When FS is 0 and a fld/fsd specific instruction causes an exception, there is a problem with the value of the mtval register
#3864 opened Nov 8, 2024 by fly-1011
1
5
sc.w Instruction Returns 0 When Operated on Different Memory Addresses, Indicating Incorrect Success Status
#3846 opened Nov 7, 2024 by fly-1011
4 tasks done
1
8
Handling Inconsistency in Load Address Misaligned and Load Access Fault Exceptions for Specific Instructions bug report Bugs to be confirmed
#3844 opened Nov 7, 2024 by fly-1011
4 tasks done
3
make verilog fail
#3842 opened Nov 6, 2024 by sasakiakaya
4 tasks done
1
Zknd extension aes64ks1i decode error. bug report Bugs to be confirmed
#3838 opened Nov 6, 2024 by ha0lyu
4 tasks done
1
8
Potential Bug in BPU on s2_fire_dup? bug report Bugs to be confirmed
#3837 opened Nov 5, 2024 by Jerry-Tianchen
4 tasks done
3
workload error; It runs for a long time with no results problem Problem requiring help
#3817 opened Oct 30, 2024 by yaoyuexiaogege
3 tasks done
3
Package the IP and compile it into a Verilog module feature request Feature request to be considered
#3743 opened Oct 15, 2024 by han-jianing
5 tasks done
2
dump-wave config: how display structs of sv in vcd wave when use gtkwave question Question requiring answer
#3678 opened Sep 29, 2024 by wyz-icer
5 tasks done
1
How did Xiangshan achieve 10Mhz uart_16550? problem Problem requiring help
#3666 opened Sep 27, 2024 by LOCKEDGATE
3 tasks done
2
Error occurred while comparing the execution of linux.bin. problem Problem requiring help
#3654 opened Sep 26, 2024 by han-jianing
3 tasks done
12
How Many LUTs Are Required for the FPGA Minimal System of the Xiangshan Processor to Operate Normally? question Question requiring answer
#3638 opened Sep 24, 2024 by Stars-Collector
5 tasks done
1
Run sudo -s ./setup-tools.sh C++ compiler has problem problem Problem requiring help
#3571 opened Sep 13, 2024 by han-jianing
3 tasks done
1
no error when make verilog, but no Top.v generated problem Problem requiring help
#3530 opened Sep 10, 2024 by han-jianing
3 tasks done
6
GPRs modification question Question requiring answer
#3466 opened Sep 2, 2024 by mlabaf2
5 tasks done
2
About SDCard module question Question requiring answer
#3448 opened Aug 30, 2024 by changekkk
5 tasks done
1
How to use Xiangshan tutorial for multi-core testing about spec 2006 problem Problem requiring help
#3446 opened Aug 29, 2024 by LOCKEDGATE
3 tasks done
@shinezyy
2
About the clock problem in Xiangshan problem Problem requiring help
#3415 opened Aug 22, 2024 by LOCKEDGATE
3 tasks done
2
wrong address space problem Problem requiring help
#3390 opened Aug 16, 2024 by mlabaf2
3 tasks done
4
How to debug Xiangshan on FPGA with OpenOCD? problem Problem requiring help
#3388 opened Aug 15, 2024 by x402
3 tasks done
@cebarobot
7
Is there any official OpenSBI version for booting linux on S2C's Prodigy™ S7-19PD Logic System？ problem Problem requiring help
#3377 opened Aug 14, 2024 by stwjt
3 tasks done
3
Is there any tutorial on how to run XiangShan RISC-V Processor on S2C's vu19p? question Question requiring answer
#3368 opened Aug 12, 2024 by yorange1
5 tasks done
2
Question about emulation of the CHI version problem Problem requiring help
#3365 opened Aug 9, 2024 by spritelzj
3 tasks done
3
add some IO ports problem Problem requiring help
#3312 opened Jul 30, 2024 by mlabaf2
3 tasks done
1
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