From 25d17d506116b9f55fa574113c7a9ce0450ff81f Mon Sep 17 00:00:00 2001
From: wakafa <wangkaifan@ict.ac.cn>
Date: Mon, 26 Dec 2022 17:46:50 +0800
Subject: [PATCH] testtop: add TestTop_L2_Standalone for slave agent
 interaction (#120)

---
 Makefile                             |   4 ++
 src/test/scala/huancun/TestTop.scala | 103 +++++++++++++++++++++++++++
 2 files changed, 107 insertions(+)

diff --git a/Makefile b/Makefile
index cbe5a2aa..39eb1401 100644
--- a/Makefile
+++ b/Makefile
@@ -13,6 +13,10 @@ test-top-l2:
 	mill -i HuanCun.test.runMain huancun.TestTop_L2 -td build
 	mv build/TestTop_L2.v build/TestTop.v
 
+test-top-l2standalone:
+	mill -i HuanCun.test.runMain huancun.TestTop_L2_Standalone -td build
+	mv build/TestTop_L2_Standalone.v build/TestTop.v
+
 test-top-l2l3:
 	mill -i HuanCun.test.runMain huancun.TestTop_L2L3 -td build
 	mv build/TestTop_L2L3.v build/TestTop.v
diff --git a/src/test/scala/huancun/TestTop.scala b/src/test/scala/huancun/TestTop.scala
index 7b8192c4..7003af47 100644
--- a/src/test/scala/huancun/TestTop.scala
+++ b/src/test/scala/huancun/TestTop.scala
@@ -69,6 +69,85 @@ class TestTop_L2()(implicit p: Parameters) extends LazyModule {
   }
 }
 
+class TestTop_L2_Standalone()(implicit p: Parameters) extends LazyModule {
+
+  /* L1D   L1D
+   *  \    /
+   *    L2
+   */
+
+  val delayFactor = 0.5
+  val cacheParams = p(HCCacheParamsKey)
+
+  def createClientNode(name: String, sources: Int) = {
+    val masterNode = TLClientNode(Seq(
+      TLMasterPortParameters.v2(
+        masters = Seq(
+          TLMasterParameters.v1(
+            name = name,
+            sourceId = IdRange(0, sources),
+            supportsProbe = TransferSizes(cacheParams.blockBytes)
+          )
+        ),
+        channelBytes = TLChannelBeatBytes(cacheParams.blockBytes),
+        minLatency = 1,
+        echoFields = cacheParams.echoField,
+        requestFields = Seq(PrefetchField(), PreferCacheField(), DirtyField(), AliasField(2)),
+        responseKeys = cacheParams.respKey
+      )
+    ))
+    masterNode
+  }
+
+  def createManagerNode(name: String, sources: Int) = {
+    val xfer = TransferSizes(cacheParams.blockBytes, cacheParams.blockBytes)
+    val slaveNode = TLManagerNode(Seq(
+      TLSlavePortParameters.v1(Seq(
+        TLSlaveParameters.v1(
+          address          = Seq(AddressSet(0, 0xffffL)),
+          regionType       = RegionType.CACHED,
+          executable       = true,
+          supportsAcquireT = xfer,
+          supportsAcquireB = xfer,
+          fifoId           = None
+        )),
+        beatBytes = 32,
+        minLatency = 2,
+        responseFields = cacheParams.respField,
+        requestKeys = cacheParams.reqKey,
+        endSinkId = sources
+      ))
+    )
+    slaveNode
+  }
+
+  val l1d_nodes = (0 until 2) map( i => createClientNode(s"l1d$i", 32))
+  val l1d_l2_tllog_nodes = (0 until 2) map(i => TLLogger(s"L1D_L2_$i"))
+  val master_nodes = l1d_nodes
+
+  val l2 = LazyModule(new HuanCun())
+  val xbar = TLXbar()
+  val l3 = createManagerNode("Fake_L3", 16)
+
+  for(i <- 0 until 2) {
+    xbar :=* l1d_l2_tllog_nodes(i) := TLBuffer() := l1d_nodes(i)
+  }
+
+  l3 :=
+    TLBuffer() :=
+    TLXbar() :=*
+    TLDelayer(delayFactor) :=*
+    l2.node :=* xbar
+
+  lazy val module = new LazyModuleImp(this){
+    master_nodes.zipWithIndex.foreach{
+      case (node, i) =>
+        node.makeIOs()(ValName(s"master_port_$i"))
+    }
+    l3.makeIOs()(ValName(s"slave_port"))
+  }
+}
+
 class TestTop_L2L3()(implicit p: Parameters) extends LazyModule {
 
   /* L1D   L1D
@@ -340,6 +419,30 @@ object TestTop_L2 extends App with HasRocketChipStageUtils {
   }
 }
 
+object TestTop_L2_Standalone extends App with HasRocketChipStageUtils {
+  val config = new Config((_, _, _) => {
+    case HCCacheParamsKey => HCCacheParameters(
+      inclusive = false,
+      clientCaches = Seq(CacheParameters(sets = 32, ways = 8, blockGranularity = 5, name = "L2", aliasBitsOpt = Some(2))),
+      echoField = Seq(DirtyField()),
+      sramClkDivBy2 = true,
+    )
+  })
+  val top = DisableMonitors(p => LazyModule(new TestTop_L2_Standalone()(p)) )(config)
+
+  (new ChiselStage).execute(args, Seq(
+    ChiselGeneratorAnnotation(() => top.module)
+  ))
+  ChiselDB.addToElaborationArtefacts
+  ElaborationArtefacts.files.foreach{
+    case (extension, contents) =>
+      val prefix = extension match {
+        case "h" | "cpp" => "chisel_db"
+      }
+      writeOutputFile("./build", s"$prefix.${extension}", contents())
+  }
+}
+
 object TestTop_L2L3 extends App with HasRocketChipStageUtils {
   val config = new Config((_, _, _) => {
     case HCCacheParamsKey => HCCacheParameters(