Skip to content

Commit

Permalink
update
Browse files Browse the repository at this point in the history
  • Loading branch information
clin99 committed Jan 4, 2019
1 parent da2c43c commit 3a75f75
Showing 1 changed file with 17 additions and 0 deletions.
17 changes: 17 additions & 0 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -216,6 +216,23 @@ The struct `Constant` records the possible number formats in Verilog
| ConstantType | `enum class` | the format of the number. The value could be NONE, INTEGER, BINARY, OCTAL, DECIMAL, HEX, REAL, EXP |
### Struct NetBit
The struct `NetBit` specifies a bit in a net
| Name | Type | Description |
| ------------- |:-------------| :--------------|
| name | std::string | the name of a net |
| bit | int | the index of the bit |
### Struct NetRange
The struct `NetRange` specifies a range in a net
| Name | Type | Description |
| ------------- |:-------------| :--------------|
| name | std::string | the name of a net |
| beg, end | int | the bit range of a net |
# Examples
The folder [example](./example) contains several tutorial examples to demonstrate the usage of Parser-Verilog.
Expand Down

0 comments on commit 3a75f75

Please sign in to comment.