From cfac7a5e3f4312d62f81d00a4152134be8d6b770 Mon Sep 17 00:00:00 2001
From: Zenithal <i@zenithal.me>
Date: Sat, 2 Apr 2022 23:48:41 +0800
Subject: [PATCH] Instructions: Separate rocket custom instructions

As standard instructions are synced from riscv-opcodes
---
 src/main/scala/rocket/CustomInstructions.scala | 12 ++++++++++++
 src/main/scala/rocket/IDecode.scala            |  1 +
 2 files changed, 13 insertions(+)
 create mode 100644 src/main/scala/rocket/CustomInstructions.scala

diff --git a/src/main/scala/rocket/CustomInstructions.scala b/src/main/scala/rocket/CustomInstructions.scala
new file mode 100644
index 00000000000..a89c901b011
--- /dev/null
+++ b/src/main/scala/rocket/CustomInstructions.scala
@@ -0,0 +1,12 @@
+// See LICENSE.SiFive for license details.
+// See LICENSE.Berkeley for license details.
+
+package freechips.rocketchip.rocket
+
+import Chisel._
+
+object CustomInstructions {
+  def CEASE              = BitPat("b00110000010100000000000001110011")
+  def CFLUSH_D_L1        = BitPat("b111111000000?????000000001110011")
+  def CDISCARD_D_L1      = BitPat("b111111000010?????000000001110011")
+}
diff --git a/src/main/scala/rocket/IDecode.scala b/src/main/scala/rocket/IDecode.scala
index 4533a67058b..6878fedc743 100644
--- a/src/main/scala/rocket/IDecode.scala
+++ b/src/main/scala/rocket/IDecode.scala
@@ -9,6 +9,7 @@ import freechips.rocketchip.tile.HasCoreParameters
 import freechips.rocketchip.util._
 import freechips.rocketchip.scie.SCIE
 import Instructions._
+import CustomInstructions._
 import ALU._
 
 abstract trait DecodeConstants extends HasCoreParameters