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Keil.STM32H5xx_DFP.pdsc
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Keil.STM32H5xx_DFP.pdsc
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<?xml version="1.0" encoding="UTF-8"?>
<package schemaVersion="1.7.36" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="https://raw.githubusercontent.com/Open-CMSIS-Pack/Open-CMSIS-Pack-Spec/v1.7.36/schema/PACK.xsd">
<vendor>Keil</vendor>
<name>STM32H5xx_DFP</name>
<description overview="Documents/OVERVIEW.md">STMicroelectronics STM32H5 Series Device Support</description>
<url>https://www.keil.com/pack/</url>
<repository type="git">https://github.com/Open-CMSIS-Pack/STM32H5xx_DFP.git</repository>
<license>LICENSE</license>
<licenseSets>
<licenseSet id="all" default="true" gating="true">
<license title="Apache-2.0 License for CMSIS add-ons" name="LICENSE" spdx="Apache-2.0"/>
</licenseSet>
</licenseSets>
<releases>
<release version="2.0.1-dev">
Active development ...
</release>
<release version="1.3.0" date="2024-04-04">
Updated to STM32Cube_FW_H5 Firmware Package version V1.2.0
Devices Support:
- Added support to:
-- H533/H523 lines with 512KB/256KB flash: Internal Non-secure/Secure Flash programming
-- H563/H562 lines with 1MB flash: Internal Non-secure/Secure Flash programming
- Fixed flashloader sector erase if the flash size less then 2MB
- Added H523/H533 SVD files
- Updated SVD files for H573/H563/H562/H503
- Updated device documentation
</release>
<release version="1.2.0" date="2023-09-01">
Devices Support:
- Updated to STM32Cube_FW_H5 Firmware Package version V1.1.0
STM32CubeMX integration:
- Added support for MEMORYMAP initialization (FrameworkCubeMX_gpdsc.ftl)
CMSIS-Driver:
- USB Device:
-- Updated PowerControl function (added check if Instance is valid)
-- Updated GetFrameNumber function (use LL function)
</release>
<release version="1.1.0" date="2023-07-10">
CMSIS Driver:
- Added Ethernet driver
- Added I2C driver
- Added SPI driver
- Added USART/UART driver
- Added USB Device driver
Device Support:
- Corrected TZ feature for STM32H503 devices
- Added CubeMX support
- Added datasheets and reference manuals
</release>
<release version="1.0.0" date="2023-03-13">
Initial public release.
Devices Support:
- Updated STM32Cube_FW_H5 Firmware Package version to V1.0.0 (HAL v1.0.0)
</release>
</releases>
<keywords>
<keyword>ST</keyword>
<keyword>Device Support</keyword>
<keyword>Device Family Package STMicroelectronics</keyword>
<keyword>STM32H5</keyword>
<keyword>STM32H5xx</keyword>
</keywords>
<devices>
<family Dfamily="STM32H5 Series" Dvendor="STMicroelectronics:13">
<processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="DSP" Dendian="Little-endian" Dclock="240000000"/>
<description>
The ARM Cortex-M33 based Microcontroller with FPU(Floating-Point Unit)is the most configurable of all Cortex-M processors.
It is a full featured microcontroller class processor based on the ARMv8-M mainline architecture with ARM TrustZone security.
</description>
<book name="https://developer.arm.com/documentation/100235/latest/" title="Arm Cortex-M33 Devices"/>
<sequences>
<!-- Override for Pre-Defined Sequences -->
<sequence name="DebugDeviceUnlock">
<block>
__var traceSWO = (__traceout & 0x1) != 0; // SWO enabled?
__var traceTPIU = (__traceout & 0x2) != 0; // Synchronous trace port enabled?
Sequence("CheckID");
</block>
<control if="traceSWO">
<block>
Sequence("ConfigureTraceSWOClock");
</block>
</control>
<control if="traceTPIU">
<block>
Sequence("ConfigureTraceTPIUClock");
</block>
</control>
</sequence>
<sequence name="DebugCoreStart">
<block>
__var ap = __ap; // Save current AP
// Replication of Standard Functionality
Write32(0xE000EDF0, 0xA05F0001); // Enable Core Debug via DHCSR
// Device Specific Debug Setup
__ap = 0; // Select System debug access port (AP0)
Write32(0xE0044004, DbgMCU_CR | (Read32(0xE0044004) & 0xF0)); // DBGMCU_CR: Configure MCU Debug
Write32(0xE0044008, DbgMCU_APB1L_Fz); // DBGMCU_APB1_FZ: Configure APB1L Peripheral Freeze Behavior
Write32(0xE004400C, DbgMCU_APB1H_Fz); // DBGMCU_APB1_FZ: Configure APB1H Peripheral Freeze Behavior
Write32(0xE0044010, DbgMCU_APB2_Fz); // DBGMCU_APB1_FZ: Configure APB2 Peripheral Freeze Behavior
Write32(0xE0044014, DbgMCU_APB3_Fz); // DBGMCU_APB3FZR: Configure APB3 Peripheral Freeze Behavior
Write32(0xE0044020, DbgMCU_AHB1_Fz); // DBGMCU_AHB1FZR: Configure AHB1 Peripheral Freeze Behavior
__ap = ap; // Restore AP
</block>
</sequence>
<!-- Override for Pre-Defined TraceStart Sequence -->
<sequence name="TraceStart">
<block>
__var traceSWO = (__traceout & 0x1) != 0; // SWO (asynchronous) Trace Selected?
__var traceTPIU = (__traceout & 0x2) != 0; // Synchronous trace port enabled?
</block>
<control if="traceSWO">
<block>
Sequence("EnableTraceSWO"); // Call SWO Trace Setup
</block>
</control>
<control if="traceTPIU">
<block>
Sequence("EnableTraceTPIU"); // Call TPIU Trace Setup
</block>
</control>
</sequence>
<sequence name="TraceStop">
<block>
__var traceSWO = (__traceout & 0x1) != 0; // SWO enabled?
__var traceTPIU = (__traceout & 0x2) != 0; // Synchronous trace port enabled?
</block>
<control if="traceSWO">
<block>
Sequence("DisableTraceSWO");
</block>
</control>
<control if="traceTPIU">
<block>
Sequence("DisableTraceTPIU");
</block>
</control>
</sequence>
<!-- User-Defined Sequences -->
<sequence name="CheckID">
<block>
__var pidr1 = 0;
__var pidr2 = 0;
__var jep106id = 0;
__var ROMTableBase = 0;
__ap = 0; // AHB-AP
ROMTableBase = ReadAP(0xF8) & ~0x3;
pidr1 = Read32(ROMTableBase + 0x0FE4);
pidr2 = Read32(ROMTableBase + 0x0FE8);
jep106id = ((pidr2 & 0x7) << 4 ) | ((pidr1 >> 4) & 0xF);
</block>
<control if="jep106id != 0x20">
<block>
Query(0, "Not a genuine ST Device! Abort connection", 1);
Message(2, "Not a genuine ST Device! Abort connection.");
</block>
</control>
</sequence>
<sequence name="EnableTraceSWO">
<block>
Sequence("ConfigureTraceSWOPin");
Sequence("ConfigureTraceSWOClock");
</block>
</sequence>
<sequence name="DisableTraceSWO">
<block>
__var ap = __ap; // Save current AP
__var dbgmcu_val = 0; // DBGMCU_CR Value
</block>
<block info="unconfigure Trace Port and Clock Enable + Trace I/O Enable + Trace Mode Asynchronous">
__ap = 0; // Select System debug access port (AP0)
dbgmcu_val = Read32(0xE0044004) & (~0xF0); // Read DBGMCU_CR and clear trace setup
Write32(0xE0044004, dbgmcu_val); // Write DBGMCU_CR: Trace Settings
__ap = ap; // Restore AP
</block>
</sequence>
<sequence name="EnableTraceTPIU">
<block>
Sequence("ConfigureTraceTPIUPins");
Sequence("ConfigureTraceTPIUClock");
</block>
</sequence>
<sequence name="DisableTraceTPIU">
<block>
__var ap = __ap; // Save current AP
__var dbgmcu_val = 0; // DBGMCU_CR Value
</block>
<block info="unconfigure Trace I/O Enable + Trace Mode Synchronous">
__ap = 0; // Select System debug access port (AP0)
dbgmcu_val = Read32(0xE0044004) & (~0xF0); // Read DBGMCU_CR and clear trace setup
Write32(0xE0044004, dbgmcu_val); // Write DBGMCU_CR: Trace Settings
__ap = ap; // Restore AP
</block>
</sequence>
<sequence name="ConfigureTraceSWOClock">
<block>
__var ap = __ap; // Save current AP
__var dbgmcu_val = 0; // DBGMCU_CR Value
__var dbgmcu_trace_val = 0; // DBGMCU_CR Value
__ap = 0; // Select System debug access port (AP0)
dbgmcu_val = Read32(0xE0044004) & (~0xF0); // Read DBGMCU_CR and clear trace setup
dbgmcu_trace_val = (1 << 5) | (1 << 4); // Trace Port and Clock Enable + Trace I/O Enable + Trace Mode Asynchronous
__ap = ap; // Restore AP
</block>
<block info="configure Trace I/O Enable + Trace Mode Asynchronous">
__ap = 0; // Select System debug access port (AP0)
Write32(0xE0044004, dbgmcu_val | dbgmcu_trace_val); // Write DBGMCU_CR: Trace Settings
__ap = ap; // Restore AP
</block>
</sequence>
<sequence name="ConfigureTraceTPIUClock">
<block>
__var ap = __ap; // Save current AP
__var dbgmcu_val = 0; // DBGMCU_CR Value
__var dbgmcu_trace_val = 0; // DBGMCU_CR Value
__var width = (__traceout & 0x003F0000) >> 16;
__ap = 0; // Select System debug access port (AP0)
dbgmcu_val = Read32(0xE0044004) & (~0xF0); // Read DBGMCU_CR and clear trace setup
__ap = ap; // Restore AP
</block>
<control if="width >= 1" info="TPIU port width 1">
<block info="configure Trace Port and Clock Enable + Trace I/O Enable + Trace Mode Synchronous 1 bit">
dbgmcu_trace_val = (3 << 5) | (1 << 4);
</block>
</control>
<control if="width >= 2" info="TPIU port width 2">
<block info="configure Trace Port and Clock Enable + Trace I/O Enable + Trace Mode Synchronous 2 bit">
dbgmcu_trace_val = (5 << 5) | (1 << 4);
</block>
</control>
<control if="width >= 4" info="TPIU port width 4">
<block info="configure Trace Port and Clock Enable + Trace I/O Enable + Trace Mode Synchronous 4 bit">
dbgmcu_trace_val = (7 << 5) | (1 << 4);
</block>
</control>
<block info="configure Trace I/O Enable + Trace Mode Asynchronous">
__ap = 0; // Select System debug access port (AP0)
Write32(0xE0044004, dbgmcu_val | dbgmcu_trace_val); // Write DBGMCU_CR: Trace Settings
__ap = ap; // Restore AP
</block>
</sequence>
<sequence name="ConfigureTraceSWOPin">
<block>
__var pin = 0;
__var port = 0;
__var portAdr = 0;
__var pos = 0;
__var secOffs = 0x00000000;
__var SWO_Pin = 0x00010003; // PB3
</block>
<control if="(Read32(0xE000EFB8) & 0x000000F0) == 0x000000F0" info="Secure debug enabled?">
<block>
secOffs = 0x10000000;
</block>
</control>
<!-- configure SWO -->
<block info="configure SWO">
pin = ((SWO_Pin ) & 0x0000FFFF);
port = ((SWO_Pin >> 16) & 0x0000FFFF);
portAdr = 0x42020000 + secOffs + (port * 0x400);
pos = pin * 2;
Write32(0x44020C8C + secOffs, ((Read32(0x44020C8C + secOffs) ) | (1 << port)) ); // RCC_AHB2ENR: IO port clock enable
Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function)
Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
</block>
<control if="pin < 8">
<block>
pos = ((pin ) & 7) * 4;
Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0
</block>
</control>
<control if="pin >= 8">
<block>
pos = ((pin - 8) & 7) * 4;
Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0
</block>
</control>
</sequence>
<sequence name="ConfigureTraceTPIUPins">
<block>
__var pin = 8;
__var port = 0;
__var portAdr = 0;
__var pos = 0;
__var secOffs = 0x00000000;
__var width = (__traceout & 0x003F0000) >> 16;
</block>
<control if="(Read32(0xE000EFB8) & 0x000000F0) == 0x000000F0" info="Secure debug enabled?">
<block>
secOffs = 0x10000000;
</block>
</control>
<!-- configure TRACECLK -->
<block info="configure TRACECLK">
pin = (TraceClk_Pin ) & 0x0000FFFF;
port = (TraceClk_Pin >> 16) & 0x0000FFFF;
portAdr = 0x42020000 + secOffs + (port * 0x400);
pos = pin * 2;
Write32(0x44020C8C + secOffs, ((Read32(0x44020C8C + secOffs) ) | (1 << port)) ); // RCC_AHB2ENR1: IO port clock enable
Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function)
Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
</block>
<control if="pin < 8">
<block>
pos = ((pin ) & 7) * 4;
Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0
</block>
</control>
<control if="pin >= 8">
<block>
pos = ((pin - 8) & 7) * 4;
Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0
</block>
</control>
<control if="width >= 1" info="TPIU port width 1">
<!-- configure TRACED0 -->
<block info="configure TRACED0">
pin = (TraceD0_Pin ) & 0x0000FFFF;
port = (TraceD0_Pin >> 16) & 0x0000FFFF;
portAdr = 0x42020000 + secOffs + (port * 0x400);
pos = pin * 2;
Write32(0x44020C8C + secOffs, ((Read32(0x44020C8C + secOffs) ) | (1 << port)) ); // RCC_AHB2ENR1: IO port clock enable
Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function)
Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
</block>
<control if="pin < 8">
<block>
pos = ((pin ) & 7) * 4;
Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0
</block>
</control>
<control if="pin >= 8">
<block>
pos = ((pin - 8) & 7) * 4;
Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0
</block>
</control>
</control>
<control if="width >= 2" info="TPIU port width 2">
<!-- configure TRACED1 -->
<block info="configure TRACED1">
pin = (TraceD1_Pin ) & 0x0000FFFF;
port = (TraceD1_Pin >> 16) & 0x0000FFFF;
portAdr = 0x42020000 + secOffs + (port * 0x400);
pos = pin * 2;
Write32(0x44020C8C + secOffs, ((Read32(0x44020C8C + secOffs) ) | (1 << port)) ); // RCC_AHB2ENR1: IO port clock enable
Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function)
Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
</block>
<control if="pin < 8">
<block>
pos = ((pin ) & 7) * 4;
Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0
</block>
</control>
<control if="pin >= 8">
<block>
pos = ((pin - 8) & 7) * 4;
Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0
</block>
</control>
</control>
<control if="width >= 4" info="TPIU port width 4">
<!-- configure TRACED2 -->
<block info="configure TRACED2">
pin = (TraceD2_Pin ) & 0x0000FFFF;
port = (TraceD2_Pin >> 16) & 0x0000FFFF;
portAdr = 0x42020000 + secOffs + (port * 0x400);
pos = pin * 2;
Write32(0x44020C8C + secOffs, ((Read32(0x44020C8C + secOffs) ) | (1 << port)) ); // RCC_AHB2ENR1: IO port clock enable
Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function)
Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
</block>
<control if="pin < 8">
<block>
pos = ((pin ) & 7) * 4;
Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0
</block>
</control>
<control if="pin >= 8">
<block>
pos = ((pin - 8) & 7) * 4;
Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0
</block>
</control>
<!-- configure TRACED3 -->
<block info="configure TRACED3">
pin = (TraceD3_Pin ) & 0x0000FFFF;
port = (TraceD3_Pin >> 16) & 0x0000FFFF;
portAdr = 0x42020000 + secOffs + (port * 0x400);
pos = pin * 2;
Write32(0x44020C8C + secOffs, ((Read32(0x44020C8C + secOffs) ) | (1 << port)) ); // RCC_AHB2ENR1: IO port clock enable
Write32(portAdr + 0x00, ((Read32(portAdr + 0x00) & ~( 3 << pos)) | (2 << pos )) ); // GPIOx_MODER: Set Mode (Alternate Function)
Write32(portAdr + 0x08, ((Read32(portAdr + 0x08) ) | (3 << pos )) ); // GPIOx_OSPEEDR: Set Speed (Very High Speed)
Write32(portAdr + 0x0C, ((Read32(portAdr + 0x0C) & ~( 3 << pos)) ) ); // GPIOx_PUPDR: Set I/O to no pull-up/pull-down
</block>
<control if="pin < 8">
<block>
pos = ((pin ) & 7) * 4;
Write32(portAdr + 0x20, ((Read32(portAdr + 0x20) & ~(15 << pos)) ) ); // GPIOx_AFRL: Alternate Function to AF0
</block>
</control>
<control if="pin >= 8">
<block>
pos = ((pin - 8) & 7) * 4;
Write32(portAdr + 0x24, ((Read32(portAdr + 0x24) & ~(15 << pos)) ) ); // GPIOx_AFRH: Alternate Function to AF0
</block>
</control>
</control>
</sequence>
</sequences>
<!-- ************************ Subfamily 'STM32H562' *************************** -->
<subFamily DsubFamily="STM32H562">
<processor Dtz="TZ"/>
<debug __ap="1" svd="CMSIS/SVD/STM32H562.svd"/>
<compile define="STM32H562xx"/>
<book name="https://www.st.com/resource/en/reference_manual/rm0481-stm32h52333xx-stm32h56263xx-and-stm32h573xx-armbased-32bit-mcus-stmicroelectronics.pdf" title="STM32H523/33xx, STM32H562/63xx and STM32H573xx Reference Manual"/>
<book name="https://www.st.com/resource/en/datasheet/stm32h562ag.pdf" title="STM32H562xx and STM32H563xx Data Sheet"/>
<debugvars configfile="CMSIS/Debug/STM32H562xx_H563xx_H573xx.dbgconf" version="1.0.0">
__var DbgMCU_CR = 0x00000006; // DBGMCU_CR: DBG_STOP, DBG_STANDBY
__var DbgMCU_APB1L_Fz = 0x00000000; // DGBMCU_APB1LFZR: All Peripherals Operate as in Normal Mode
__var DbgMCU_APB1H_Fz = 0x00000000; // DGBMCU_APB1HFZR: All Peripherals Operate as in Normal Mode
__var DbgMCU_APB2_Fz = 0x00000000; // DGBMCU_APB2FZR : All Peripherals Operate as in Normal Mode
__var DbgMCU_APB3_Fz = 0x00000000; // DBGMCU_APB3FZR : All Peripherals Operate as in Normal Mode
__var DbgMCU_AHB1_Fz = 0x00000000; // DBGMCU_AHB1FZR : All Peripherals Operate as in Normal Mode
__var TraceClk_Pin = 0x00040002; // PE2
__var TraceD0_Pin = 0x00040003; // PE3
__var TraceD1_Pin = 0x00040004; // PE4
__var TraceD2_Pin = 0x00040005; // PE5
__var TraceD3_Pin = 0x00040006; // PE6
</debugvars>
<memory name="SRAM1_2" access="rwx" start="0x20000000" size="0x00050000" default="1" init="0" />
<memory name="SRAM3" access="rwx" start="0x20050000" size="0x00050000" default="0" init="0" />
<!-- ################################### 2MB ################################## -->
<!-- ************************* Device 'STM32H562RI' ************************ -->
<device Dname="STM32H562RITx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="64"/>
</device>
<device Dname="STM32H562RIVx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFN" n="68"/>
</device>
<!-- ************************* Device 'STM32H562VI' ************************* -->
<device Dname="STM32H562VITx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="100"/>
</device>
<!-- ************************* Device 'STM32H562ZI' ************************ -->
<device Dname="STM32H562ZITx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="144"/>
</device>
<!-- ************************* Device 'STM32H562II' ************************ -->
<device Dname="STM32H562IITx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="176"/>
</device>
<device Dname="STM32H562IIKx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="BGA" n="176"/>
</device>
<!-- ************************* Device 'STM32H562AI' ************************ -->
<device Dname="STM32H562AIIx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="BGA" n="169"/>
</device>
<!-- ################################### 1MB ################################## -->
<!-- ************************* Device 'STM32H562RG' ************************ -->
<device Dname="STM32H562RGTx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0800.FLM" start="0x08000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0C00.FLM" start="0x0C000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="64"/>
</device>
<device Dname="STM32H562RGVx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0800.FLM" start="0x08000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0C00.FLM" start="0x0C000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFN" n="68"/>
</device>
<!-- ************************* Device 'STM32H562VG' ************************ -->
<device Dname="STM32H562VGTx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0800.FLM" start="0x08000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0C00.FLM" start="0x0C000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="64"/>
</device>
<!-- ************************* Device 'STM32H562ZG' ************************ -->
<device Dname="STM32H562ZGTx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0800.FLM" start="0x08000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0C00.FLM" start="0x0C000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="144"/>
</device>
<!-- ************************* Device 'STM32H562IG' ************************ -->
<device Dname="STM32H562IGTx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0800.FLM" start="0x08000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0C00.FLM" start="0x0C000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="176"/>
</device>
<device Dname="STM32H562IGKx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0800.FLM" start="0x08000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0C00.FLM" start="0x0C000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="BGA" n="176"/>
</device>
<!-- ************************* Device 'STM32H562AG' ************************ -->
<device Dname="STM32H562AGIx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0800.FLM" start="0x08000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0C00.FLM" start="0x0C000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="169"/>
</device>
</subFamily>
<!-- ************************ Subfamily 'STM32H563' *************************** -->
<subFamily DsubFamily="STM32H563">
<processor Dtz="TZ"/>
<debug __ap="1" svd="CMSIS/SVD/STM32H563.svd"/>
<compile define="STM32H563xx"/>
<book name="https://www.st.com/resource/en/reference_manual/rm0481-stm32h52333xx-stm32h56263xx-and-stm32h573xx-armbased-32bit-mcus-stmicroelectronics.pdf" title="STM32H523/33xx, STM32H562/63xx and STM32H573xx Reference Manual"/>
<book name="https://www.st.com/resource/en/datasheet/stm32h562ag.pdf" title="STM32H562xx and STM32H563xx Data Sheet"/>
<debugvars configfile="CMSIS/Debug/STM32H562xx_H563xx_H573xx.dbgconf" version="1.0.0">
__var DbgMCU_CR = 0x00000006; // DBGMCU_CR: DBG_STOP, DBG_STANDBY
__var DbgMCU_APB1L_Fz = 0x00000000; // DGBMCU_APB1LFZR: All Peripherals Operate as in Normal Mode
__var DbgMCU_APB1H_Fz = 0x00000000; // DGBMCU_APB1HFZR: All Peripherals Operate as in Normal Mode
__var DbgMCU_APB2_Fz = 0x00000000; // DGBMCU_APB2FZR : All Peripherals Operate as in Normal Mode
__var DbgMCU_APB3_Fz = 0x00000000; // DBGMCU_APB3FZR : All Peripherals Operate as in Normal Mode
__var DbgMCU_AHB1_Fz = 0x00000000; // DBGMCU_AHB1FZR : All Peripherals Operate as in Normal Mode
__var TraceClk_Pin = 0x00040002; // PE2
__var TraceD0_Pin = 0x00040003; // PE3
__var TraceD1_Pin = 0x00040004; // PE4
__var TraceD2_Pin = 0x00040005; // PE5
__var TraceD3_Pin = 0x00040006; // PE6
</debugvars>
<memory name="SRAM1_2" access="rwx" start="0x20000000" size="0x00050000" default="1" init="0" />
<memory name="SRAM3" access="rwx" start="0x20050000" size="0x00050000" default="0" init="0" />
<!-- ################################### 2MB ################################## -->
<!-- ************************* Device 'STM32H563RI' ************************ -->
<device Dname="STM32H563RITx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="64"/>
</device>
<device Dname="STM32H563RIVx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFN" n="68"/>
</device>
<!-- ************************* Device 'STM32H563VI' ************************* -->
<device Dname="STM32H563VITx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="100"/>
</device>
<device Dname="STM32H563VITxQ">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="100"/>
</device>
<!-- ************************* Device 'STM32H563ZI' ************************ -->
<device Dname="STM32H563ZITx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="144"/>
</device>
<device Dname="STM32H563ZITxQ">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="144"/>
</device>
<!-- ************************* Device 'STM32H563II' ************************ -->
<device Dname="STM32H563IITx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="176"/>
</device>
<device Dname="STM32H563IITxQ">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="176"/>
</device>
<device Dname="STM32H563IIKx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="BGA" n="176"/>
</device>
<device Dname="STM32H563IIKxQ">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="BGA" n="176"/>
</device>
<!-- ************************* Device 'STM32H563AI' ************************ -->
<device Dname="STM32H563AIIx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="BGA" n="169"/>
</device>
<device Dname="STM32H563AIIxQ">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="BGA" n="169"/>
</device>
<!-- ************************* Device 'STM32H563MI' ************************ -->
<device Dname="STM32H563MIYxQ">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="CSP" n="80"/>
</device>
<!-- ################################### 1MB ################################## -->
<!-- ************************* Device 'STM32H563RG' ************************ -->
<device Dname="STM32H563RGTx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0800.FLM" start="0x08000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0C00.FLM" start="0x0C000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="64"/>
</device>
<device Dname="STM32H563RGVx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0800.FLM" start="0x08000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0C00.FLM" start="0x0C000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFN" n="68"/>
</device>
<!-- ************************* Device 'STM32H563VG' ************************ -->
<device Dname="STM32H563VGTx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0800.FLM" start="0x08000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0C00.FLM" start="0x0C000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="64"/>
</device>
<!-- ************************* Device 'STM32H563ZG' ************************ -->
<device Dname="STM32H563ZGTx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0800.FLM" start="0x08000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0C00.FLM" start="0x0C000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="144"/>
</device>
<!-- ************************* Device 'STM32H563IG' ************************ -->
<device Dname="STM32H563IGTx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0800.FLM" start="0x08000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0C00.FLM" start="0x0C000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="176"/>
</device>
<device Dname="STM32H563IGKx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0800.FLM" start="0x08000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0C00.FLM" start="0x0C000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="BGA" n="176"/>
</device>
<!-- ************************* Device 'STM32H563AG' ************************ -->
<device Dname="STM32H563AGIx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00100000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0800.FLM" start="0x08000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_1M_0C00.FLM" start="0x0C000000" size="0x00100000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="169"/>
</device>
</subFamily>
<!-- ************************ Subfamily 'STM32H573' *************************** -->
<subFamily DsubFamily="STM32H573">
<processor Dtz="TZ"/>
<debug __ap="1" svd="CMSIS/SVD/STM32H573.svd"/>
<compile define="STM32H573xx"/>
<book name="https://www.st.com/resource/en/reference_manual/rm0481-stm32h52333xx-stm32h56263xx-and-stm32h573xx-armbased-32bit-mcus-stmicroelectronics.pdf" title="STM32H523/33xx, STM32H562/63xx and STM32H573xx Reference Manual"/>
<book name="https://www.st.com/resource/en/datasheet/stm32h573ai.pdf" title="STM32H573xx Data Sheet"/>
<debugvars configfile="CMSIS/Debug/STM32H562xx_H563xx_H573xx.dbgconf" version="1.0.0">
__var DbgMCU_CR = 0x00000006; // DBGMCU_CR: DBG_STOP, DBG_STANDBY
__var DbgMCU_APB1L_Fz = 0x00000000; // DGBMCU_APB1LFZR: All Peripherals Operate as in Normal Mode
__var DbgMCU_APB1H_Fz = 0x00000000; // DGBMCU_APB1HFZR: All Peripherals Operate as in Normal Mode
__var DbgMCU_APB2_Fz = 0x00000000; // DGBMCU_APB2FZR : All Peripherals Operate as in Normal Mode
__var DbgMCU_APB3_Fz = 0x00000000; // DBGMCU_APB3FZR : All Peripherals Operate as in Normal Mode
__var DbgMCU_AHB1_Fz = 0x00000000; // DBGMCU_AHB1FZR : All Peripherals Operate as in Normal Mode
__var TraceClk_Pin = 0x00040002; // PE2
__var TraceD0_Pin = 0x00040003; // PE3
__var TraceD1_Pin = 0x00040004; // PE4
__var TraceD2_Pin = 0x00040005; // PE5
__var TraceD3_Pin = 0x00040006; // PE6
</debugvars>
<memory name="SRAM1_2" access="rwx" start="0x20000000" size="0x00050000" default="1" init="0" />
<memory name="SRAM3" access="rwx" start="0x20050000" size="0x00050000" default="0" init="0" />
<!-- ################################### 2MB ################################## -->
<!-- ************************* Device 'STM32H573RI' ***************************** -->
<device Dname="STM32H573RITx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="64"/>
</device>
<device Dname="STM32H573RIVx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFN" n="68"/>
</device>
<!-- ************************* Device 'STM32H573VI' ***************************** -->
<device Dname="STM32H573VITx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="100"/>
</device>
<device Dname="STM32H573VITxQ">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="100"/>
</device>
<!-- ************************* Device 'STM32H573ZI' ***************************** -->
<device Dname="STM32H573ZITx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="144"/>
</device>
<device Dname="STM32H573ZITxQ">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="144"/>
</device>
<!-- ************************* Device 'STM32H573II' ***************************** -->
<device Dname="STM32H573IITx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="176"/>
</device>
<device Dname="STM32H573IITxQ">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="176"/>
</device>
<device Dname="STM32H573IIKx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="BGA" n="176"/>
</device>
<device Dname="STM32H573IIKxQ">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="BGA" n="176"/>
</device>
<!-- ************************* Device 'STM32H573AI' ***************************** -->
<device Dname="STM32H573AIIx">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="BGA" n="169"/>
</device>
<device Dname="STM32H573AIIxQ">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="BGA" n="169"/>
</device>
<!-- ************************* Device 'STM32H573MI' ***************************** -->
<device Dname="STM32H573MIYxQ">
<memory name="Flash" access="rx" start="0x08000000" size="0x00200000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0800.FLM" start="0x08000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_2M_0C00.FLM" start="0x0C000000" size="0x00200000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="CSP" n="80"/>
</device>
</subFamily>
<!-- ************************ Subfamily 'STM32H503' *************************** -->
<subFamily DsubFamily="STM32H503">
<processor Dtz="NO_TZ"/>
<debug __ap="1" svd="CMSIS/SVD/STM32H503.svd"/>
<compile define="STM32H503xx"/>
<book name="https://www.st.com/resource/en/reference_manual/rm0492-stm32h503-line-armbased-32bit-mcus-stmicroelectronics.pdf" title="STM32H503xx Reference Manual"/>
<book name="https://www.st.com/resource/en/datasheet/stm32h503eb.pdf" title="STM32H503xx Data Sheet"/>
<debugvars configfile="CMSIS/Debug/STM32H503xx.dbgconf" version="1.0.0">
__var DbgMCU_CR = 0x00000006; // DBGMCU_CR: DBG_STOP, DBG_STANDBY
__var DbgMCU_APB1L_Fz = 0x00000000; // DGBMCU_APB1LFZR: All Peripherals Operate as in Normal Mode
__var DbgMCU_APB1H_Fz = 0x00000000; // DGBMCU_APB1HFZR: All Peripherals Operate as in Normal Mode
__var DbgMCU_APB2_Fz = 0x00000000; // DGBMCU_APB2FZR : All Peripherals Operate as in Normal Mode
__var DbgMCU_APB3_Fz = 0x00000000; // DBGMCU_APB3FZR : All Peripherals Operate as in Normal Mode
__var DbgMCU_AHB1_Fz = 0x00000000; // DBGMCU_AHB1FZR : All Peripherals Operate as in Normal Mode
__var TraceClk_Pin = 0x00010005; // PB5
__var TraceD0_Pin = 0x00010006; // PB6
__var TraceD1_Pin = 0x00010007; // PB7
__var TraceD2_Pin = 0x00010008; // PB8
__var TraceD3_Pin = 0x0002000C; // PC12
</debugvars>
<algorithm name="CMSIS/Flash/STM32H503_128k_0800.FLM" start="0x08000000" size="0x00020000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<memory name="Flash" access="rx" start="0x08000000" size="0x00020000" default="1" startup="1" />
<memory name="SRAM1" access="rwx" start="0x20000000" size="0x00004000" default="1" init="0" />
<memory name="SRAM2" access="rwx" start="0x20004000" size="0x00004000" default="0" init="0" />
<!-- ################################### 128kB ################################ -->
<!-- ************************* Device 'STM32H503EB' ************************ -->
<device Dname="STM32H503EBYx">
<feature type="CSP" n="25"/>
</device>
<!-- ************************* Device 'STM32H503KB' ************************ -->
<device Dname="STM32H503KBUx">
<feature type="QFP" n="32"/>
</device>
<!-- ************************* Device 'STM32H503CB' ************************ -->
<device Dname="STM32H503CBUx">
<feature type="QFP" n="48"/>
</device>
<device Dname="STM32H503CBTx">
<feature type="QFP" n="48"/>
</device>
<!-- ************************* Device 'STM32H503RB' ************************ -->
<device Dname="STM32H503RBTx">
<feature type="QFP" n="64"/>
</device>
</subFamily>
<!-- ************************ Subfamily 'STM32H523' *************************** -->
<subFamily DsubFamily="STM32H523">
<processor Dtz="TZ"/>
<debug __ap="1" svd="CMSIS/SVD/STM32H523.svd"/>
<compile define="STM32H523xx"/>
<book name="https://www.st.com/resource/en/reference_manual/rm0481-stm32h52333xx-stm32h56263xx-and-stm32h573xx-armbased-32bit-mcus-stmicroelectronics.pdf" title="STM32H523/33xx, STM32H562/63xx and STM32H573xx Reference Manual"/>
<book name="https://www.st.com/resource/en/datasheet/stm32h523ce.pdf" title="STM32H523xx Data Sheet"/>
<debugvars configfile="CMSIS/Debug/STM32H562xx_H563xx_H573xx.dbgconf" version="1.0.0">
__var DbgMCU_CR = 0x00000006; // DBGMCU_CR: DBG_STOP, DBG_STANDBY
__var DbgMCU_APB1L_Fz = 0x00000000; // DGBMCU_APB1LFZR: All Peripherals Operate as in Normal Mode
__var DbgMCU_APB1H_Fz = 0x00000000; // DGBMCU_APB1HFZR: All Peripherals Operate as in Normal Mode
__var DbgMCU_APB2_Fz = 0x00000000; // DGBMCU_APB2FZR : All Peripherals Operate as in Normal Mode
__var DbgMCU_APB3_Fz = 0x00000000; // DBGMCU_APB3FZR : All Peripherals Operate as in Normal Mode
__var DbgMCU_AHB1_Fz = 0x00000000; // DBGMCU_AHB1FZR : All Peripherals Operate as in Normal Mode
__var TraceClk_Pin = 0x00040002; // PE2
__var TraceD0_Pin = 0x00040003; // PE3
__var TraceD1_Pin = 0x00040004; // PE4
__var TraceD2_Pin = 0x00040005; // PE5
__var TraceD3_Pin = 0x00040006; // PE6
</debugvars>
<memory name="SRAM1_2" access="rwx" start="0x20000000" size="0x00034000" default="1" init="0" />
<memory name="SRAM3" access="rwx" start="0x20034000" size="0x00010000" default="0" init="0" />
<!-- ################################### 512KB ################################## -->
<!-- ************************* Device 'STM32H523HE' ***************************** -->
<device Dname="STM32H523HEYxT">
<memory name="Flash" access="rx" start="0x08000000" size="0x0080000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_512K_0800.FLM" start="0x08000000" size="0x0080000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_512K_0C00.FLM" start="0x0C000000" size="0x0080000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="CSP" n="39"/>
</device>
<!-- ************************* Device 'STM32H523CE' ***************************** -->
<device Dname="STM32H523CEUx">
<memory name="Flash" access="rx" start="0x08000000" size="0x0080000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_512K_0800.FLM" start="0x08000000" size="0x0080000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_512K_0C00.FLM" start="0x0C000000" size="0x0080000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFN" n="48"/>
</device>
<device Dname="STM32H523CETx">
<memory name="Flash" access="rx" start="0x08000000" size="0x0080000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_512K_0800.FLM" start="0x08000000" size="0x0080000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_512K_0C00.FLM" start="0x0C000000" size="0x0080000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="48"/>
</device>
<!-- ************************* Device 'STM32H523RE' ***************************** -->
<device Dname="STM32H523RETx">
<memory name="Flash" access="rx" start="0x08000000" size="0x0080000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_512K_0800.FLM" start="0x08000000" size="0x0080000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_512K_0C00.FLM" start="0x0C000000" size="0x0080000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="64"/>
</device>
<!-- ************************* Device 'STM32H523VE' ***************************** -->
<device Dname="STM32H523VETx">
<memory name="Flash" access="rx" start="0x08000000" size="0x0080000" default="1" startup="1" />
<algorithm name="CMSIS/Flash/STM32H5xx_512K_0800.FLM" start="0x08000000" size="0x0080000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<algorithm name="CMSIS/Flash/STM32H5xx_512K_0C00.FLM" start="0x0C000000" size="0x0080000" default="1" RAMstart="0x20000000" RAMsize="0x8000" />
<feature type="QFP" n="100"/>