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CS202_Computer Organization/Lab Assignment1/Q1.asm

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+.data
+    filename: .space 100
+    buffer: .space 400000
+.text
+main:
+	#read filename
+	la $a0, filename
+	li $v0, 8
+	li $a1, 18
+	syscall
+
+	# open file
+	li $v0, 13
+	la $a0, filename
+	li $a1, 0 # 0 for read
+	li $a2, 0
+	syscall
+	move $s6, $v0 # save file descriptor
+
+	# read file
+	li $v0,14
+	move $a0,$s6 # load file descriptor
+	la $a1, buffer # save read content to buffer space
+	li $a2, 40 # reads 40 ascii chars
+	syscall
+
+
+    	# close file
+    	li $v0,16
+    	move $a0, $s6 # load file descriptor
+    	syscall
+
+
+	addi $t0, $a1, 0
+	li $t7, 0
+
+	li $t9, 0
+	li $a2, 0
+
+method_loop:	
+	slti $t8, $t9, 10
+	beq $t8, 0, print
+	beq $t9, 5, method_else
+	jal read
+	add $t7, $t7, $t6
+	j method_end
+method_else:
+	addi $t0, $t0, 4
+method_end:
+	addi $t9, $t9, 1
+	j method_loop
+
+read: 
+	li $t1, 0
+	li $t6, 0
+loop:
+	slti $t5, $t1, 4
+	beq $t5, 0, exit
+	mul $t6, $t6, 16
+	lb $t2, 0($t0)
+
+	slti $t5, $t2, 97
+	beq $t5, 0, char
+	addi $t2, $t2, -48
+	j calc
+char:	
+	addi $t2, $t2, -87
+calc:	
+	add $t6, $t6, $t2
+	addi $t1, $t1, 1
+	addi $t0, $t0, 1
+	j loop
+exit: jr $ra
+
+print:
+	div $t6, $t7, 65536
+	rem $t7, $t7, 65536
+	add $t8, $t7, $t6
+	lui $a0, 65535
+	add $a0, $a0, $t8
+	not $a0, $a0
+
+	li $v0, 34
+	syscall
+

CS202_Computer Organization/Lab Assignment1/Q2.asm

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+.data
+    str: .space 100
+.text
+main:
+	li $v0,8 #to get a string
+    la $a0,str
+    li $a1,100
+    syscall
+
+	addi $t0, $a0, 0 #addr
+	li $t7, 0 #bits_num
+	li $t6, 0 #1_num
+	 #bit
+loop:
+	lb $t1, 0($t0)
+	slti $t3, $t1, 47
+	beq $t3, 1, exit
+	bne $t1, 49, once_end
+	addi $t6, $t6, 1
+once_end:
+	addi $t7, $t7, 1
+	addi $t0, $t0, 1
+	j loop
+
+exit:
+	rem $t7, $t7, 2
+	rem $t6, $t6, 2 
+	xor $a0, $t6, $t7
+	li $v0, 1
+	slti $a0, $a0, 1
+	syscall

CS202_Computer Organization/Lab Assignment1/Q3.asm

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+.data
+    in: .space 10000
+    bin: .space 100000
+
+    yes: .asciiz " is a binary palindrome"
+    no: .asciiz " is not a binary palindrome"
+    ascode: .asciiz "the ASCII code is "
+    binary: .asciiz "the binary code is "
+.text
+main:
+	li $v0,8 #to get a string
+	la $a0, in
+	li $a1,100
+	syscall
+
+    	la $s1, in
+    	la $s2, bin
+    	li $v0, 11
+
+    	addi $t0, $s1, 0 #byte in pointer
+    	addi $t1, $s2, 0 #byte out pointer
+    	lb $t2, 0($t0)
+    	jal convert
+    	addi $t0, $t0, 1
+
+loop:
+	lb $t2, 0($t0) #current ascii
+	slti $v1, $t2, 32
+	beq $v1, 1, check
+
+	li $t7, 45
+	sb $t7, 0($t1)
+	addi $t1, $t1, 1
+
+	jal convert
+	addi $t0, $t0, 1
+	j loop
+
+convert:
+	addi $a0, $t2, 0
+	syscall
+
+	li $t9 64
+	li $t7, 48
+	sb $t7, 0($t1)
+	addi $t1, $t1, 1
+convert_loop:
+	slti $v1, $t9, 1
+	beq $v1, 1, convert_loop_exit
+	div $t8, $t2, $t9
+	addi $t8, $t8, 48
+	sb $t8, 0($t1)
+	addi $t1, $t1, 1
+
+	rem $t2, $t2, $t9
+	div $t9, $t9, 2
+	j convert_loop
+convert_loop_exit:
+	jr $ra
+
+check:
+	addi $t0, $s2, -1
+check_loop:
+	addi $t0, $t0, 1
+	addi $t1, $t1, -1
+	lb $t2, 0($t0)
+	lb $t3, 0($t1)
+	bne 	$t2, $t3, check_fail
+	addi $t4, $t1, -1
+	beq $t4, $t0, check_success
+	beq $t1, $t0, check_success
+	j check_loop
+
+check_fail:
+	li $v0, 4
+	la $a0, no
+	syscall
+	j ccl
+check_success:
+	li $v0, 4
+	la $a0, yes
+	syscall
+ccl:
+	li $v0, 11
+	li $a0, 10
+	syscall
+
+	li $v0, 4
+	la $a0, ascode
+	syscall
+
+	li $v0, 1
+	addi $t0, $s1, 0
+	lb $a0, 0($t0)
+	syscall
+
+	addi $t0, $t0, 1
+ccl_loop:
+	lb $t2, 0($t0)
+	slti $v1, $t2, 32
+	beq $v1, 1, ccl_loop_exit
+	li $v0, 11
+	li $a0, 45
+	syscall
+	li $v0, 1
+	addi $a0, $t2, 0
+	syscall
+
+	addi $t0, $t0, 1
+	j ccl_loop
+ccl_loop_exit:	
+	li $v0, 11
+	li $a0, 10
+	syscall
+
+	li $v0, 4
+	la $a0, binary
+	syscall
+	la $a0, bin
+	syscall
+

CS207_Digital Logic Design/Assignment 1/Task2_src/A1T2TT.md

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+### Task 2 Truth Table
+
+| $A$ | $B$    | $(A+B)'$ | $A'B'$ | $(AB)'$ | $A' + B'$ |
+| ---- | ---- | ---- | ---- | ---- | ---- |
+| 00   | 00   | 11 | 11 | 11 | 11 |
+| 00   | 01   | 10 | 10 | 11 | 11 |
+| 00   | 10   | 01 | 01 | 11 | 11 |
+| 00   | 11   | 00 | 00 | 11 | 11 |
+| 01   | 00   | 10 | 10 | 11 | 11 |
+| 01   | 01   | 10 | 10 | 10 | 10 |
+| 01   | 10   | 00 | 00 | 11 | 11 |
+| 01   | 11   | 00 | 00 | 10 | 10 |
+| 10   | 00   | 01 | 01 | 01 | 01 |
+| 10   | 01   | 00 | 00 | 11 | 11 |
+| 10   | 10   | 01 | 01 | 01 | 01 |
+| 10   | 11   | 00 | 00 | 01 | 01 |
+| 11   | 00   | 00 | 00 | 11 | 11 |
+| 11   | 01   | 00 | 00 | 10 | 10 |
+| 11   | 10   | 00 | 00 | 01 | 01 |
+| 11   | 11   | 00 | 00 | 00 | 00 |

CS207_Digital Logic Design/Assignment 1/Task2_src/DeMorgan2bit_df.v

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+`timescale 1ns / 1ps
+
+module DeMorgan2bit_df(a, b, cos, poc, cop, soc);
+input [1: 0] a, b;	
+output [1: 0] cos, poc, cop, soc;
+    assign cos[0] = ~(a[0] | b[0]);
+    assign cos[1] = ~(a[1] | b[1]);
+    assign poc[0] = ~a[0] & ~b[0];
+    assign poc[1] = ~a[1] & ~b[1];
+    assign cop[0] = ~(a[0] & b[0]);
+    assign cop[1] = ~(a[1] & b[1]);
+    assign soc[0] = ~a[0] | ~b[0];
+    assign soc[1] = ~a[1] | ~b[1];
+endmodule

CS207_Digital Logic Design/Assignment 1/Task2_src/DeMorgan2bit_sd.v

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+`timescale 1ns / 1ps
+
+module DeMorgan2bit_sd(a, b, cos, poc, cop, soc);
+input [1: 0] a,b;   
+output [1: 0] cos, poc, cop, soc;
+wire na0, nb0, na1, nb1;
+    not (na0, a[0]);
+    not (nb0, b[0]);
+    not (na1, a[1]);
+    not (nb1, b[1]);
+    nor (cos[0], a[0], b[0]);
+    nor (cos[1], a[1], b[1]);
+    and (poc[0], na0, nb0);
+    and (poc[1], na1, nb1);
+    nand (cop[0], a[0], b[0]);
+    nand (cop[1], a[1], b[1]);
+    or (soc[0], na0, nb0);
+    or (soc[1], na1, nb1);
+endmodule

CS207_Digital Logic Design/Assignment 1/Task2_src/DeMorgan2bit_sim.v

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+`timescale 1ns / 1ps
+
+module DeMorgan2bit_sim();
+reg [1: 0] sa, sb;   
+wire [1: 0] cos_df, poc_df, cop_df, soc_df, cos_sd, poc_sd, cop_sd, soc_sd;
+DeMorgan2bit_df df(
+    sa, sb, cos_df, poc_df, cop_df, soc_df
+);
+DeMorgan2bit_sd sd(
+    sa, sb, cos_sd, poc_sd, cop_sd, soc_sd
+);
+initial begin 
+    sa = 2'b0; sb = 2'b0;
+    repeat(15) #10 {sa, sb} = {sa, sb} + 1;
+    #10 $finish();
+end
+endmodule

CS207_Digital Logic Design/Assignment 1/Task3_src/Expressions.md

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+### Task 3 Expressions
+
+#### Expression 1: $F(A,B,C,D) = ∑(0,2,3,6,7,10,11,12,13,15) $
+
+$= A'B'C'D'+ A'B'CD' + A'B'CD + A'BCD' + A'BCD + AB'CD' + AB'CD + ABC'D' + ABC'D + ABCD$
+
+#### Expression 2: $F(A,B,C,D) = ∏(1,4,5,8,9,14)$
+
+$=(A+B+C+D')(A+B'+C+D)(A+B'+C+D')(A'+B+C+D)(A'+B+C+D')(A'+B'+C'+D)$
+
+#### Expression 3: $F(A,B,C,D) = B'CD' + A'CD' + A'B'D' + ABC' + CD$

CS207_Digital Logic Design/Assignment 1/Task3_src/Task3.v

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+`timescale 1ns / 1ps
+
+module Task3(a, b, c, d, o1, o2, o3);
+input  a, b, c, d;	
+output  o1, o2, o3;
+    assign o1 = (~a&~b&~c&~d) | (~a&~b&c&~d) | (~a&~b&c&d) | (~a&b&c&~d) | (~a&b&c&d)
+        | (a&~b&c&~d) | (a&~b&c&d) | (a&b&~c&~d) | (a&b&~c&d) | (a&b&c&d);
+    assign o2 = (a|b|c|~d) & (a|~b|c|d) & (a|~b|c|~d) & (~a|b|c|d) & (~a|b|c|~d) & (~a|~b|~c|d);
+    assign o3 = (~b&c&~d) | (~a&c&~d) | (~a&~b&~d) | (a&b&~c)|(c&d);
+endmodule

CS207_Digital Logic Design/Assignment 1/Task3_src/Task3_sim.v

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+`timescale 1ns / 1ps
+
+
+module Task3_sim( );
+reg sa, sb, sc, sd;
+wire so1, so2, so3;
+Task3 task3(
+    sa, sb, sc, sd, so1, so2, so3
+);
+initial begin 
+    sa = 0; sb = 0; sc = 0; sd = 0;
+    repeat(15) #10 {sa, sb, sc, sd} = {sa, sb, sc, sd} + 1;
+    #10 $finish();
+end
+endmodule

CS207_Digital Logic Design/Assignment 1/UnsignedMultiplier_src/A1T1TT.md

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+### Task 1 Truth Table
+
+| in1[1] | in1[0] | in1[1] | in2[0] | product_led[3] | product_led[2] | product_led[1] | product_led[0] |
+| ------ | ------ | ------ | ------ | -------------- | -------------- | -------------- | -------------- |
+| 0      | 0      | 0      | 0      | 0              | 0              | 0              | 0              |
+| 0      | 0      | 0      | 1      | 0              | 0              | 0              | 0              |
+| 0      | 0      | 1      | 0      | 0              | 0              | 0              | 0              |
+| 0      | 0      | 1      | 1      | 0              | 0              | 0              | 0              |
+| 0      | 1      | 0      | 0      | 0              | 0              | 0              | 0              |
+| 0      | 1      | 0      | 1      | 0              | 0              | 0              | 1              |
+| 0      | 1      | 1      | 0      | 0              | 0              | 1              | 0              |
+| 0      | 1      | 1      | 1      | 0              | 0              | 1              | 1              |
+| 1      | 0      | 0      | 0      | 0              | 0              | 0              | 0              |
+| 1      | 0      | 0      | 1      | 0              | 0              | 1              | 0              |
+| 1      | 0      | 1      | 0      | 0              | 1              | 0              | 0              |
+| 1      | 0      | 1      | 1      | 0              | 1              | 1              | 0              |
+| 1      | 1      | 0      | 0      | 0              | 0              | 0              | 0              |
+| 1      | 1      | 0      | 1      | 0              | 0              | 1              | 1              |
+| 1      | 1      | 1      | 0      | 0              | 1              | 1              | 0              |
+| 1      | 1      | 1      | 1      | 1              | 0              | 0              | 1              |

CS207_Digital Logic Design/Assignment 1/UnsignedMultiplier_src/UnsignedMultiplier.v

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+`timescale 1ns / 1ps
+
+module UnsignedMultiplier(in1, in2, product_led);
+input [1: 0] in1, in2;	
+output [3: 0]  product_led;
+    assign product_led[0] = in1[0]&in2[0];
+    assign product_led[1] = (~(in1[1]&in2[0]) & (in1[0]&in2[1]))
+        | (~(in1[0]&in2[1]) & (in1[1]&in2[0]));
+    assign product_led[2] = ((in1[1]&in2[0]) & ~(in1[1]&in2[1]) & (in1[0]&in2[1]))
+        | (~(in1[1]&in2[0]) & (in1[1]&in2[1])) | ((in1[1]&in2[1]) & ~(in1[0]&in2[1]));
+    assign product_led[3] = (in1[1]&in2[0]) & (in1[1]&in2[1] & (in1[0]&in2[1]));
+endmodule