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vga_display_map.map
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Release 14.2 Map P.28xd (nt64)
Xilinx Map Application Log File for Design 'vga_display'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o vga_display_map.ncd vga_display.ngd
vga_display.pcf
Target Device : xc6slx16
Target Package : csg324
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Thu Dec 17 12:29:44 2015
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 5 secs
Total CPU time at the beginning of Placer: 3 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:7081e4f1) REAL time: 5 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:7081e4f1) REAL time: 5 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:7081e4f1) REAL time: 5 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:8d4d2553) REAL time: 6 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:8d4d2553) REAL time: 6 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:8d4d2553) REAL time: 6 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:8d4d2553) REAL time: 6 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:8d4d2553) REAL time: 6 secs
Phase 9.8 Global Placement
.............
.......................................................................................................................................................................
..............................................................................................................................................................
..........................
Phase 9.8 Global Placement (Checksum:417c1561) REAL time: 8 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:417c1561) REAL time: 8 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:23b24867) REAL time: 9 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:23b24867) REAL time: 9 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:1cd1e3d1) REAL time: 9 secs
Total REAL time to Placer completion: 9 secs
Total CPU time to Placer completion: 7 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 1
Slice Logic Utilization:
Number of Slice Registers: 152 out of 18,224 1%
Number used as Flip Flops: 152
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 405 out of 9,112 4%
Number used as logic: 401 out of 9,112 4%
Number using O6 output only: 203
Number using O5 output only: 54
Number using O5 and O6: 144
Number used as ROM: 0
Number used as Memory: 0 out of 2,176 0%
Number used exclusively as route-thrus: 4
Number with same-slice register load: 1
Number with same-slice carry load: 3
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 153 out of 2,278 6%
Nummber of MUXCYs used: 184 out of 4,556 4%
Number of LUT Flip Flop pairs used: 424
Number with an unused Flip Flop: 277 out of 424 65%
Number with an unused LUT: 19 out of 424 4%
Number of fully used LUT-FF pairs: 128 out of 424 30%
Number of unique control sets: 20
Number of slice register sites lost
to control set restrictions: 104 out of 18,224 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 29 out of 232 12%
Number of LOCed IOBs: 29 out of 29 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 8 out of 32 25%
Number of RAMB8BWERs: 1 out of 64 1%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 4 out of 16 25%
Number used as BUFGs: 4
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 248 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0%
Number of OLOGIC2/OSERDES2s: 0 out of 248 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 1 out of 32 3%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.44
Peak Memory Usage: 371 MB
Total REAL time to MAP completion: 10 secs
Total CPU time to MAP completion: 7 secs
Mapping completed.
See MAP report file "vga_display_map.mrp" for details.