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es1371.c
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/*****************************************************************************/
/*
* es1371.c -- Creative Ensoniq ES1371.
*
* Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Special thanks to Ensoniq
*
* Supported devices:
* /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
* /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
* /dev/dsp1 additional DAC, like /dev/dsp, but outputs to mixer "SYNTH" setting
* /dev/midi simple MIDI UART interface, no ioctl
*
* NOTE: the card does not have any FM/Wavetable synthesizer, it is supposed
* to be done in software. That is what /dev/dac is for. By now (Q2 1998)
* there are several MIDI to PCM (WAV) packages, one of them is timidity.
*
* Revision history
* 04.06.1998 0.1 Initial release
* Mixer stuff should be overhauled; especially optional AC97 mixer bits
* should be detected. This results in strange behaviour of some mixer
* settings, like master volume and mic.
* 08.06.1998 0.2 First release using Alan Cox' soundcore instead of miscdevice
* 03.08.1998 0.3 Do not include modversions.h
* Now mixer behaviour can basically be selected between
* "OSS documented" and "OSS actual" behaviour
* 31.08.1998 0.4 Fix realplayer problems - dac.count issues
* 27.10.1998 0.5 Fix joystick support
* -- Oliver Neukum (c188@org.chemie.uni-muenchen.de)
* 10.12.1998 0.6 Fix drain_dac trying to wait on not yet initialized DMA
* 23.12.1998 0.7 Fix a few f_file & FMODE_ bugs
* Don't wake up app until there are fragsize bytes to read/write
* 06.01.1999 0.8 remove the silly SA_INTERRUPT flag.
* hopefully killed the egcs section type conflict
* 12.03.1999 0.9 cinfo.blocks should be reset after GETxPTR ioctl.
* reported by Johan Maes <joma@telindus.be>
* 22.03.1999 0.10 return EAGAIN instead of EBUSY when O_NONBLOCK
* read/write cannot be executed
* 07.04.1999 0.11 implemented the following ioctl's: SOUND_PCM_READ_RATE,
* SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
* Alpha fixes reported by Peter Jones <pjones@redhat.com>
* Another Alpha fix (wait_src_ready in init routine)
* reported by "Ivan N. Kokshaysky" <ink@jurassic.park.msu.ru>
* Note: joystick address handling might still be wrong on archs
* other than i386
* 15.06.1999 0.12 Fix bad allocation bug.
* Thanks to Deti Fliegl <fliegl@in.tum.de>
* 28.06.1999 0.13 Add pci_set_master
* 03.08.1999 0.14 adapt to Linus' new __setup/__initcall
* added kernel command line option "es1371=joystickaddr"
* removed CONFIG_SOUND_ES1371_JOYPORT_BOOT kludge
* 10.08.1999 0.15 (Re)added S/PDIF module option for cards revision >= 4.
* Initial version by Dave Platt <dplatt@snulbug.mtview.ca.us>.
* module_init/__setup fixes
* 08.16.1999 0.16 Joe Cotellese <joec@ensoniq.com>
* Added detection for ES1371 revision ID so that we can
* detect the ES1373 and later parts.
* added AC97 #defines for readability
* added a /proc file system for dumping hardware state
* updated SRC and CODEC w/r functions to accommodate bugs
* in some versions of the ES137x chips.
* 31.08.1999 0.17 add spin_lock_init
* replaced current->state = x with set_current_state(x)
* 03.09.1999 0.18 change read semantics for MIDI to match
* OSS more closely; remove possible wakeup race
* 21.10.1999 0.19 Round sampling rates, requested by
* Kasamatsu Kenichi <t29w0267@ip.media.kyoto-u.ac.jp>
* 27.10.1999 0.20 Added SigmaTel 3D enhancement string
* Codec ID printing changes
* 28.10.1999 0.21 More waitqueue races fixed
* Joe Cotellese <joec@ensoniq.com>
* Changed PCI detection routine so we can more easily
* detect ES137x chip and derivatives.
* 05.01.2000 0.22 Should now work with rev7 boards; patch by
* Eric Lemar, elemar@cs.washington.edu
* 08.01.2000 0.23 Prevent some ioctl's from returning bad count values on underrun/overrun;
* Tim Janik's BSE (Bedevilled Sound Engine) found this
* 07.02.2000 0.24 Use pci_alloc_consistent and pci_register_driver
* 07.02.2000 0.25 Use ac97_codec
* 01.03.2000 0.26 SPDIF patch by Mikael Bouillot <mikael.bouillot@bigfoot.com>
* Use pci_module_init
* 21.11.2000 0.27 Initialize dma buffers in poll, otherwise poll may return a bogus mask
* 12.12.2000 0.28 More dma buffer initializations, patch from
* Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
* 05.01.2001 0.29 Hopefully updates will not be required anymore when Creative bumps
* the CT5880 revision.
* suggested by Stephan Müller <smueller@chronox.de>
* 31.01.2001 0.30 Register/Unregister gameport
* Fix SETTRIGGER non OSS API conformity
* 14.07.2001 0.31 Add list of laptops needing amplifier control
* 03.01.2003 0.32 open_mode fixes from Georg Acher <acher@in.tum.de>
*/
/*****************************************************************************/
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/sound.h>
#include <linux/slab.h>
#include <linux/soundcard.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/poll.h>
#include <linux/bitops.h>
#include <linux/proc_fs.h>
#include <linux/spinlock.h>
#include <linux/smp_lock.h>
#include <linux/ac97_codec.h>
#include <linux/gameport.h>
#include <linux/wait.h>
#include <asm/io.h>
#include <asm/page.h>
#include <asm/uaccess.h>
/* --------------------------------------------------------------------- */
#undef OSS_DOCUMENTED_MIXER_SEMANTICS
#define ES1371_DEBUG
#define DBG(x) {}
/*#define DBG(x) {x}*/
/* --------------------------------------------------------------------- */
#ifndef PCI_VENDOR_ID_ENSONIQ
#define PCI_VENDOR_ID_ENSONIQ 0x1274
#endif
#ifndef PCI_VENDOR_ID_ECTIVA
#define PCI_VENDOR_ID_ECTIVA 0x1102
#endif
#ifndef PCI_DEVICE_ID_ENSONIQ_ES1371
#define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371
#endif
#ifndef PCI_DEVICE_ID_ENSONIQ_CT5880
#define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880
#endif
#ifndef PCI_DEVICE_ID_ECTIVA_EV1938
#define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938
#endif
/* ES1371 chip ID */
/* This is a little confusing because all ES1371 compatible chips have the
same DEVICE_ID, the only thing differentiating them is the REV_ID field.
This is only significant if you want to enable features on the later parts.
Yes, I know it's stupid and why didn't we use the sub IDs?
*/
#define ES1371REV_ES1373_A 0x04
#define ES1371REV_ES1373_B 0x06
#define ES1371REV_CT5880_A 0x07
#define CT5880REV_CT5880_C 0x02
#define CT5880REV_CT5880_D 0x03
#define ES1371REV_ES1371_B 0x09
#define EV1938REV_EV1938_A 0x00
#define ES1371REV_ES1373_8 0x08
#define ES1371_MAGIC ((PCI_VENDOR_ID_ENSONIQ<<16)|PCI_DEVICE_ID_ENSONIQ_ES1371)
#define ES1371_EXTENT 0x40
#define JOY_EXTENT 8
#define ES1371_REG_CONTROL 0x00
#define ES1371_REG_STATUS 0x04 /* on the 5880 it is control/status */
#define ES1371_REG_UART_DATA 0x08
#define ES1371_REG_UART_STATUS 0x09
#define ES1371_REG_UART_CONTROL 0x09
#define ES1371_REG_UART_TEST 0x0a
#define ES1371_REG_MEMPAGE 0x0c
#define ES1371_REG_SRCONV 0x10
#define ES1371_REG_CODEC 0x14
#define ES1371_REG_LEGACY 0x18
#define ES1371_REG_SERIAL_CONTROL 0x20
#define ES1371_REG_DAC1_SCOUNT 0x24
#define ES1371_REG_DAC2_SCOUNT 0x28
#define ES1371_REG_ADC_SCOUNT 0x2c
#define ES1371_REG_DAC1_FRAMEADR 0xc30
#define ES1371_REG_DAC1_FRAMECNT 0xc34
#define ES1371_REG_DAC2_FRAMEADR 0xc38
#define ES1371_REG_DAC2_FRAMECNT 0xc3c
#define ES1371_REG_ADC_FRAMEADR 0xd30
#define ES1371_REG_ADC_FRAMECNT 0xd34
#define ES1371_FMT_U8_MONO 0
#define ES1371_FMT_U8_STEREO 1
#define ES1371_FMT_S16_MONO 2
#define ES1371_FMT_S16_STEREO 3
#define ES1371_FMT_STEREO 1
#define ES1371_FMT_S16 2
#define ES1371_FMT_MASK 3
static const unsigned sample_size[] = { 1, 2, 2, 4 };
static const unsigned sample_shift[] = { 0, 1, 1, 2 };
#define CTRL_RECEN_B 0x08000000 /* 1 = don't mix analog in to digital out */
#define CTRL_SPDIFEN_B 0x04000000
#define CTRL_JOY_SHIFT 24
#define CTRL_JOY_MASK 3
#define CTRL_JOY_200 0x00000000 /* joystick base address */
#define CTRL_JOY_208 0x01000000
#define CTRL_JOY_210 0x02000000
#define CTRL_JOY_218 0x03000000
#define CTRL_GPIO_IN0 0x00100000 /* general purpose inputs/outputs */
#define CTRL_GPIO_IN1 0x00200000
#define CTRL_GPIO_IN2 0x00400000
#define CTRL_GPIO_IN3 0x00800000
#define CTRL_GPIO_OUT0 0x00010000
#define CTRL_GPIO_OUT1 0x00020000
#define CTRL_GPIO_OUT2 0x00040000
#define CTRL_GPIO_OUT3 0x00080000
#define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */
#define CTRL_SYNCRES 0x00004000 /* AC97 warm reset */
#define CTRL_ADCSTOP 0x00002000 /* stop ADC transfers */
#define CTRL_PWR_INTRM 0x00001000 /* 1 = power level ints enabled */
#define CTRL_M_CB 0x00000800 /* recording source: 0 = ADC, 1 = MPEG */
#define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
#define CTRL_PDLEV0 0x00000000 /* power down level */
#define CTRL_PDLEV1 0x00000100
#define CTRL_PDLEV2 0x00000200
#define CTRL_PDLEV3 0x00000300
#define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
#define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
#define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
#define CTRL_ADC_EN 0x00000010 /* enable ADC */
#define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
#define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port */
#define CTRL_XTALCLKDIS 0x00000002 /* 1 = disable crystal clock input */
#define CTRL_PCICLKDIS 0x00000001 /* 1 = disable PCI clock distribution */
#define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
#define CSTAT_5880_AC97_RST 0x20000000 /* CT5880 Reset bit */
#define STAT_EN_SPDIF 0x00040000 /* enable S/PDIF circuitry */
#define STAT_TS_SPDIF 0x00020000 /* test S/PDIF circuitry */
#define STAT_TESTMODE 0x00010000 /* test ASIC */
#define STAT_SYNC_ERR 0x00000100 /* 1 = codec sync error */
#define STAT_VC 0x000000c0 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
#define STAT_SH_VC 6
#define STAT_MPWR 0x00000020 /* power level interrupt */
#define STAT_MCCB 0x00000010 /* CCB int pending */
#define STAT_UART 0x00000008 /* UART int pending */
#define STAT_DAC1 0x00000004 /* DAC1 int pending */
#define STAT_DAC2 0x00000002 /* DAC2 int pending */
#define STAT_ADC 0x00000001 /* ADC int pending */
#define USTAT_RXINT 0x80 /* UART rx int pending */
#define USTAT_TXINT 0x04 /* UART tx int pending */
#define USTAT_TXRDY 0x02 /* UART tx ready */
#define USTAT_RXRDY 0x01 /* UART rx ready */
#define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */
#define UCTRL_TXINTEN 0x60 /* TX int enable field mask */
#define UCTRL_ENA_TXINT 0x20 /* enable TX int */
#define UCTRL_CNTRL 0x03 /* control field */
#define UCTRL_CNTRL_SWR 0x03 /* software reset command */
/* sample rate converter */
#define SRC_OKSTATE 1
#define SRC_RAMADDR_MASK 0xfe000000
#define SRC_RAMADDR_SHIFT 25
#define SRC_DAC1FREEZE (1UL << 21)
#define SRC_DAC2FREEZE (1UL << 20)
#define SRC_ADCFREEZE (1UL << 19)
#define SRC_WE 0x01000000 /* read/write control for SRC RAM */
#define SRC_BUSY 0x00800000 /* SRC busy */
#define SRC_DIS 0x00400000 /* 1 = disable SRC */
#define SRC_DDAC1 0x00200000 /* 1 = disable accum update for DAC1 */
#define SRC_DDAC2 0x00100000 /* 1 = disable accum update for DAC2 */
#define SRC_DADC 0x00080000 /* 1 = disable accum update for ADC2 */
#define SRC_CTLMASK 0x00780000
#define SRC_RAMDATA_MASK 0x0000ffff
#define SRC_RAMDATA_SHIFT 0
#define SRCREG_ADC 0x78
#define SRCREG_DAC1 0x70
#define SRCREG_DAC2 0x74
#define SRCREG_VOL_ADC 0x6c
#define SRCREG_VOL_DAC1 0x7c
#define SRCREG_VOL_DAC2 0x7e
#define SRCREG_TRUNC_N 0x00
#define SRCREG_INT_REGS 0x01
#define SRCREG_ACCUM_FRAC 0x02
#define SRCREG_VFREQ_FRAC 0x03
#define CODEC_PIRD 0x00800000 /* 0 = write AC97 register */
#define CODEC_PIADD_MASK 0x007f0000
#define CODEC_PIADD_SHIFT 16
#define CODEC_PIDAT_MASK 0x0000ffff
#define CODEC_PIDAT_SHIFT 0
#define CODEC_RDY 0x80000000 /* AC97 read data valid */
#define CODEC_WIP 0x40000000 /* AC97 write in progress */
#define CODEC_PORD 0x00800000 /* 0 = write AC97 register */
#define CODEC_POADD_MASK 0x007f0000
#define CODEC_POADD_SHIFT 16
#define CODEC_PODAT_MASK 0x0000ffff
#define CODEC_PODAT_SHIFT 0
#define LEGACY_JFAST 0x80000000 /* fast joystick timing */
#define LEGACY_FIRQ 0x01000000 /* force IRQ */
#define SCTRL_DACTEST 0x00400000 /* 1 = DAC test, test vector generation purposes */
#define SCTRL_P2ENDINC 0x00380000 /* */
#define SCTRL_SH_P2ENDINC 19
#define SCTRL_P2STINC 0x00070000 /* */
#define SCTRL_SH_P2STINC 16
#define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
#define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
#define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
#define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
#define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
#define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
#define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
#define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
#define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */
#define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */
#define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
#define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
#define SCTRL_R1FMT 0x00000030 /* format mask */
#define SCTRL_SH_R1FMT 4
#define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
#define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
#define SCTRL_P2FMT 0x0000000c /* format mask */
#define SCTRL_SH_P2FMT 2
#define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
#define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
#define SCTRL_P1FMT 0x00000003 /* format mask */
#define SCTRL_SH_P1FMT 0
/* misc stuff */
#define POLL_COUNT 0x1000
#define FMODE_DAC 4 /* slight misuse of mode_t */
/* MIDI buffer sizes */
#define MIDIINBUF 256
#define MIDIOUTBUF 256
#define FMODE_MIDI_SHIFT 3
#define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
#define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
#define ES1371_MODULE_NAME "es1371"
#define PFX ES1371_MODULE_NAME ": "
/* --------------------------------------------------------------------- */
struct es1371_state {
/* magic */
unsigned int magic;
/* list of es1371 devices */
struct list_head devs;
/* the corresponding pci_dev structure */
struct pci_dev *dev;
/* soundcore stuff */
int dev_audio;
int dev_dac;
int dev_midi;
/* hardware resources */
unsigned long io; /* long for SPARC */
unsigned int irq;
/* PCI ID's */
u16 vendor;
u16 device;
u8 rev; /* the chip revision */
/* options */
int spdif_volume; /* S/PDIF output is enabled if != -1 */
#ifdef ES1371_DEBUG
/* debug /proc entry */
struct proc_dir_entry *ps;
#endif /* ES1371_DEBUG */
struct ac97_codec *codec;
/* wave stuff */
unsigned ctrl;
unsigned sctrl;
unsigned dac1rate, dac2rate, adcrate;
spinlock_t lock;
struct semaphore open_sem;
mode_t open_mode;
wait_queue_head_t open_wait;
struct dmabuf {
void *rawbuf;
dma_addr_t dmaaddr;
unsigned buforder;
unsigned numfrag;
unsigned fragshift;
unsigned hwptr, swptr;
unsigned total_bytes;
int count;
unsigned error; /* over/underrun */
wait_queue_head_t wait;
/* redundant, but makes calculations easier */
unsigned fragsize;
unsigned dmasize;
unsigned fragsamples;
/* OSS stuff */
unsigned mapped:1;
unsigned ready:1;
unsigned endcleared:1;
unsigned enabled:1;
unsigned ossfragshift;
int ossmaxfrags;
unsigned subdivision;
} dma_dac1, dma_dac2, dma_adc;
/* midi stuff */
struct {
unsigned ird, iwr, icnt;
unsigned ord, owr, ocnt;
wait_queue_head_t iwait;
wait_queue_head_t owait;
unsigned char ibuf[MIDIINBUF];
unsigned char obuf[MIDIOUTBUF];
} midi;
struct gameport *gameport;
struct semaphore sem;
};
/* --------------------------------------------------------------------- */
static LIST_HEAD(devs);
/* --------------------------------------------------------------------- */
static inline unsigned ld2(unsigned int x)
{
unsigned r = 0;
if (x >= 0x10000) {
x >>= 16;
r += 16;
}
if (x >= 0x100) {
x >>= 8;
r += 8;
}
if (x >= 0x10) {
x >>= 4;
r += 4;
}
if (x >= 4) {
x >>= 2;
r += 2;
}
if (x >= 2)
r++;
return r;
}
/* --------------------------------------------------------------------- */
static unsigned wait_src_ready(struct es1371_state *s)
{
unsigned int t, r;
for (t = 0; t < POLL_COUNT; t++) {
if (!((r = inl(s->io + ES1371_REG_SRCONV)) & SRC_BUSY))
return r;
udelay(1);
}
printk(KERN_DEBUG PFX "sample rate converter timeout r = 0x%08x\n", r);
return r;
}
static unsigned src_read(struct es1371_state *s, unsigned reg)
{
unsigned int temp,i,orig;
/* wait for ready */
temp = wait_src_ready (s);
/* we can only access the SRC at certain times, make sure
we're allowed to before we read */
orig = temp;
/* expose the SRC state bits */
outl ( (temp & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT) | 0x10000UL,
s->io + ES1371_REG_SRCONV);
/* now, wait for busy and the correct time to read */
temp = wait_src_ready (s);
if ( (temp & 0x00870000UL ) != ( SRC_OKSTATE << 16 )){
/* wait for the right state */
for (i=0; i<POLL_COUNT; i++){
temp = inl (s->io + ES1371_REG_SRCONV);
if ( (temp & 0x00870000UL ) == ( SRC_OKSTATE << 16 ))
break;
}
}
/* hide the state bits */
outl ((orig & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT), s->io + ES1371_REG_SRCONV);
return temp;
}
static void src_write(struct es1371_state *s, unsigned reg, unsigned data)
{
unsigned int r;
r = wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC);
r |= (reg << SRC_RAMADDR_SHIFT) & SRC_RAMADDR_MASK;
r |= (data << SRC_RAMDATA_SHIFT) & SRC_RAMDATA_MASK;
outl(r | SRC_WE, s->io + ES1371_REG_SRCONV);
}
/* --------------------------------------------------------------------- */
/* most of the following here is black magic */
static void set_adc_rate(struct es1371_state *s, unsigned rate)
{
unsigned long flags;
unsigned int n, truncm, freq;
if (rate > 48000)
rate = 48000;
if (rate < 4000)
rate = 4000;
n = rate / 3000;
if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
n--;
truncm = (21 * n - 1) | 1;
freq = ((48000UL << 15) / rate) * n;
s->adcrate = (48000UL << 15) / (freq / n);
spin_lock_irqsave(&s->lock, flags);
if (rate >= 24000) {
if (truncm > 239)
truncm = 239;
src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
(((239 - truncm) >> 1) << 9) | (n << 4));
} else {
if (truncm > 119)
truncm = 119;
src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
}
src_write(s, SRCREG_ADC+SRCREG_INT_REGS,
(src_read(s, SRCREG_ADC+SRCREG_INT_REGS) & 0x00ff) |
((freq >> 5) & 0xfc00));
src_write(s, SRCREG_ADC+SRCREG_VFREQ_FRAC, freq & 0x7fff);
src_write(s, SRCREG_VOL_ADC, n << 8);
src_write(s, SRCREG_VOL_ADC+1, n << 8);
spin_unlock_irqrestore(&s->lock, flags);
}
static void set_dac1_rate(struct es1371_state *s, unsigned rate)
{
unsigned long flags;
unsigned int freq, r;
if (rate > 48000)
rate = 48000;
if (rate < 4000)
rate = 4000;
freq = ((rate << 15) + 1500) / 3000;
s->dac1rate = (freq * 3000 + 16384) >> 15;
spin_lock_irqsave(&s->lock, flags);
r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC)) | SRC_DDAC1;
outl(r, s->io + ES1371_REG_SRCONV);
src_write(s, SRCREG_DAC1+SRCREG_INT_REGS,
(src_read(s, SRCREG_DAC1+SRCREG_INT_REGS) & 0x00ff) |
((freq >> 5) & 0xfc00));
src_write(s, SRCREG_DAC1+SRCREG_VFREQ_FRAC, freq & 0x7fff);
r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC));
outl(r, s->io + ES1371_REG_SRCONV);
spin_unlock_irqrestore(&s->lock, flags);
}
static void set_dac2_rate(struct es1371_state *s, unsigned rate)
{
unsigned long flags;
unsigned int freq, r;
if (rate > 48000)
rate = 48000;
if (rate < 4000)
rate = 4000;
freq = ((rate << 15) + 1500) / 3000;
s->dac2rate = (freq * 3000 + 16384) >> 15;
spin_lock_irqsave(&s->lock, flags);
r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC)) | SRC_DDAC2;
outl(r, s->io + ES1371_REG_SRCONV);
src_write(s, SRCREG_DAC2+SRCREG_INT_REGS,
(src_read(s, SRCREG_DAC2+SRCREG_INT_REGS) & 0x00ff) |
((freq >> 5) & 0xfc00));
src_write(s, SRCREG_DAC2+SRCREG_VFREQ_FRAC, freq & 0x7fff);
r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC));
outl(r, s->io + ES1371_REG_SRCONV);
spin_unlock_irqrestore(&s->lock, flags);
}
/* --------------------------------------------------------------------- */
static void __devinit src_init(struct es1371_state *s)
{
unsigned int i;
/* before we enable or disable the SRC we need
to wait for it to become ready */
wait_src_ready(s);
outl(SRC_DIS, s->io + ES1371_REG_SRCONV);
for (i = 0; i < 0x80; i++)
src_write(s, i, 0);
src_write(s, SRCREG_DAC1+SRCREG_TRUNC_N, 16 << 4);
src_write(s, SRCREG_DAC1+SRCREG_INT_REGS, 16 << 10);
src_write(s, SRCREG_DAC2+SRCREG_TRUNC_N, 16 << 4);
src_write(s, SRCREG_DAC2+SRCREG_INT_REGS, 16 << 10);
src_write(s, SRCREG_VOL_ADC, 1 << 12);
src_write(s, SRCREG_VOL_ADC+1, 1 << 12);
src_write(s, SRCREG_VOL_DAC1, 1 << 12);
src_write(s, SRCREG_VOL_DAC1+1, 1 << 12);
src_write(s, SRCREG_VOL_DAC2, 1 << 12);
src_write(s, SRCREG_VOL_DAC2+1, 1 << 12);
set_adc_rate(s, 22050);
set_dac1_rate(s, 22050);
set_dac2_rate(s, 22050);
/* WARNING:
* enabling the sample rate converter without properly programming
* its parameters causes the chip to lock up (the SRC busy bit will
* be stuck high, and I've found no way to rectify this other than
* power cycle)
*/
wait_src_ready(s);
outl(0, s->io+ES1371_REG_SRCONV);
}
/* --------------------------------------------------------------------- */
static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
{
struct es1371_state *s = (struct es1371_state *)codec->private_data;
unsigned long flags;
unsigned t, x;
spin_lock_irqsave(&s->lock, flags);
for (t = 0; t < POLL_COUNT; t++)
if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
break;
/* save the current state for later */
x = wait_src_ready(s);
/* enable SRC state data in SRC mux */
outl((x & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC)) | 0x00010000,
s->io+ES1371_REG_SRCONV);
/* wait for not busy (state 0) first to avoid
transition states */
for (t=0; t<POLL_COUNT; t++){
if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
break;
udelay(1);
}
/* wait for a SAFE time to write addr/data and then do it, dammit */
for (t=0; t<POLL_COUNT; t++){
if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
break;
udelay(1);
}
outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) |
((data << CODEC_PODAT_SHIFT) & CODEC_PODAT_MASK), s->io+ES1371_REG_CODEC);
/* restore SRC reg */
wait_src_ready(s);
outl(x, s->io+ES1371_REG_SRCONV);
spin_unlock_irqrestore(&s->lock, flags);
}
static u16 rdcodec(struct ac97_codec *codec, u8 addr)
{
struct es1371_state *s = (struct es1371_state *)codec->private_data;
unsigned long flags;
unsigned t, x;
spin_lock_irqsave(&s->lock, flags);
/* wait for WIP to go away */
for (t = 0; t < 0x1000; t++)
if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
break;
/* save the current state for later */
x = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC));
/* enable SRC state data in SRC mux */
outl( x | 0x00010000,
s->io+ES1371_REG_SRCONV);
/* wait for not busy (state 0) first to avoid
transition states */
for (t=0; t<POLL_COUNT; t++){
if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
break;
udelay(1);
}
/* wait for a SAFE time to write addr/data and then do it, dammit */
for (t=0; t<POLL_COUNT; t++){
if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
break;
udelay(1);
}
outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | CODEC_PORD, s->io+ES1371_REG_CODEC);
/* restore SRC reg */
wait_src_ready(s);
outl(x, s->io+ES1371_REG_SRCONV);
/* wait for WIP again */
for (t = 0; t < 0x1000; t++)
if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
break;
/* now wait for the stinkin' data (RDY) */
for (t = 0; t < POLL_COUNT; t++)
if ((x = inl(s->io+ES1371_REG_CODEC)) & CODEC_RDY)
break;
spin_unlock_irqrestore(&s->lock, flags);
return ((x & CODEC_PIDAT_MASK) >> CODEC_PIDAT_SHIFT);
}
/* --------------------------------------------------------------------- */
static inline void stop_adc(struct es1371_state *s)
{
unsigned long flags;
spin_lock_irqsave(&s->lock, flags);
s->ctrl &= ~CTRL_ADC_EN;
outl(s->ctrl, s->io+ES1371_REG_CONTROL);
spin_unlock_irqrestore(&s->lock, flags);
}
static inline void stop_dac1(struct es1371_state *s)
{
unsigned long flags;
spin_lock_irqsave(&s->lock, flags);
s->ctrl &= ~CTRL_DAC1_EN;
outl(s->ctrl, s->io+ES1371_REG_CONTROL);
spin_unlock_irqrestore(&s->lock, flags);
}
static inline void stop_dac2(struct es1371_state *s)
{
unsigned long flags;
spin_lock_irqsave(&s->lock, flags);
s->ctrl &= ~CTRL_DAC2_EN;
outl(s->ctrl, s->io+ES1371_REG_CONTROL);
spin_unlock_irqrestore(&s->lock, flags);
}
static void start_dac1(struct es1371_state *s)
{
unsigned long flags;
unsigned fragremain, fshift;
spin_lock_irqsave(&s->lock, flags);
if (!(s->ctrl & CTRL_DAC1_EN) && (s->dma_dac1.mapped || s->dma_dac1.count > 0)
&& s->dma_dac1.ready) {
s->ctrl |= CTRL_DAC1_EN;
s->sctrl = (s->sctrl & ~(SCTRL_P1LOOPSEL | SCTRL_P1PAUSE | SCTRL_P1SCTRLD)) | SCTRL_P1INTEN;
outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
fragremain = ((- s->dma_dac1.hwptr) & (s->dma_dac1.fragsize-1));
fshift = sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
if (fragremain < 2*fshift)
fragremain = s->dma_dac1.fragsize;
outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
outl(s->ctrl, s->io+ES1371_REG_CONTROL);
outl((s->dma_dac1.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
}
spin_unlock_irqrestore(&s->lock, flags);
}
static void start_dac2(struct es1371_state *s)
{
unsigned long flags;
unsigned fragremain, fshift;
spin_lock_irqsave(&s->lock, flags);
if (!(s->ctrl & CTRL_DAC2_EN) && (s->dma_dac2.mapped || s->dma_dac2.count > 0)
&& s->dma_dac2.ready) {
s->ctrl |= CTRL_DAC2_EN;
s->sctrl = (s->sctrl & ~(SCTRL_P2LOOPSEL | SCTRL_P2PAUSE | SCTRL_P2DACSEN |
SCTRL_P2ENDINC | SCTRL_P2STINC)) | SCTRL_P2INTEN |
(((s->sctrl & SCTRL_P2FMT) ? 2 : 1) << SCTRL_SH_P2ENDINC) |
(0 << SCTRL_SH_P2STINC);
outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
fragremain = ((- s->dma_dac2.hwptr) & (s->dma_dac2.fragsize-1));
fshift = sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
if (fragremain < 2*fshift)
fragremain = s->dma_dac2.fragsize;
outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
outl(s->ctrl, s->io+ES1371_REG_CONTROL);
outl((s->dma_dac2.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
}
spin_unlock_irqrestore(&s->lock, flags);
}
static void start_adc(struct es1371_state *s)
{
unsigned long flags;
unsigned fragremain, fshift;
spin_lock_irqsave(&s->lock, flags);
if (!(s->ctrl & CTRL_ADC_EN) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
&& s->dma_adc.ready) {
s->ctrl |= CTRL_ADC_EN;
s->sctrl = (s->sctrl & ~SCTRL_R1LOOPSEL) | SCTRL_R1INTEN;
outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
fragremain = ((- s->dma_adc.hwptr) & (s->dma_adc.fragsize-1));
fshift = sample_shift[(s->sctrl & SCTRL_R1FMT) >> SCTRL_SH_R1FMT];
if (fragremain < 2*fshift)
fragremain = s->dma_adc.fragsize;
outl((fragremain >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
outl(s->ctrl, s->io+ES1371_REG_CONTROL);
outl((s->dma_adc.fragsize >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
}
spin_unlock_irqrestore(&s->lock, flags);
}
/* --------------------------------------------------------------------- */
#define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
#define DMABUF_MINORDER 1
static inline void dealloc_dmabuf(struct es1371_state *s, struct dmabuf *db)
{
struct page *page, *pend;
if (db->rawbuf) {
/* undo marking the pages as reserved */
pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
for (page = virt_to_page(db->rawbuf); page <= pend; page++)
ClearPageReserved(page);
pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
}
db->rawbuf = NULL;
db->mapped = db->ready = 0;
}
static int prog_dmabuf(struct es1371_state *s, struct dmabuf *db, unsigned rate, unsigned fmt, unsigned reg)
{
int order;
unsigned bytepersec;
unsigned bufs;
struct page *page, *pend;
db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
if (!db->rawbuf) {
db->ready = db->mapped = 0;
for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
break;
if (!db->rawbuf)
return -ENOMEM;
db->buforder = order;
/* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */
pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
for (page = virt_to_page(db->rawbuf); page <= pend; page++)
SetPageReserved(page);
}
fmt &= ES1371_FMT_MASK;
bytepersec = rate << sample_shift[fmt];
bufs = PAGE_SIZE << db->buforder;
if (db->ossfragshift) {
if ((1000 << db->ossfragshift) < bytepersec)
db->fragshift = ld2(bytepersec/1000);
else
db->fragshift = db->ossfragshift;
} else {
db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
if (db->fragshift < 3)
db->fragshift = 3;
}
db->numfrag = bufs >> db->fragshift;
while (db->numfrag < 4 && db->fragshift > 3) {
db->fragshift--;
db->numfrag = bufs >> db->fragshift;
}
db->fragsize = 1 << db->fragshift;
if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
db->numfrag = db->ossmaxfrags;
db->fragsamples = db->fragsize >> sample_shift[fmt];
db->dmasize = db->numfrag << db->fragshift;
memset(db->rawbuf, (fmt & ES1371_FMT_S16) ? 0 : 0x80, db->dmasize);
outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
outl(db->dmaaddr, s->io+(reg & 0xff));
outl((db->dmasize >> 2)-1, s->io+((reg + 4) & 0xff));
db->enabled = 1;
db->ready = 1;
return 0;
}
static inline int prog_dmabuf_adc(struct es1371_state *s)
{
stop_adc(s);
return prog_dmabuf(s, &s->dma_adc, s->adcrate, (s->sctrl >> SCTRL_SH_R1FMT) & ES1371_FMT_MASK,
ES1371_REG_ADC_FRAMEADR);
}
static inline int prog_dmabuf_dac2(struct es1371_state *s)
{
stop_dac2(s);
return prog_dmabuf(s, &s->dma_dac2, s->dac2rate, (s->sctrl >> SCTRL_SH_P2FMT) & ES1371_FMT_MASK,
ES1371_REG_DAC2_FRAMEADR);
}
static inline int prog_dmabuf_dac1(struct es1371_state *s)
{
stop_dac1(s);
return prog_dmabuf(s, &s->dma_dac1, s->dac1rate, (s->sctrl >> SCTRL_SH_P1FMT) & ES1371_FMT_MASK,
ES1371_REG_DAC1_FRAMEADR);
}
static inline unsigned get_hwptr(struct es1371_state *s, struct dmabuf *db, unsigned reg)
{
unsigned hwptr, diff;
outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
hwptr = (inl(s->io+(reg & 0xff)) >> 14) & 0x3fffc;
diff = (db->dmasize + hwptr - db->hwptr) % db->dmasize;
db->hwptr = hwptr;
return diff;
}
static inline void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c)
{
if (bptr + len > bsize) {
unsigned x = bsize - bptr;
memset(((char *)buf) + bptr, c, x);
bptr = 0;
len -= x;
}
memset(((char *)buf) + bptr, c, len);
}
/* call with spinlock held! */
static void es1371_update_ptr(struct es1371_state *s)
{
int diff;
/* update ADC pointer */
if (s->ctrl & CTRL_ADC_EN) {
diff = get_hwptr(s, &s->dma_adc, ES1371_REG_ADC_FRAMECNT);