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Commit 5b84193

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eyckeyck
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fixes PMP size for tests
1 parent 6c80009 commit 5b84193

2 files changed

Lines changed: 23 additions & 16 deletions

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‎.github/workflows/ci.yml‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -97,8 +97,8 @@ jobs:
9797
LD_LIBRARY_PATH=. ./riscv-sim -f pmp_csr_test --isa rv64gc_m --backend interp || rc=$?
9898
[ "${rc:-0}" -eq 2 ]
9999
100-
- name: rv64gc_mp CSR test - interp (with PMP)
101-
run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_csr_test --isa rv64gc_mp --backend interp
100+
- name: rv64gc_mp_64 CSR test - interp (with PMP)
101+
run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_csr_test --isa rv64gc_mp_64 --backend interp
102102

103103
- name: Build PMP enforcement test firmware
104104
run: |
@@ -107,8 +107,8 @@ jobs:
107107
-o pmp_enforce_test \
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contrib/fw/pmp-enforce-test/pmp_enforce_test.S
109109
110-
- name: rv64gc_mp enforcement test - interp
111-
run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_enforce_test --isa rv64gc_mp --backend interp
110+
- name: rv64gc_mp_64 enforcement test - interp
111+
run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_enforce_test --isa rv64gc_mp_64 --backend interp
112112

113113
- name: Build PMP shift test firmware
114114
run: |
@@ -117,8 +117,8 @@ jobs:
117117
-o pmp_shift_test \
118118
contrib/fw/pmp-shift-test/pmp_shift_test.S
119119
120-
- name: rv64gc_mp shift test - interp
121-
run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_shift_test --isa rv64gc_mp --backend interp
120+
- name: rv64gc_mp_64 shift test - interp
121+
run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_shift_test --isa rv64gc_mp_64 --backend interp
122122

123123
- name: Build PMP upper-cfg test firmware
124124
run: |
@@ -127,8 +127,8 @@ jobs:
127127
-o pmp_upper_cfg_test \
128128
contrib/fw/pmp-upper-cfg-test/pmp_upper_cfg_test.S
129129
130-
- name: rv64gc_mp upper-cfg test - interp
131-
run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_upper_cfg_test --isa rv64gc_mp --backend interp
130+
- name: rv64gc_mp_64 upper-cfg test - interp
131+
run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_upper_cfg_test --isa rv64gc_mp_64 --backend interp
132132

133133
- name: Build PMP cfg2 test firmware
134134
run: |
@@ -137,8 +137,8 @@ jobs:
137137
-o pmp_cfg2_test \
138138
contrib/fw/pmp-cfg2-test/pmp_cfg2_test.S
139139
140-
- name: rv64gc_mp cfg2 test - interp
141-
run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_cfg2_test --isa rv64gc_mp --backend interp
140+
- name: rv64gc_mp_64 cfg2 test - interp
141+
run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_cfg2_test --isa rv64gc_mp_64 --backend interp
142142

143143
- name: Build PMP TOR test firmware
144144
run: |
@@ -147,8 +147,8 @@ jobs:
147147
-o pmp_tor_test \
148148
contrib/fw/pmp-tor-test/pmp_tor_test.S
149149
150-
- name: rv64gc_mp TOR test - interp
151-
run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_tor_test --isa rv64gc_mp --backend interp
150+
- name: rv64gc_mp_64 TOR test - interp
151+
run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_tor_test --isa rv64gc_mp_64 --backend interp
152152

153153
- name: Build PMP 64-entry pmpaddr test firmware
154154
run: |
@@ -157,8 +157,8 @@ jobs:
157157
-o pmp_64entry_addr_test \
158158
contrib/fw/pmp-64entry-addr-test/pmp_64entry_addr_test.S
159159
160-
- name: rv64gc_mp 64-entry pmpaddr test - interp
161-
run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_64entry_addr_test --isa rv64gc_mp --backend interp
160+
- name: rv64gc_mp_64 64-entry pmpaddr test - interp
161+
run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_64entry_addr_test --isa rv64gc_mp_64 --backend interp
162162

163163
- name: Build PMP 64-entry pmpcfg test firmware
164164
run: |
@@ -167,8 +167,8 @@ jobs:
167167
-o pmp_64entry_cfg_test \
168168
contrib/fw/pmp-64entry-cfg-test/pmp_64entry_cfg_test.S
169169
170-
- name: rv64gc_mp 64-entry pmpcfg test - interp
171-
run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_64entry_cfg_test --isa rv64gc_mp --backend interp
170+
- name: rv64gc_mp_64 64-entry pmpcfg test - interp
171+
run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_64entry_cfg_test --isa rv64gc_mp_64 --backend interp
172172

173173
- name: Build PMP 8-entry guard test firmware (VP/S5 model)
174174
run: |

‎src/sysc/register_cores.cpp‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -132,6 +132,13 @@ __attribute__((used)) volatile std::array<bool, 20> riscv_init = {
132132
std::make_unique<iss::mem::pmp<iss::arch::rv64gc>>(cpu->get_priv_if()));
133133
return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast<arch::rv64gc*>(cpu), gdb_port)}};
134134
}),
135+
iss_factory::instance().register_creator("rv64gc_mp_64:interp",
136+
[](unsigned gdb_port, sysc::riscv::core_complex_if* cc) -> iss_factory::base_t {
137+
auto* cpu = new core2sc_adapter<arch::riscv_hart_m_p<arch::rv64gc>>(cc);
138+
cpu->memories.insert_before_last(
139+
std::make_unique<iss::mem::pmp<iss::arch::rv64gc, 64>>(cpu->get_priv_if()));
140+
return {sysc::core_ptr{cpu}, vm_ptr{create(static_cast<arch::rv64gc*>(cpu), gdb_port)}};
141+
}),
135142
iss_factory::instance().register_creator("rv64gc_mp_8:interp",
136143
[](unsigned gdb_port, sysc::riscv::core_complex_if* cc) -> iss_factory::base_t {
137144
auto* cpu = new core2sc_adapter<arch::riscv_hart_m_p<arch::rv64gc>>(cc);

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