tag:github.com,2008:https://github.com/MicrochipTech/fpga-hls-examples/releases Release notes from fpga-hls-examples 2025-06-25T13:38:18Z tag:github.com,2008:Repository/367125027/2025.1 2025-07-03T18:46:54Z 2025.1 <h1>fpga-hls-examples 2025.1</h1> <h2>Changes since last release (v2024.1)</h2> <p>• Added SHLS examples to demonstrate <a href="https://github.com/MicrochipTech/fpga-hls-examples/tree/main/ECC_demo">Error Correction Code</a> and <a href="https://github.com/MicrochipTech/fpga-hls-examples/tree/main/auto_instrument">Automatic On-Chip Instrumentation</a> functionality<br> • (Canny RISC-V) Added an <a href="https://github.com/MicrochipTech/fpga-hls-examples/tree/main/Canny_RISCV">example</a> demonstrating how to design an SHLS module with input and output FIFOs in a RISC-V environment<br> • Updated source code and documentation for trainings to compile with Libero/SmartHLS 2025.1<br> • Included pre-generated .job files for trainings compiled with Libero 2025.1<br> • Moved LFS files to Release Assets</p> <h3>Known Issues:</h3> <ul> <li>For the auto instrumentation example: <ul> <li>If run using Windows, you may see the error "Error: can't read "merged_file": no such variable". To fix this, open <code>C:\Microchip\Libero_SoC_2025.1\SmartHLS\SmartHLS\examples\scripts\utils\instrument\update_vcd.tcl</code>. On line 198, change "$merged_file" to "$vcdFile".</li> <li>If run on Windows or Linux, Modelsim may display the error message saying "....clken" signals were not found. To solve this issue, go to line 257 of <code>C:\Microchip\Libero_SoC_2025.1\SmartHLS\SmartHLS\lib\python\instrumentation\read_vcd.py</code> and change "clk" to "clk$".</li> <li>These issues will be addressed in the next release of Libero.</li> </ul> </li> </ul> dheepk-mchp tag:github.com,2008:Repository/367125027/2024.1 2025-06-19T16:32:22Z 2025.1 <h1>fpga-hls-examples 2025.1</h1> <h2>Changes since last release (v2024.1)</h2> <ul> <li>Updated source code and documentation for trainings to compile with Libero/SmartHLS 2025.1.</li> <li>Included pre-generated .job files for trainings compiled with Libero 2025.1.</li> <li>Included the LFS files as part of precompiled libraries in Assets</li> </ul> jennifermah76 tag:github.com,2008:Repository/367125027/2023.2 2023-09-11T19:41:24Z 2023.2 <ul> <li>Updated Training documents for SmartHLS 2023.2</li> <li>Added examples of the SmartHLS dataflow feature into Trainings 1 and 2</li> <li>Added a 4th training covering the SmartHLS PolarFire SoC flow. Targets either the Icicle kit reference design or a custom design.</li> </ul> andrewcanisMCHP