diff --git a/.gitignore b/.gitignore index d47ecbb26d72a..5a7224ce19f91 100644 --- a/.gitignore +++ b/.gitignore @@ -115,5 +115,8 @@ all.config # Kdevelop4 *.kdev4 +#audio-kernel +techpack/audio/ + # fetched Android config fragments kernel/configs/android-*.cfg diff --git a/Documentation/devicetree/bindings/arm/msm/msm_watchdog.txt b/Documentation/devicetree/bindings/arm/msm/msm_watchdog.txt index 53ad68e2e1b29..33ac152728fc5 100644 --- a/Documentation/devicetree/bindings/arm/msm/msm_watchdog.txt +++ b/Documentation/devicetree/bindings/arm/msm/msm_watchdog.txt @@ -33,6 +33,7 @@ Optional properties: - qcom,ipi-ping : (boolean) send keep alive ping to other cpus if present - qcom,wakeup-enable : (boolean) enable non secure watchdog to freeze / unfreeze automatically across suspend / resume path. +- qcom,scandump-size : size of scan dump memory region Example: diff --git a/Documentation/devicetree/bindings/arm/msm/rpmh-master-stat.txt b/Documentation/devicetree/bindings/arm/msm/rpmh-master-stat.txt deleted file mode 100644 index 36e1a69c564fe..0000000000000 --- a/Documentation/devicetree/bindings/arm/msm/rpmh-master-stat.txt +++ /dev/null @@ -1,18 +0,0 @@ -* RPMH Master Stats - -Differet Subsystems maintains master data in SMEM. -It tells about the individual masters information at any given -time like "system sleep counts", "system sleep last entered at" -and "system sleep accumulated duration" etc. These stats can be -show to the user using the debugfs interface of the kernel. -To achieve this, device tree node has been added. - -The required properties for rpmh-master-stats are: - -- compatible: "qcom,rpmh-master-stats". - -Example: - -qcom,rpmh-master-stats { - compatible = "qcom,rpmh-master-stats"; -}; diff --git a/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt b/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt index 176f9e115b423..b327a4226768d 100644 --- a/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt +++ b/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt @@ -254,6 +254,23 @@ Example: pinctrl-1 = <&led_disable>; }; + pmi8998_flashlight: qcom,flashlight { + label = "flash"; + qcom,led-name = "flashlight"; + qcom,max-current = <750>; + qcom,default-led-trigger = + "flashlight_trigger"; + qcom,id = <3>; + qcom,current-ma = <500>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + pinctrl-names = "led_enable","led_disable"; + pinctrl-0 = <&led_enable>; + pinctrl-1 = <&led_disable>; + }; + pmi8998_torch0: qcom,torch_0 { label = "torch"; qcom,led-name = "led:torch_0"; diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-lrme.txt b/Documentation/devicetree/bindings/media/video/msm-cam-lrme.txt deleted file mode 100644 index 9a37922dd93a1..0000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-cam-lrme.txt +++ /dev/null @@ -1,149 +0,0 @@ -* Qualcomm Technologies, Inc. MSM Camera LRME - -The MSM camera Low Resolution Motion Estimation device provides dependency -definitions for enabling Camera LRME HW. MSM camera LRME is implemented in -multiple device nodes. The root LRME device node has properties defined to -hint the driver about the LRME HW nodes available during the probe sequence. -Each node has multiple properties defined for interrupts, clocks and -regulators. - -======================= -Required Node Structure -======================= -LRME root interface node takes care of the handling LRME high level -driver handling and controls underlying LRME hardware present. - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,cam-lrme" - -- compat-hw-name - Usage: required - Value type: - Definition: Should be "qcom,lrme" - -- num-lrme - Usage: required - Value type: - Definition: Number of supported LRME HW blocks - -Example: - qcom,cam-lrme { - compatible = "qcom,cam-lrme"; - compat-hw-name = "qcom,lrme"; - num-lrme = <1>; - }; - -======================= -Required Node Structure -======================= -LRME Node provides interface for Low Resolution Motion Estimation hardware -driver about the device register map, interrupt map, clocks, regulators. - -- cell-index - Usage: required - Value type: - Definition: Node instance number - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,lrme" - -- reg-names - Usage: optional - Value type: - Definition: Name of the register resources - -- reg - Usage: optional - Value type: - Definition: Register values - -- reg-cam-base - Usage: optional - Value type: - Definition: Offset of the register space compared to - to Camera base register space - -- interrupt-names - Usage: optional - Value type: - Definition: Name of the interrupt - -- interrupts - Usage: optional - Value type: - Definition: Interrupt line associated with LRME HW - -- regulator-names - Usage: required - Value type: - Definition: Name of the regulator resources for LRME HW - -- camss-supply - Usage: required - Value type: - Definition: Regulator reference corresponding to the names listed - in "regulator-names" - -- clock-names - Usage: required - Value type: - Definition: List of clock names required for LRME HW - -- clocks - Usage: required - Value type: - Definition: List of clocks required for LRME HW - -- clock-rates - Usage: required - Value type: - Definition: List of clocks rates - -- clock-cntl-level - Usage: required - Value type: - Definition: List of strings corresponds clock-rates levels - Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo - -- src-clock-name - Usage: required - Value type: - Definition: Source clock name - -Examples: - cam_lrme: qcom,lrme@ac6b000 { - cell-index = <0>; - compatible = "qcom,lrme"; - reg-names = "lrme"; - reg = <0xac6b000 0xa00>; - reg-cam-base = <0x6b000>; - interrupt-names = "lrme"; - interrupts = <0 476 0>; - regulator-names = "camss"; - camss-supply = <&titan_top_gdsc>; - clock-names = "camera_ahb", - "camera_axi", - "soc_ahb_clk", - "cpas_ahb_clk", - "camnoc_axi_clk", - "lrme_clk_src", - "lrme_clk"; - clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, - <&clock_gcc GCC_CAMERA_AXI_CLK>, - <&clock_camcc CAM_CC_SOC_AHB_CLK>, - <&clock_camcc CAM_CC_CPAS_AHB_CLK>, - <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, - <&clock_camcc CAM_CC_LRME_CLK_SRC>, - <&clock_camcc CAM_CC_LRME_CLK>; - clock-rates = <0 0 0 0 0 0 0>, - <0 0 0 0 0 19200000 19200000>, - <0 0 0 0 0 19200000 19200000>, - <0 0 0 0 0 19200000 19200000>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; - src-clock-name = "lrme_core_clk_src"; - }; - diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen3.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen3.txt index f50fd88894c68..75996a57f2090 100644 --- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen3.txt +++ b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-fg-gen3.txt @@ -104,6 +104,13 @@ First Level Node - FG Gen3 device this property is not specified, then the default value used will be 75mA. +- qcom,fg-cutoff-current + Usage: optional + Value type: + Definition: Minimum Battery current (in mA) used for cutoff SOC + estimate. If this property is not specified, then a default + value of 500 mA will be applied. + - qcom,fg-delta-soc-thr Usage: optional Value type: diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index a37e441ede16e..0035ea0ffcd65 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -315,3 +315,5 @@ zarlink Zarlink Semiconductor zii Zodiac Inflight Innovations zte ZTE Corp. zyxel ZyXEL Communications Corp. +ssp Bcm4775 +ssp,bcm4775 broadcom 4775 gps chip diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index f13ae153fb246..d2315ffd8f126 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h @@ -112,8 +112,12 @@ int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); #define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE 4096 -/* This is the base location for PIE (ET_DYN with INTERP) loads. */ -#define ELF_ET_DYN_BASE 0x400000UL +/* This is the location that an ET_DYN program is loaded if exec'ed. Typical + use of this is to invoke "./ld.so someprog" to test out a new version of + the loader. We need to make sure that it is out of the way of the program + that it will "exec", and that there is sufficient room for the brk. */ + +#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2) /* When the program starts, a1 contains a pointer to a function to be registered with atexit, as per the SVR4 ABI. A value of 0 means we diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h index d10e362354389..a58bbaa3ec603 100644 --- a/arch/arm/include/asm/kvm_mmu.h +++ b/arch/arm/include/asm/kvm_mmu.h @@ -223,16 +223,6 @@ static inline unsigned int kvm_get_vmid_bits(void) return 8; } -static inline void *kvm_get_hyp_vector(void) -{ - return kvm_ksym_ref(__kvm_hyp_vector); -} - -static inline int kvm_map_vectors(void) -{ - return 0; -} - #endif /* !__ASSEMBLY__ */ #endif /* __ARM_KVM_MMU_H__ */ diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 32a80d6e40457..22c3842a576f9 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -781,34 +781,6 @@ config FORCE_MAX_ZONEORDER However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 4M allocations matching the default size used by generic code. -config UNMAP_KERNEL_AT_EL0 - bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT - default y - help - Speculation attacks against some high-performance processors can - be used to bypass MMU permission checks and leak kernel data to - userspace. This can be defended against by unmapping the kernel - when running in userspace, mapping it back in on exception entry - via a trampoline page in the vector table. - - If unsure, say Y. - -config HARDEN_BRANCH_PREDICTOR - bool "Harden the branch predictor against aliasing attacks" if EXPERT - help - Speculation attacks against some high-performance processors rely on - being able to manipulate the branch predictor for a victim context by - executing aliasing branches in the attacker context. Such attacks - can be partially mitigated against by clearing internal branch - predictor state and limiting the prediction logic in some situations. - - This config option will take CPU-specific actions to harden the - branch predictor against aliasing attacks and may rely on specific - instruction sequences or control bits being set by the system - firmware. - - If unsure, say Y. - menuconfig ARMV8_DEPRECATED bool "Emulate deprecated/obsolete ARMv8 instructions" depends on COMPAT @@ -1218,3 +1190,10 @@ source "arch/arm64/crypto/Kconfig" endif source "lib/Kconfig" + +config BOOT_INFO + bool "Boot information from bootloader" + default y + help + On embedded linux device, we try to collect more information from + bootloader to kernel. eg. powerup reason. diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index eaa15ce3c72d9..775cb6dcec0ac 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -1,86 +1,36 @@ -dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb msm8916-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb - ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SDM845) += \ - sdm845-cdp-overlay.dtbo \ sdm845-mtp-overlay.dtbo \ - sdm845-qrd-overlay.dtbo \ - sdm845-4k-panel-mtp-overlay.dtbo \ - sdm845-4k-panel-cdp-overlay.dtbo \ - sdm845-4k-panel-qrd-overlay.dtbo \ - sdm845-v2-qvr-overlay.dtbo \ - sdm845-v2-cdp-overlay.dtbo \ sdm845-v2-mtp-overlay.dtbo \ - sdm845-v2-qrd-overlay.dtbo \ - sdm845-v2-4k-panel-mtp-overlay.dtbo \ - sdm845-v2-4k-panel-cdp-overlay.dtbo \ - sdm845-v2-4k-panel-qrd-overlay.dtbo \ - sdm845-v2.1-cdp-overlay.dtbo \ sdm845-v2.1-mtp-overlay.dtbo \ - sdm845-v2.1-qrd-overlay.dtbo \ - sdm845-v2.1-4k-panel-mtp-overlay.dtbo \ - sdm845-v2.1-4k-panel-cdp-overlay.dtbo \ - sdm845-v2.1-4k-panel-qrd-overlay.dtbo \ - sda845-cdp-overlay.dtbo \ - sda845-mtp-overlay.dtbo \ - sda845-qrd-overlay.dtbo \ - sda845-4k-panel-mtp-overlay.dtbo \ - sda845-4k-panel-cdp-overlay.dtbo \ - sda845-4k-panel-qrd-overlay.dtbo \ - sda845-v2-cdp-overlay.dtbo \ - sda845-v2-mtp-overlay.dtbo \ - sda845-v2-qrd-overlay.dtbo \ - sda845-v2-hdk-overlay.dtbo \ - sda845-v2-4k-panel-mtp-overlay.dtbo \ - sda845-v2-4k-panel-cdp-overlay.dtbo \ - sda845-v2-4k-panel-qrd-overlay.dtbo \ - sda845-v2.1-cdp-overlay.dtbo \ - sda845-v2.1-mtp-overlay.dtbo \ - sda845-v2.1-qrd-overlay.dtbo \ - sda845-v2.1-4k-panel-cdp-overlay.dtbo \ - sda845-v2.1-4k-panel-mtp-overlay.dtbo \ - sda845-v2.1-4k-panel-qrd-overlay.dtbo + polaris-p0-overlay.dtbo \ + polaris-p0-v2-overlay.dtbo \ + polaris-p1-overlay.dtbo \ + polaris-p1-v2-overlay.dtbo \ + polaris-p1-v2.1-overlay.dtbo \ + polaris-p2-overlay.dtbo \ + polaris-p2-v2-overlay.dtbo \ + polaris-p2-v2.1-overlay.dtbo \ + polaris-p3-overlay.dtbo \ + polaris-p3-v2-overlay.dtbo \ + polaris-p3-v2.1-overlay.dtbo -sdm845-cdp-overlay.dtbo-base := sdm845.dtb sdm845-mtp-overlay.dtbo-base := sdm845.dtb -sdm845-qrd-overlay.dtbo-base := sdm845.dtb -sdm845-4k-panel-mtp-overlay.dtbo-base := sdm845.dtb -sdm845-4k-panel-cdp-overlay.dtbo-base := sdm845.dtb -sdm845-4k-panel-qrd-overlay.dtbo-base := sdm845.dtb -sdm845-v2-qvr-overlay.dtbo-base := sdm845-v2.dtb -sdm845-v2-cdp-overlay.dtbo-base := sdm845-v2.dtb sdm845-v2-mtp-overlay.dtbo-base := sdm845-v2.dtb -sdm845-v2-qrd-overlay.dtbo-base := sdm845-v2.dtb -sdm845-v2-4k-panel-mtp-overlay.dtbo-base := sdm845-v2.dtb -sdm845-v2-4k-panel-cdp-overlay.dtbo-base := sdm845-v2.dtb -sdm845-v2-4k-panel-qrd-overlay.dtbo-base := sdm845-v2.dtb -sdm845-v2.1-cdp-overlay.dtbo-base := sdm845-v2.1.dtb sdm845-v2.1-mtp-overlay.dtbo-base := sdm845-v2.1.dtb -sdm845-v2.1-qrd-overlay.dtbo-base := sdm845-v2.1.dtb -sdm845-v2.1-4k-panel-mtp-overlay.dtbo-base := sdm845-v2.1.dtb -sdm845-v2.1-4k-panel-cdp-overlay.dtbo-base := sdm845-v2.1.dtb -sdm845-v2.1-4k-panel-qrd-overlay.dtbo-base := sdm845-v2.1.dtb -sda845-cdp-overlay.dtbo-base := sda845.dtb -sda845-mtp-overlay.dtbo-base := sda845.dtb -sda845-qrd-overlay.dtbo-base := sda845.dtb -sda845-4k-panel-mtp-overlay.dtbo-base := sda845.dtb -sda845-4k-panel-cdp-overlay.dtbo-base := sda845.dtb -sda845-4k-panel-qrd-overlay.dtbo-base := sda845.dtb -sda845-v2-cdp-overlay.dtbo-base := sda845-v2.dtb -sda845-v2-mtp-overlay.dtbo-base := sda845-v2.dtb -sda845-v2-qrd-overlay.dtbo-base := sda845-v2.dtb -sda845-v2-hdk-overlay.dtbo-base := sda845-v2.dtb -sda845-v2-4k-panel-mtp-overlay.dtbo-base := sda845-v2.dtb -sda845-v2-4k-panel-cdp-overlay.dtbo-base := sda845-v2.dtb -sda845-v2-4k-panel-qrd-overlay.dtbo-base := sda845-v2.dtb -sda845-v2.1-cdp-overlay.dtbo-base := sda845-v2.1.dtb -sda845-v2.1-mtp-overlay.dtbo-base := sda845-v2.1.dtb -sda845-v2.1-qrd-overlay.dtbo-base := sda845-v2.1.dtb -sda845-v2.1-4k-panel-cdp-overlay.dtbo-base := sda845-v2.1.dtb -sda845-v2.1-4k-panel-mtp-overlay.dtbo-base := sda845-v2.1.dtb -sda845-v2.1-4k-panel-qrd-overlay.dtbo-base := sda845-v2.1.dtb + +polaris-p0-overlay.dtbo-base := sdm845.dtb +polaris-p0-v2-overlay.dtbo-base := sdm845-v2.dtb +polaris-p1-overlay.dtbo-base := sdm845.dtb +polaris-p1-v2-overlay.dtbo-base := sdm845-v2.dtb +polaris-p1-v2.1-overlay.dtbo-base := sdm845-v2.1.dtb +polaris-p2-overlay.dtbo-base := sdm845.dtb +polaris-p2-v2-overlay.dtbo-base := sdm845-v2.dtb +polaris-p2-v2.1-overlay.dtbo-base := sdm845-v2.1.dtb +polaris-p3-overlay.dtbo-base := sdm845.dtb +polaris-p3-v2-overlay.dtbo-base := sdm845-v2.dtb +polaris-p3-v2.1-overlay.dtbo-base := sdm845-v2.1.dtb + else dtb-$(CONFIG_ARCH_SDM845) += sdm845-sim.dtb \ sdm845-rumi.dtb \ @@ -95,8 +45,20 @@ dtb-$(CONFIG_ARCH_SDM845) += sdm845-sim.dtb \ sdm845-4k-panel-mtp.dtb \ sdm845-4k-panel-cdp.dtb \ sdm845-4k-panel-qrd.dtb \ - sdm845-interposer-sdm670-mtp.dtb \ - sdm845-interposer-sdm670-cdp.dtb + polaris-p0.dtb \ + polaris-p0-v2.dtb \ + polaris-p1.dtb \ + polaris-p1-v2.dtb \ + polaris-p1-v2.1.dtb \ + polaris-p2.dtb \ + polaris-p2-v2.dtb \ + polaris-p2-v2.1.dtb \ + polaris-p3.dtb \ + polaris-p3-v2.dtb \ + polaris-p3-v2.1.dtb \ + polaris-mp.dtb \ + polaris-mp-v2.dtb \ + polaris-mp-v2.1.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/arch/arm64/boot/dts/qcom/batterydata-d5-atl-3400mAh.dtsi b/arch/arm64/boot/dts/qcom/batterydata-d5-atl-3400mAh.dtsi new file mode 100644 index 0000000000000..2c87ca5d03d2d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/batterydata-d5-atl-3400mAh.dtsi @@ -0,0 +1,78 @@ + +qcom,d5_atl_3400mah { + qcom,max-voltage-uv = <4400000>; + qcom,fastchg-current-ma = <3300>; + qcom,nom-batt-capacity-mah = <3400>; + qcom,fg-cc-cv-threshold-mv = <4390>; + qcom,batt-id-kohm = <68>; + qcom,battery-beta = <3380>; + qcom,battery-type = "d5_atl"; + qcom,jeita-fcc-ranges = <0 50 330000 + 51 150 990000 + 151 450 3300000 + 451 600 1650000>; + qcom,jeita-fv-ranges = <0 50 4400000 + 51 150 4400000 + 151 450 4400000 + 451 600 4100000>; + qcom,checksum = <0xE38B>; + qcom,gui-version = "PMI8998GUI - 2.0.0.58"; + qcom,fg-profile-data = [ + 6C 1F B7 05 + 69 0A AD FC + 7B 1D 4A 07 + 48 12 15 14 + 7E 18 52 23 + F9 44 C2 53 + 55 00 00 00 + 0E 00 00 00 + 00 00 FC 07 + C6 C5 D8 C2 + 20 00 08 00 + 04 D3 CA E4 + F7 F4 CB EA + 77 01 C7 0B + 05 FC D9 2A + 18 06 09 20 + 27 00 14 00 + 48 1D 4E E3 + 8D FA 54 CC + EF 1C 68 02 + 3F 0D 89 0A + FA 19 D3 1B + 3E 3D B2 4A + 70 00 00 00 + 12 00 00 00 + 00 00 05 CC + D8 C2 27 C3 + 1B 00 00 00 + D7 EA CA E4 + 26 EC 52 E3 + 85 00 70 03 + 83 03 0F 1B + B3 33 CC FF + 07 10 00 00 + 4A 0D 66 46 + 1B 00 40 00 + 49 01 0A FA + FF 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/batterydata-d5-cos-3400mAh.dtsi b/arch/arm64/boot/dts/qcom/batterydata-d5-cos-3400mAh.dtsi new file mode 100644 index 0000000000000..56c5133d8cc42 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/batterydata-d5-cos-3400mAh.dtsi @@ -0,0 +1,78 @@ + +qcom,d5_cos_3400mah { + qcom,max-voltage-uv = <4400000>; + qcom,fastchg-current-ma = <3300>; + qcom,nom-batt-capacity-mah = <3400>; + qcom,fg-cc-cv-threshold-mv = <4390>; + qcom,batt-id-kohm = <100>; + qcom,battery-beta = <3380>; + qcom,battery-type = "d5_cos"; + qcom,jeita-fcc-ranges = <0 50 330000 + 51 150 990000 + 151 450 3300000 + 451 600 1650000>; + qcom,jeita-fv-ranges = <0 50 4400000 + 51 150 4400000 + 151 450 4400000 + 451 600 4100000>; + qcom,checksum = <0x5B7D>; + qcom,gui-version = "PMI8998GUI - 2.0.0.58"; + qcom,fg-profile-data = [ + 80 1F 9B 05 + 7F 0A 89 FC + 69 1D 47 EC + F8 0B 8B 14 + 95 19 17 22 + FE 3C E7 4A + 57 00 00 00 + 17 00 00 00 + 00 00 E8 C4 + AC C5 06 BB + 1F 00 08 00 + 1C DA 06 E5 + BD F5 22 E3 + A7 F2 E9 03 + 0C 04 38 1D + 19 06 09 20 + 27 00 14 00 + 14 1E 37 F5 + 95 02 7F F5 + EF 1C 5A 02 + 4B 0D 98 0A + 1C 1A 71 1B + B7 3D 06 4A + 70 00 00 00 + 11 00 00 00 + 00 00 A9 CC + 89 BB 9D BA + 1A 00 00 00 + 73 EA 06 E5 + BA EC 2C 00 + 5D FA 47 0A + 81 EA A4 1A + A1 33 CC FF + 07 10 00 00 + 34 0D 66 46 + 1A 00 40 00 + 49 01 0A FA + FF 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/batterydata-itech-3020mAh.dtsi b/arch/arm64/boot/dts/qcom/batterydata-itech-3020mAh.dtsi new file mode 100644 index 0000000000000..374b846fb2563 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/batterydata-itech-3020mAh.dtsi @@ -0,0 +1,54 @@ +/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,itech-3020mah { + qcom,max-voltage-uv = <4400000>; + qcom,v-cutoff-uv = <3400000>; + qcom,chg-term-ua = <100000>; + qcom,batt-id-kohm = <150>; + qcom,battery-type = "itech_3020mah"; + qcom,fg-profile-data = [ + E8 83 0C 7D + E9 80 B2 76 + 20 83 40 73 + D7 6C 59 7E + FB 81 58 93 + 0D AE 02 B1 + 5B 12 D7 82 + 86 78 F3 76 + 4A 71 0C 83 + 1B 80 73 8D + 49 89 07 82 + D8 99 79 BC + AA C8 7C 17 + F8 0B F4 5B + CE 6E 71 FD + 09 2E 79 44 + 52 43 00 00 + DE 3D 2A 37 + D3 46 00 00 + 00 00 00 00 + 00 00 00 00 + 3A 6B B7 69 + DD 6C 83 83 + 42 76 CA 68 + 78 75 EF 80 + D4 74 56 5B + 00 00 00 00 + 0A A5 5A D2 + 54 A0 71 0C + 28 00 FF 36 + F0 11 30 03 + 00 00 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-jdi-fhd-nt35596s-video.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-jdi-fhd-nt35596s-video.dtsi new file mode 100644 index 0000000000000..1dc007a40a5b1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/dsi-panel-jdi-fhd-nt35596s-video.dtsi @@ -0,0 +1,718 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *---------------------------------------------------------------------------*/ +&soc { + dsi_jdi_fhd_nt35596s_video: qcom,mdss_dsi_jdi_fhd_nt35596s_video { + qcom,mdss-dsi-panel-name = "jdi fhd video dsi panel"; + qcom,mdss-dsi-panel-id = <0>; + qcom,mdss-dsi-panel-model = "JDI FHD NT35596S VIDEO PANEL"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0x0>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0 15>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <136>; + qcom,cont-splash-enabled; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-panel-on-dimming-delay = <120>; + qcom,esd-err-irq-gpio = <&tlmm 52 0x2001>; + qcom,dispccbb-enabled; + qcom,dispblnotify-enabled; + qcom,dispparam-enabled; + qcom,disp-paneloff-disablecabc-enabled; + qcom,mdss-night-brightness = <7 25 43 61>; + qcom,disp-panel-offon-mode-enabled; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-panel-xy-coordinate = <0x0F 0x18>; + qcom,mdss-dsi-panel-max-luminance = <0x0F 0x20>; + qcom,mdss-dsi-panel-max-luminance-valid = <0x01 0x01>; + qcom,mdss-dsi-panel-bl-info = <408 500 380 620>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <16>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <28>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <24>; + qcom,mdss-dsi-v-front-porch = <7>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 FF 24 + 15 00 00 00 00 00 02 9D 34 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 C4 25 + 15 00 00 00 00 00 02 D1 08 + 15 00 00 00 00 00 02 D2 84 + 15 01 00 00 00 00 02 FF 26 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 03 1C + 15 00 00 00 00 00 02 3B 08 + 15 00 00 00 00 00 02 6B 08 + 15 00 00 00 00 00 02 97 08 + 15 00 00 00 00 00 02 C5 08 + 15 00 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 FF 23 + 15 00 00 00 00 00 02 FB 01 + 15 00 00 00 00 00 02 01 84 + 15 00 00 00 00 00 02 05 2D + 15 00 00 00 00 00 02 06 00 + 15 00 00 00 00 00 02 33 07 + 15 00 00 00 00 00 02 21 EE + 15 00 00 00 00 00 02 22 ED + 15 00 00 00 00 00 02 23 EA + 15 00 00 00 00 00 02 24 E8 + 15 00 00 00 00 00 02 25 E5 + 15 00 00 00 00 00 02 26 E2 + 15 00 00 00 00 00 02 27 DE + 15 00 00 00 00 00 02 28 BB + 15 00 00 00 00 00 02 29 87 + 15 00 00 00 00 00 02 2A 77 + 15 01 00 00 00 00 02 32 0C + 15 00 00 00 00 00 02 13 3F + 15 00 00 00 00 00 02 14 34 + 15 00 00 00 00 00 02 15 2A + 15 00 00 00 00 00 02 16 25 + 15 00 00 00 00 00 02 17 9D + 15 00 00 00 00 00 02 18 9A + 15 00 00 00 00 00 02 19 97 + 15 00 00 00 00 00 02 1A 94 + 15 00 00 00 00 00 02 1B 91 + 15 00 00 00 00 00 02 1C 8E + 15 00 00 00 00 00 02 1D 8B + 15 00 00 00 00 00 02 1E 89 + 15 00 00 00 00 00 02 1F 86 + 15 00 00 00 00 00 02 20 83 + 15 01 00 00 00 00 02 FF 22 + 15 00 00 00 00 00 02 00 0A + 15 00 00 00 00 00 02 01 43 + 15 00 00 00 00 00 02 02 5B + 15 00 00 00 00 00 02 03 6A + 15 00 00 00 00 00 02 04 7A + 15 00 00 00 00 00 02 05 82 + 15 00 00 00 00 00 02 06 85 + 15 00 00 00 00 00 02 07 80 + 15 00 00 00 00 00 02 08 7C + 15 00 00 00 00 00 02 09 7C + 15 00 00 00 00 00 02 0A 74 + 15 00 00 00 00 00 02 0B 71 + 15 00 00 00 00 00 02 0C 6E + 15 00 00 00 00 00 02 0D 68 + 15 00 00 00 00 00 02 0E 65 + 15 01 00 00 00 00 02 0F 5C + 15 00 00 00 00 00 02 10 32 + 15 00 00 00 00 00 02 11 18 + 15 00 00 00 00 00 02 12 00 + 15 00 00 00 00 00 02 13 00 + 15 00 00 00 00 00 02 1A 00 + 15 00 00 00 00 00 02 1B 00 + 15 00 00 00 00 00 02 1C 00 + 15 00 00 00 00 00 02 1D 00 + 15 00 00 00 00 00 02 1E 00 + 15 00 00 00 00 00 02 1F 00 + 15 00 00 00 00 00 02 20 00 + 15 00 00 00 00 00 02 21 00 + 15 00 00 00 00 00 02 22 00 + 15 00 00 00 00 00 02 23 00 + 15 00 00 00 00 00 02 24 00 + 15 01 00 00 00 00 02 25 00 + 15 00 00 00 00 00 02 26 00 + 15 00 00 00 00 00 02 27 00 + 15 00 00 00 00 00 02 28 00 + 15 00 00 00 00 00 02 29 00 + 15 00 00 00 00 00 02 2A 00 + 15 00 00 00 00 00 02 2B 00 + 15 00 00 00 00 00 02 2F 00 + 15 00 00 00 00 00 02 30 00 + 15 00 00 00 00 00 02 31 00 + 15 00 00 00 00 00 02 32 0C + 15 00 00 00 00 00 02 33 0C + 15 00 00 00 00 00 02 34 0C + 15 00 00 00 00 00 02 35 0B + 15 00 00 00 00 00 02 36 09 + 15 00 00 00 00 00 02 37 09 + 15 01 00 00 00 00 02 38 08 + 15 00 00 00 00 00 02 39 05 + 15 00 00 00 00 00 02 3A 03 + 15 00 00 00 00 00 02 3B 00 + 15 00 00 00 00 00 02 3F 00 + 15 00 00 00 00 00 02 40 00 + 15 00 00 00 00 00 02 41 00 + 15 00 00 00 00 00 02 42 00 + 15 00 00 00 00 00 02 43 00 + 15 00 00 00 00 00 02 44 00 + 15 00 00 00 00 00 02 45 00 + 15 00 00 00 00 00 02 46 00 + 15 00 00 00 00 00 02 47 00 + 15 00 00 00 00 00 02 48 00 + 15 00 00 00 00 00 02 49 03 + 15 00 00 00 00 00 02 4A 06 + 15 01 00 00 00 00 02 4B 07 + 15 00 00 00 00 00 02 4C 07 + 15 00 00 00 00 00 02 4D 00 + 15 00 00 00 00 00 02 4E 00 + 15 00 00 00 00 00 02 4F 00 + 15 00 00 00 00 00 02 50 00 + 15 00 00 00 00 00 02 51 00 + 15 00 00 00 00 00 02 52 00 + 15 00 00 00 00 00 02 53 01 + 15 00 00 00 00 00 02 54 01 + 15 00 00 00 00 00 02 55 89 + 15 00 00 00 00 00 02 56 00 + 15 00 00 00 00 00 02 58 00 + 15 00 00 00 00 00 02 68 00 + 15 00 00 00 00 00 02 84 FF + 15 00 00 00 00 00 02 85 FF + 15 01 00 00 00 00 02 86 03 + 15 00 00 00 00 00 02 87 00 + 15 00 00 00 00 00 02 88 00 + 15 00 00 00 00 00 02 A2 20 + 15 00 00 00 00 00 02 A9 01 + 15 00 00 00 00 00 02 AA 12 + 15 00 00 00 00 00 02 AB 13 + 15 00 00 00 00 00 02 AC 0A + 15 00 00 00 00 00 02 AD 74 + 15 00 00 00 00 00 02 AF 33 + 15 00 00 00 00 00 02 B0 03 + 15 00 00 00 00 00 02 B1 14 + 15 00 00 00 00 00 02 B2 42 + 15 00 00 00 00 00 02 B3 40 + 15 00 00 00 00 00 02 B4 A5 + 15 01 00 00 00 00 02 B6 44 + 15 00 00 00 00 00 02 B7 04 + 15 00 00 00 00 00 02 B8 14 + 15 00 00 00 00 00 02 B9 42 + 15 00 00 00 00 00 02 BA 40 + 15 00 00 00 00 00 02 BB A5 + 15 00 00 00 00 00 02 BD 44 + 15 00 00 00 00 00 02 BE 04 + 15 00 00 00 00 00 02 BF 00 + 15 00 00 00 00 00 02 C0 75 + 15 00 00 00 00 00 02 C1 6A + 15 00 00 00 00 00 02 C2 A5 + 15 00 00 00 00 00 02 C4 22 + 15 00 00 00 00 00 02 C5 02 + 15 00 00 00 00 00 02 C6 00 + 15 01 00 00 00 00 02 C7 95 + 15 00 00 00 00 00 02 C8 8A + 15 00 00 00 00 00 02 C9 A5 + 15 00 00 00 00 00 02 CB 22 + 15 00 00 00 00 00 02 CC 02 + 15 00 00 00 00 00 02 CD 00 + 15 00 00 00 00 00 02 CE B5 + 15 00 00 00 00 00 02 CF AA + 15 00 00 00 00 00 02 D0 A5 + 15 00 00 00 00 00 02 D2 22 + 15 00 00 00 00 00 02 D3 02 + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 00 00 02 26 02 + 15 00 00 00 00 00 02 35 00 + 15 00 00 00 00 00 02 51 FF + 15 00 00 00 00 00 02 53 24 + 15 00 00 00 00 00 02 55 00 + 15 01 00 00 00 00 02 B0 00 + 05 01 00 00 50 00 02 11 00 + 05 01 00 00 14 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 00 00 02 28 00 + 05 01 00 00 46 00 02 10 00]; + qcom,mdss-dsi-displayoff-command = [05 01 00 00 20 00 02 28 00]; + qcom,mdss-dsi-displayon-command = [05 01 00 00 14 00 02 29 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-displayoff-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-displayon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <1>; + + qcom,mdss-dsi-dispparam-cabcuion-command = [ + 15 01 00 00 00 00 02 55 03 + ]; + qcom,mdss-dsi-dispparam-cabcuion-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcstillon-command = [ + 15 00 00 00 00 00 02 55 01 + 15 01 00 00 00 00 03 68 01 01 + ]; + qcom,mdss-dsi-dispparam-cabcstillon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcmovieon-command = [ + 15 01 00 00 00 00 02 55 02 + ]; + qcom,mdss-dsi-dispparam-cabcmovieon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcoff-command = [ + 39 01 00 00 01 00 02 55 00 + ]; + qcom,mdss-dsi-dispparam-skince-cabcuion-command = [ + 15 01 00 00 00 00 02 55 83 + ]; + qcom,mdss-dsi-dispparam-skince-cabcuion-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-skince-cabcstillon-command = [ + 15 00 00 00 00 00 02 55 81 + 15 01 00 00 00 00 03 68 01 01 + ]; + qcom,mdss-dsi-dispparam-skince-cabcstillon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-skince-cabcmovieon-command = [ + 15 01 00 00 00 00 02 55 82 + ]; + qcom,mdss-dsi-dispparam-skince-cabcmovieon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-skince-cabcoff-command = [ + 15 01 00 00 00 00 02 55 80 + ]; + qcom,mdss-dsi-dispparam-skince-cabcoff-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-cabcoff-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-dimmingon-command = [ + 39 01 00 00 01 00 02 53 2C + ]; + qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-idleon-command = [ + 39 01 00 00 01 00 02 39 00 + ]; + qcom,mdss-dsi-dispparam-idleoff-command = [ + 39 01 00 00 01 00 02 38 00 + ]; + qcom,mdss-dsi-dispparam-papermode2-command = [ + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 10 00 02 26 01 + 15 01 00 00 00 00 02 FF 20 + 15 00 00 00 00 00 02 75 00 + 15 00 00 00 00 00 02 76 00 + 15 00 00 00 00 00 02 77 00 + 15 00 00 00 00 00 02 78 27 + 15 00 00 00 00 00 02 79 00 + 15 00 00 00 00 00 02 7A 67 + 15 00 00 00 00 00 02 7B 00 + 15 00 00 00 00 00 02 7C 94 + 15 00 00 00 00 00 02 7D 00 + 15 00 00 00 00 00 02 7E B8 + 15 00 00 00 00 00 02 7F 00 + 15 00 00 00 00 00 02 80 D4 + 15 00 00 00 00 00 02 81 00 + 15 00 00 00 00 00 02 82 EA + 15 00 00 00 00 00 02 83 00 + 15 00 00 00 00 00 02 84 FC + 15 00 00 00 00 00 02 85 01 + 15 00 00 00 00 00 02 86 0F + 15 00 00 00 00 00 02 87 01 + 15 00 00 00 00 00 02 88 46 + 15 00 00 00 00 00 02 89 01 + 15 00 00 00 00 00 02 8A 70 + 15 00 00 00 00 00 02 8B 01 + 15 00 00 00 00 00 02 8C AD + 15 00 00 00 00 00 02 8D 01 + 15 00 00 00 00 00 02 8E DA + 15 00 00 00 00 00 02 8F 02 + 15 00 00 00 00 00 02 90 1D + 15 00 00 00 00 00 02 91 02 + 15 00 00 00 00 00 02 92 50 + 15 00 00 00 00 00 02 93 02 + 15 00 00 00 00 00 02 94 52 + 15 00 00 00 00 00 02 95 02 + 15 00 00 00 00 00 02 96 83 + 15 00 00 00 00 00 02 97 02 + 15 00 00 00 00 00 02 98 BA + 15 00 00 00 00 00 02 99 02 + 15 00 00 00 00 00 02 9A DE + 15 00 00 00 00 00 02 9B 03 + 15 00 00 00 00 00 02 9C 12 + 15 00 00 00 00 00 02 9D 03 + 15 00 00 00 00 00 02 9E 2E + 15 00 00 00 00 00 02 9F 03 + 15 00 00 00 00 00 02 A0 54 + 15 00 00 00 00 00 02 A2 03 + 15 00 00 00 00 00 02 A3 61 + 15 00 00 00 00 00 02 A4 03 + 15 00 00 00 00 00 02 A5 6F + 15 00 00 00 00 00 02 A6 03 + 15 00 00 00 00 00 02 A7 7E + 15 00 00 00 00 00 02 A9 03 + 15 00 00 00 00 00 02 AA 90 + 15 00 00 00 00 00 02 AB 03 + 15 00 00 00 00 00 02 AC A7 + 15 00 00 00 00 00 02 AD 03 + 15 00 00 00 00 00 02 AE C2 + 15 00 00 00 00 00 02 AF 03 + 15 00 00 00 00 00 02 B0 D5 + 15 00 00 00 00 00 02 B1 03 + 15 01 00 00 00 00 02 B2 D8 + 15 00 00 00 00 00 02 B3 00 + 15 00 00 00 00 00 02 B4 00 + 15 00 00 00 00 00 02 B5 00 + 15 00 00 00 00 00 02 B6 27 + 15 00 00 00 00 00 02 B7 00 + 15 00 00 00 00 00 02 B8 67 + 15 00 00 00 00 00 02 B9 00 + 15 00 00 00 00 00 02 BA 94 + 15 00 00 00 00 00 02 BB 00 + 15 00 00 00 00 00 02 BC B8 + 15 00 00 00 00 00 02 BD 00 + 15 00 00 00 00 00 02 BE D4 + 15 00 00 00 00 00 02 BF 00 + 15 00 00 00 00 00 02 C0 EA + 15 00 00 00 00 00 02 C1 00 + 15 00 00 00 00 00 02 C2 FC + 15 00 00 00 00 00 02 C3 01 + 15 00 00 00 00 00 02 C4 0F + 15 00 00 00 00 00 02 C5 01 + 15 00 00 00 00 00 02 C6 46 + 15 00 00 00 00 00 02 C7 01 + 15 00 00 00 00 00 02 C8 70 + 15 00 00 00 00 00 02 C9 01 + 15 00 00 00 00 00 02 CA AD + 15 00 00 00 00 00 02 CB 01 + 15 00 00 00 00 00 02 CC DA + 15 00 00 00 00 00 02 CD 02 + 15 00 00 00 00 00 02 CE 1D + 15 00 00 00 00 00 02 CF 02 + 15 00 00 00 00 00 02 D0 50 + 15 00 00 00 00 00 02 D1 02 + 15 00 00 00 00 00 02 D2 52 + 15 00 00 00 00 00 02 D3 02 + 15 00 00 00 00 00 02 D4 83 + 15 00 00 00 00 00 02 D5 02 + 15 00 00 00 00 00 02 D6 BA + 15 00 00 00 00 00 02 D7 02 + 15 00 00 00 00 00 02 D8 DE + 15 00 00 00 00 00 02 D9 03 + 15 00 00 00 00 00 02 DA 12 + 15 00 00 00 00 00 02 DB 03 + 15 00 00 00 00 00 02 DC 2E + 15 00 00 00 00 00 02 DD 03 + 15 00 00 00 00 00 02 DE 54 + 15 00 00 00 00 00 02 DF 03 + 15 00 00 00 00 00 02 E0 61 + 15 00 00 00 00 00 02 E1 03 + 15 00 00 00 00 00 02 E2 6F + 15 00 00 00 00 00 02 E3 03 + 15 00 00 00 00 00 02 E4 7E + 15 00 00 00 00 00 02 E5 03 + 15 00 00 00 00 00 02 E6 90 + 15 00 00 00 00 00 02 E7 03 + 15 00 00 00 00 00 02 E8 A7 + 15 00 00 00 00 00 02 E9 03 + 15 00 00 00 00 00 02 EA C2 + 15 00 00 00 00 00 02 EB 03 + 15 00 00 00 00 00 02 EC D5 + 15 00 00 00 00 00 02 ED 03 + 15 00 00 00 00 00 02 EE D8 + 15 00 00 00 00 00 02 EF 00 + 15 00 00 00 00 00 02 F0 BC + 15 00 00 00 00 00 02 F1 00 + 15 00 00 00 00 00 02 F2 CB + 15 00 00 00 00 00 02 F3 00 + 15 00 00 00 00 00 02 F4 E4 + 15 00 00 00 00 00 02 F5 00 + 15 00 00 00 00 00 02 F6 F9 + 15 00 00 00 00 00 02 F7 01 + 15 00 00 00 00 00 02 F8 0B + 15 00 00 00 00 00 02 F9 01 + 15 00 00 00 00 00 02 FA 1B + 15 01 00 00 00 00 02 FF 21 + 15 00 00 00 00 00 02 00 01 + 15 00 00 00 00 00 02 01 2A + 15 00 00 00 00 00 02 02 01 + 15 00 00 00 00 00 02 03 38 + 15 00 00 00 00 00 02 04 01 + 15 00 00 00 00 00 02 05 44 + 15 00 00 00 00 00 02 06 01 + 15 00 00 00 00 00 02 07 6E + 15 00 00 00 00 00 02 08 01 + 15 00 00 00 00 00 02 09 8F + 15 00 00 00 00 00 02 0A 01 + 15 00 00 00 00 00 02 0B C2 + 15 00 00 00 00 00 02 0C 01 + 15 00 00 00 00 00 02 0D E9 + 15 00 00 00 00 00 02 0E 02 + 15 00 00 00 00 00 02 0F 27 + 15 00 00 00 00 00 02 10 02 + 15 00 00 00 00 00 02 11 56 + 15 00 00 00 00 00 02 12 02 + 15 00 00 00 00 00 02 13 58 + 15 00 00 00 00 00 02 14 02 + 15 00 00 00 00 00 02 15 87 + 15 00 00 00 00 00 02 16 02 + 15 00 00 00 00 00 02 17 BD + 15 00 00 00 00 00 02 18 02 + 15 00 00 00 00 00 02 19 E2 + 15 00 00 00 00 00 02 1A 03 + 15 00 00 00 00 00 02 1B 14 + 15 00 00 00 00 00 02 1C 03 + 15 00 00 00 00 00 02 1D 30 + 15 00 00 00 00 00 02 1E 03 + 15 00 00 00 00 00 02 1F 58 + 15 00 00 00 00 00 02 20 03 + 15 00 00 00 00 00 02 21 64 + 15 00 00 00 00 00 02 22 03 + 15 00 00 00 00 00 02 23 72 + 15 00 00 00 00 00 02 24 03 + 15 00 00 00 00 00 02 25 81 + 15 00 00 00 00 00 02 26 03 + 15 00 00 00 00 00 02 27 95 + 15 00 00 00 00 00 02 28 03 + 15 00 00 00 00 00 02 29 AD + 15 00 00 00 00 00 02 2A 03 + 15 00 00 00 00 00 02 2B C6 + 15 00 00 00 00 00 02 2D 03 + 15 00 00 00 00 00 02 2F D6 + 15 00 00 00 00 00 02 30 03 + 15 01 00 00 00 00 02 31 D8 + 15 00 00 00 00 00 02 32 00 + 15 00 00 00 00 00 02 33 BC + 15 00 00 00 00 00 02 34 00 + 15 00 00 00 00 00 02 35 CB + 15 00 00 00 00 00 02 36 00 + 15 00 00 00 00 00 02 37 E4 + 15 00 00 00 00 00 02 38 00 + 15 00 00 00 00 00 02 39 F9 + 15 00 00 00 00 00 02 3A 01 + 15 00 00 00 00 00 02 3B 0B + 15 00 00 00 00 00 02 3D 01 + 15 00 00 00 00 00 02 3F 1B + 15 00 00 00 00 00 02 40 01 + 15 00 00 00 00 00 02 41 2A + 15 00 00 00 00 00 02 42 01 + 15 00 00 00 00 00 02 43 38 + 15 00 00 00 00 00 02 44 01 + 15 00 00 00 00 00 02 45 44 + 15 00 00 00 00 00 02 46 01 + 15 00 00 00 00 00 02 47 6E + 15 00 00 00 00 00 02 48 01 + 15 00 00 00 00 00 02 49 8F + 15 00 00 00 00 00 02 4A 01 + 15 00 00 00 00 00 02 4B C2 + 15 00 00 00 00 00 02 4C 01 + 15 00 00 00 00 00 02 4D E9 + 15 00 00 00 00 00 02 4E 02 + 15 00 00 00 00 00 02 4F 27 + 15 00 00 00 00 00 02 50 02 + 15 00 00 00 00 00 02 51 56 + 15 00 00 00 00 00 02 52 02 + 15 00 00 00 00 00 02 53 58 + 15 00 00 00 00 00 02 54 02 + 15 00 00 00 00 00 02 55 87 + 15 00 00 00 00 00 02 56 02 + 15 00 00 00 00 00 02 58 BD + 15 00 00 00 00 00 02 59 02 + 15 00 00 00 00 00 02 5A E2 + 15 00 00 00 00 00 02 5B 03 + 15 00 00 00 00 00 02 5C 14 + 15 00 00 00 00 00 02 5D 03 + 15 00 00 00 00 00 02 5E 30 + 15 00 00 00 00 00 02 5F 03 + 15 00 00 00 00 00 02 60 58 + 15 00 00 00 00 00 02 61 03 + 15 00 00 00 00 00 02 62 64 + 15 00 00 00 00 00 02 63 03 + 15 00 00 00 00 00 02 64 72 + 15 00 00 00 00 00 02 65 03 + 15 00 00 00 00 00 02 66 81 + 15 00 00 00 00 00 02 67 03 + 15 00 00 00 00 00 02 68 95 + 15 00 00 00 00 00 02 69 03 + 15 01 00 00 00 00 02 6A AD + 15 00 00 00 00 00 02 6B 03 + 15 00 00 00 00 00 02 6C C6 + 15 00 00 00 00 00 02 6D 03 + 15 00 00 00 00 00 02 6E D6 + 15 00 00 00 00 00 02 6F 03 + 15 00 00 00 00 00 02 70 D8 + 15 00 00 00 00 00 02 71 01 + 15 00 00 00 00 00 02 72 7D + 15 00 00 00 00 00 02 73 01 + 15 00 00 00 00 00 02 74 81 + 15 00 00 00 00 00 02 75 01 + 15 00 00 00 00 00 02 76 88 + 15 00 00 00 00 00 02 77 01 + 15 00 00 00 00 00 02 78 8F + 15 00 00 00 00 00 02 79 01 + 15 00 00 00 00 00 02 7A 96 + 15 00 00 00 00 00 02 7B 01 + 15 00 00 00 00 00 02 7C 9D + 15 00 00 00 00 00 02 7D 01 + 15 00 00 00 00 00 02 7E A3 + 15 00 00 00 00 00 02 7F 01 + 15 00 00 00 00 00 02 80 A8 + 15 00 00 00 00 00 02 81 01 + 15 00 00 00 00 00 02 82 AE + 15 00 00 00 00 00 02 83 01 + 15 00 00 00 00 00 02 84 C3 + 15 00 00 00 00 00 02 85 01 + 15 00 00 00 00 00 02 86 D6 + 15 00 00 00 00 00 02 87 01 + 15 00 00 00 00 00 02 88 F5 + 15 00 00 00 00 00 02 89 02 + 15 00 00 00 00 00 02 8A 12 + 15 00 00 00 00 00 02 8B 02 + 15 00 00 00 00 00 02 8C 42 + 15 00 00 00 00 00 02 8D 02 + 15 00 00 00 00 00 02 8E 6B + 15 00 00 00 00 00 02 8F 02 + 15 00 00 00 00 00 02 90 6C + 15 00 00 00 00 00 02 91 02 + 15 00 00 00 00 00 02 92 98 + 15 00 00 00 00 00 02 93 02 + 15 00 00 00 00 00 02 94 CD + 15 00 00 00 00 00 02 95 02 + 15 00 00 00 00 00 02 96 F2 + 15 00 00 00 00 00 02 97 03 + 15 00 00 00 00 00 02 98 20 + 15 00 00 00 00 00 02 99 03 + 15 00 00 00 00 00 02 9A 3C + 15 00 00 00 00 00 02 9B 03 + 15 00 00 00 00 00 02 9C 61 + 15 00 00 00 00 00 02 9D 03 + 15 00 00 00 00 00 02 9E 6B + 15 00 00 00 00 00 02 9F 03 + 15 00 00 00 00 00 02 A0 77 + 15 00 00 00 00 00 02 A2 03 + 15 00 00 00 00 00 02 A3 85 + 15 00 00 00 00 00 02 A4 03 + 15 00 00 00 00 00 02 A5 95 + 15 00 00 00 00 00 02 A6 03 + 15 00 00 00 00 00 02 A7 9F + 15 00 00 00 00 00 02 A9 03 + 15 00 00 00 00 00 02 AA BF + 15 00 00 00 00 00 02 AB 03 + 15 00 00 00 00 00 02 AC D6 + 15 00 00 00 00 00 02 AD 03 + 15 01 00 00 00 00 02 AE D8 + 15 00 00 00 00 00 02 AF 01 + 15 00 00 00 00 00 02 B0 7D + 15 00 00 00 00 00 02 B1 01 + 15 00 00 00 00 00 02 B2 81 + 15 00 00 00 00 00 02 B3 01 + 15 00 00 00 00 00 02 B4 88 + 15 00 00 00 00 00 02 B5 01 + 15 00 00 00 00 00 02 B6 8F + 15 00 00 00 00 00 02 B7 01 + 15 00 00 00 00 00 02 B8 96 + 15 00 00 00 00 00 02 B9 01 + 15 00 00 00 00 00 02 BA 9D + 15 00 00 00 00 00 02 BB 01 + 15 00 00 00 00 00 02 BC A3 + 15 00 00 00 00 00 02 BD 01 + 15 00 00 00 00 00 02 BE A8 + 15 00 00 00 00 00 02 BF 01 + 15 00 00 00 00 00 02 C0 AE + 15 00 00 00 00 00 02 C1 01 + 15 00 00 00 00 00 02 C2 C3 + 15 00 00 00 00 00 02 C3 01 + 15 00 00 00 00 00 02 C4 D6 + 15 00 00 00 00 00 02 C5 01 + 15 00 00 00 00 00 02 C6 F5 + 15 00 00 00 00 00 02 C7 02 + 15 00 00 00 00 00 02 C8 12 + 15 00 00 00 00 00 02 C9 02 + 15 00 00 00 00 00 02 CA 42 + 15 00 00 00 00 00 02 CB 02 + 15 00 00 00 00 00 02 CC 6B + 15 00 00 00 00 00 02 CD 02 + 15 00 00 00 00 00 02 CE 6C + 15 00 00 00 00 00 02 CF 02 + 15 00 00 00 00 00 02 D0 98 + 15 00 00 00 00 00 02 D1 02 + 15 00 00 00 00 00 02 D2 CD + 15 00 00 00 00 00 02 D3 02 + 15 00 00 00 00 00 02 D4 F2 + 15 00 00 00 00 00 02 D5 03 + 15 00 00 00 00 00 02 D6 20 + 15 00 00 00 00 00 02 D7 03 + 15 00 00 00 00 00 02 D8 3C + 15 00 00 00 00 00 02 D9 03 + 15 00 00 00 00 00 02 DA 61 + 15 00 00 00 00 00 02 DB 03 + 15 00 00 00 00 00 02 DC 6B + 15 00 00 00 00 00 02 DD 03 + 15 00 00 00 00 00 02 DE 77 + 15 00 00 00 00 00 02 DF 03 + 15 00 00 00 00 00 02 E0 85 + 15 00 00 00 00 00 02 E1 03 + 15 00 00 00 00 00 02 E2 95 + 15 00 00 00 00 00 02 E3 03 + 15 00 00 00 00 00 02 E4 9F + 15 00 00 00 00 00 02 E5 03 + 15 00 00 00 00 00 02 E6 BF + 15 00 00 00 00 00 02 E7 03 + 15 00 00 00 00 00 02 E8 D6 + 15 00 00 00 00 00 02 E9 03 + 15 00 00 00 00 00 02 EA D8 + 15 01 00 00 00 00 02 FF 10 + ]; + qcom,mdss-dsi-dispparam-papermode2-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-default-command = [ + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 10 00 02 26 02 + ]; + qcom,mdss-dsi-dispparam-default-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-normal1-command = [ + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 10 00 02 26 01 + ]; + qcom,mdss-dsi-dispparam-normal1-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-normal2-command = [ + 15 01 00 00 00 00 02 FF 10 + 15 01 00 00 10 00 02 26 02 + ]; + qcom,mdss-dsi-dispparam-normal2-command-state = "dsi_hs_mode"; + + qcom,mdss-dsi-read-brightness-command = [ + 06 01 00 01 05 00 02 52 00]; + qcom,mdss-dsi-read-brightness-command-state = "dsi_hs_mode"; + + qcom,mdss-dsi-dispparam-xy-coordinate-command = [ + 06 01 00 01 05 00 02 A1 00]; + qcom,mdss-dsi-dispparam-xy-coordinate-command-state = "dsi_hs_mode"; + + qcom,mdss-dsi-dispparam-max-luminance-command = [ + 06 01 00 01 05 00 02 A1 00]; + qcom,mdss-dsi-dispparam-max-luminance-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-dispparam-max-luminance-valid-command = [ + 06 01 00 01 05 00 02 DB 00]; + qcom,mdss-dsi-dispparam-max-luminance-valid-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-jdi-fhd-r63452-cmd.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-jdi-fhd-r63452-cmd.dtsi new file mode 100644 index 0000000000000..9d417b64f8b04 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/dsi-panel-jdi-fhd-r63452-cmd.dtsi @@ -0,0 +1,112 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *---------------------------------------------------------------------------*/ +&soc { + dsi_jdi_fhd_r63452_cmd: qcom,mdss_dsi_jdi_fhd_r63452_cmd { + qcom,mdss-dsi-panel-name = "jdi fhd cmd incell dsi panel"; + qcom,mdss-dsi-panel-id = <0>; + qcom,mdss-dsi-panel-model = "JDI FHD R63452 CMD PANEL"; + qcom,mdss-dsi-panel-sleepwrmod = <0>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-panel-timings = [e3 50 36 00 a9 a3 3a 50 3d 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x20>; + qcom,mdss-dsi-t-clk-pre = <0x36>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 1>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <64>; + qcom,mdss-pan-physical-height-dimension = <114>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-panel-on-dimming-delay = <120>; + qcom,mdss-night-brightness = <7 25 43 61>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <4>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + 29 00 00 00 00 00 02 b0 00 + 29 00 00 00 00 00 02 d6 01 + 29 00 00 00 00 00 0E EC 64 DC EC 3B 52 00 0B 0B 13 15 68 0B B5 + 29 00 00 00 00 00 02 b0 03 + 39 00 00 00 00 00 02 35 00 + 39 00 00 00 00 00 02 36 00 + 39 00 00 00 00 00 02 3A 77 + 39 00 00 00 00 00 05 2A 00 00 04 37 + 39 00 00 00 00 00 05 2B 00 00 07 7F + 39 00 00 00 00 00 03 44 00 00 + 39 00 00 00 00 00 02 51 FF + 39 00 00 00 00 00 02 53 24 + 39 00 00 00 00 00 02 55 00 + 39 00 00 00 00 00 02 5E 00 + 39 00 00 00 00 00 02 84 00 + 05 01 00 00 14 00 02 29 00 + 05 01 00 00 50 00 02 11 00 + 29 00 00 00 00 00 02 B0 04 + 39 00 00 00 00 00 02 84 00 + 29 00 00 00 00 00 02 C8 11 + 29 01 00 00 00 00 02 B0 03]; + qcom,mdss-dsi-off-command = [ + 29 00 00 00 00 00 02 b0 00 + 29 00 00 00 00 00 02 d6 01 + 29 00 00 00 00 00 0E EC 64 DC EC 3B 52 00 0B 0B 13 15 68 0B 95 + 29 00 00 00 00 00 02 b0 03 + 05 01 00 00 02 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-tianma-fhd-nt36672a-video.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-tianma-fhd-nt36672a-video.dtsi new file mode 100644 index 0000000000000..f766480d700a7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/dsi-panel-tianma-fhd-nt36672a-video.dtsi @@ -0,0 +1,82 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/*--------------------------------------------------------------------------- + * This file is autogenerated file using gcdb parser. Please do not edit it. + * Update input XML file to add a new entry or update variable in this file + * VERSION = "1.0" + *---------------------------------------------------------------------------*/ +&soc { + dsi_tianma_fhd_nt36672a_video: qcom,mdss_dsi_tianma_fhd_nt36672a_video { + qcom,mdss-dsi-panel-name = "tianma fhd video dsi panel"; + qcom,mdss-dsi-panel-id = <0>; + qcom,mdss-dsi-panel-model = "TIANMA FHD NT36672A VIDEO PANEL"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0x0>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <0 15>, <1 20>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <136>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-panel-on-dimming-delay = <120>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2246>; + qcom,mdss-dsi-h-front-porch = <40>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 05 01 00 00 78 00 02 11 00 + 15 00 00 00 00 00 02 FF 10 + 15 00 00 00 00 00 02 35 00 + 05 01 00 00 14 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index b4631e95036cd..af215434d06c7 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -1852,42 +1852,6 @@ memory-region = <&wcnss_fw_mem>; }; - qcom,venus@1de0000 { - compatible = "qcom,pil-tz-generic"; - reg = <0x1de0000 0x4000>; - - vdd-supply = <&gdsc_venus>; - qcom,proxy-reg-names = "vdd"; - - clocks = <&clock_gcc clk_gcc_venus0_vcodec0_clk>, - <&clock_gcc clk_gcc_venus0_ahb_clk>, - <&clock_gcc clk_gcc_venus0_axi_clk>, - <&clock_gcc clk_gcc_crypto_clk>, - <&clock_gcc clk_gcc_crypto_ahb_clk>, - <&clock_gcc clk_gcc_crypto_axi_clk>, - <&clock_gcc clk_crypto_clk_src>; - - clock-names = "core_clk", "iface_clk", "bus_clk", - "scm_core_clk", "scm_iface_clk", - "scm_bus_clk", "scm_core_clk_src"; - - qcom,proxy-clock-names = "core_clk", "iface_clk", - "bus_clk", "scm_core_clk", - "scm_iface_clk", "scm_bus_clk", - "scm_core_clk_src"; - qcom,scm_core_clk_src-freq = <80000000>; - - qcom,msm-bus,name = "pil-venus"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <63 512 0 0>, - <63 512 0 304000>; - qcom,pas-id = <9>; - qcom,proxy-timeout-ms = <100>; - qcom,firmware-name = "venus"; - memory-region = <&venus_mem>; - }; }; #include "pm8953-rpm-regulator.dtsi" diff --git a/arch/arm64/boot/dts/qcom/pm8005.dtsi b/arch/arm64/boot/dts/qcom/pm8005.dtsi index aff92a8100a2a..1f8d20e9dd578 100644 --- a/arch/arm64/boot/dts/qcom/pm8005.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8005.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -25,12 +25,11 @@ reg = <0x100 0x100>; }; - pm8005_tz: qcom,temp-alarm@2400 { + qcom,temp-alarm@2400 { compatible = "qcom,qpnp-temp-alarm"; reg = <0x2400 0x100>; interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_RISING>; label = "pm8005_tz"; - #thermal-sensor-cells = <0>; }; pm8005_gpios: pinctrl@c000 { @@ -80,28 +79,3 @@ }; }; }; - -&thermal_zones { - pm8005_tz { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8005_tz>; - trips { - pm8005-trip0 { - temperature = <105000>; - hysteresis = <0>; - type = "passive"; - }; - pm8005-trip1 { - temperature = <125000>; - hysteresis = <0>; - type = "passive"; - }; - pm8005-trip2 { - temperature = <145000>; - hysteresis = <0>; - type = "passive"; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index 89499f864a55d..df52fe2658e11 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -1,4 +1,5 @@ /* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -44,6 +45,9 @@ qcom,pon-type = <0>; qcom,pull-up = <1>; linux,code = <116>; + qcom,s1-timer = <6720>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; }; qcom,pon_2 { @@ -56,9 +60,9 @@ qcom,pon-type = <3>; qcom,support-reset = <1>; qcom,pull-up = <1>; - qcom,s1-timer = <6720>; + qcom,s1-timer = <1352>; qcom,s2-timer = <2000>; - qcom,s2-type = ; + qcom,s2-type = ; qcom,use-bark; }; }; diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index 2f4b00e0ccd63..52278eb1a13da 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -1,4 +1,5 @@ /* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -643,10 +644,10 @@ pmi8998_torch0: qcom,torch_0 { label = "torch"; qcom,led-name = "led:torch_0"; - qcom,max-current = <500>; + qcom,max-current = <300>; qcom,default-led-trigger = "torch0_trigger"; qcom,id = <0>; - qcom,current-ma = <300>; + qcom,current-ma = <75>; qcom,ires-ua = <12500>; qcom,hdrm-voltage-mv = <325>; qcom,hdrm-vol-hi-lo-win-mv = <100>; @@ -655,10 +656,10 @@ pmi8998_torch1: qcom,torch_1 { label = "torch"; qcom,led-name = "led:torch_1"; - qcom,max-current = <500>; + qcom,max-current = <300>; qcom,default-led-trigger = "torch1_trigger"; qcom,id = <1>; - qcom,current-ma = <300>; + qcom,current-ma = <75>; qcom,ires-ua = <12500>; qcom,hdrm-voltage-mv = <325>; qcom,hdrm-vol-hi-lo-win-mv = <100>; diff --git a/arch/arm64/boot/dts/qcom/polaris-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/polaris-audio-overlay.dtsi new file mode 100644 index 0000000000000..7b0c72a219e40 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-audio-overlay.dtsi @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdm845-audio-overlay.dtsi" +&snd_934x { + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "AMIC2_EXT_0", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC2_EXT_1", "MIC BIAS1", + "MIC BIAS1", "Headset Mic2", + "AMIC3", "MIC BIAS3", + "MIC BIAS3", "ANCRight Headset Mic", + "AMIC1", "MIC BIAS1", + "MIC BIAS1", "ANCLeft Headset Mic", + "AMIC4", "MIC BIAS3", + "MIC BIAS3", "ANCRight Headset Mic", + "AMIC5", "MIC BIAS4", + "MIC BIAS4", "Analog Mic5"; + + qcom,wsa-max-devs = <0>; + qcom,euro-us-hw-auto-switch; + qcom,hw-auto-sw-en-gpio = <&sbu_mic_oe>; + qcom,uart-audio-sw-gpio = <&sbu_uart_en>; + qcom,adc2-switch-gpio = <&adc2_switch_gpio>; + qcom,msm-mbhc-usbc-audio-supported = <1>; + pinctrl-names = "aud_active", "aud_sleep", + "quat-mi2s-active", "quat-mi2s-sleep", + "quat-tdm-active", "quat-tdm-sleep"; + pinctrl-0 = <&wcd_usbc_analog_en2_active>; + pinctrl-1 = <&wcd_usbc_analog_en2_idle>; + pinctrl-2 = <&quat_mi2s_active &quat_mi2s_sd0_active + &quat_mi2s_sd1_active>; + pinctrl-3 = <&quat_mi2s_sleep &quat_mi2s_sd0_sleep + &quat_mi2s_sd1_sleep>; + pinctrl-4 = <&quat_tdm_active &quat_tdm_dout_active>; + pinctrl-5 = <&quat_tdm_sleep &quat_tdm_dout_sleep>; + +}; + +&soc { + sbu_mic_oe: msm_cdc_pinctrl@43 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&sbu_mic_oe_active>; + pinctrl-1 = <&sbu_mic_oe_idle>; + }; + + sbu_uart_en: msm_cdc_pinctrl@51 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&sbu_uart_en_active>; + pinctrl-1 = <&sbu_uart_en_idle>; + }; + + adc2_switch_gpio: msm_cdc_pinctrl@104 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&adc2_switch_gpio_active>; + pinctrl-1 = <&adc2_switch_gpio_idle>; + }; + + vreg_pa_p_5p0: vreg_pa_p_5p0 { + compatible = "regulator-fixed"; + regulator-name = "vreg_pa_p_5p0"; + startup-delay-us=<2000>; + gpio = <&tlmm 31 0>; + enable-active-high; + }; + + vreg_pa_n_5p0: vreg_pa_n_5p0 { + compatible = "regulator-fixed"; + regulator-name = "vreg_pa_n_5p0"; + startup-delay-us=<4000>; + gpio = <&tlmm 32 0>; + enable-active-high; + }; + +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-camera-sensor-mtp.dtsi b/arch/arm64/boot/dts/qcom/polaris-camera-sensor-mtp.dtsi new file mode 100644 index 0000000000000..838c83ce73b87 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-camera-sensor-mtp.dtsi @@ -0,0 +1,413 @@ +/* + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pmi8998_flash0 &pmi8998_flash1>; + torch-source = <&pmi8998_torch0 &pmi8998_torch1>; + switch-source = <&pmi8998_switch0>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pmi8998_flash0 &pmi8998_flash1>; + torch-source = <&pmi8998_torch0 &pmi8998_torch1>; + switch-source = <&pmi8998_switch0>; + status = "ok"; + }; + + actuator_rear_regulator: gpio-regulator@0 { + compatible = "regulator-fixed"; + reg = <0x00 0x00>; + regulator-name = "actuator_rear_regulator"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <100>; + enable-active-high; + gpio = <&tlmm 26 0>; + vin-supply = <&pmi8998_bob>; + }; + + actuator_rear_aux_regulator: gpio-regulator@1 { + compatible = "regulator-fixed"; + reg = <0x01 0x00>; + regulator-name = "actuator_rear_aux_regulator"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <100>; + enable-active-high; + gpio = <&tlmm 27 0>; + vin-supply = <&pmi8998_bob>; + }; + + camera_rear_ldo: gpio-regulator@2 { + compatible = "regulator-fixed"; + reg = <0x02 0x00>; + regulator-name = "camera_rear_ldo"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&pm8998_gpios 11 0>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_rear_dvdd_en_default>; + vin-supply = <&pm8998_s3>; + }; + + camera_ldo: gpio-regulator@3 { + compatible = "regulator-fixed"; + reg = <0x03 0x00>; + regulator-name = "camera_ldo"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <233>; + enable-active-high; + gpio = <&pm8998_gpios 9 0>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_dvdd_en_default>; + vin-supply = <&pm8998_s4>; + }; + + camera_aux_vdig_ldo: gpio-regulator@4 { + compatible = "regulator-fixed"; + reg = <0x04 0x00>; + regulator-name = "camera_aux_ldo"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 77 0>; + vin-supply = <&pm8998_s3>; + }; + + camera_ois_regulator: gpio-regulator@5 { + compatible = "regulator-fixed"; + reg = <0x05 0x00>; + regulator-name = "camera_ois_regulator"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <100>; + enable-active-high; + gpio = <&tlmm 50 0>; + vin-supply = <&pmi8998_bob>; + }; +}; + +&cam_cci { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&actuator_rear_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + }; + + actuator_rear_aux: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&actuator_rear_aux_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + }; + + ois_rear: qcom,ois@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,ois"; + cci-master = <0>; + cam_vaf-supply = <&camera_ois_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,eeprom"; + slave-addr = <0xa0>; + i2c-freq-mode = <1>; + num-blocks = <1>; + page0 = <0 0 0 0 0 0>; + poll0 = <0 0 0 0 0 0>; + mem0 = <8192 0x00 2 0 1 0>; + qcom,cam-power-seq-type = "cam_vio"; + qcom,cam-power-seq-cfg-val = <1>; + qcom,cam-power-seq-delay = <1>; + cam_vio-supply = <&pm8998_lvs1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0>; + rgltr-max-voltage = <0 0>; + rgltr-load-current = <0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK0"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + slave-addr = <0xa0>; + i2c-freq-mode = <1>; + num-blocks = <1>; + page0 = <0 0 0 0 0 0>; + poll0 = <0 0 0 0 0 0>; + mem0 = <8192 0x00 2 0 1 0>; + qcom,cam-power-seq-type = "cam_vio"; + qcom,cam-power-seq-cfg-val = <1>; + qcom,cam-power-seq-delay = <1>; + cam_vio-supply = <&pm8998_lvs1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0>; + rgltr-max-voltage = <0 0>; + rgltr-load-current = <0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 13 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK0"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + slave-addr = <0x6c>; + i2c-freq-mode = <1>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3312000 1050000 0>; + rgltr-max-voltage = <0 3600000 1050000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 9 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA2"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&camera_rear_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3312000 1050000 0>; + rgltr-max-voltage = <0 3600000 1050000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 80 0>, + <&tlmm 87 0>, + <&tlmm 102 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-custom1 = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VANA0", + "CAM_CUSTOM0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux>; + actuator-src = <&actuator_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vdig-supply = <&camera_aux_vdig_ldo>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1000000 0 3312000 0>; + rgltr-max-voltage = <1000000 0 3600000 0>; + rgltr-load-current = <105000 0 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 28 0>, + <&tlmm 79 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET1", + "CAM_VANA1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3312000 1050000 0>; + rgltr-max-voltage = <0 3600000 1050000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 9 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-mp-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/polaris-mp-pinctrl.dtsi new file mode 100644 index 0000000000000..427effbf4a245 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-mp-pinctrl.dtsi @@ -0,0 +1,14 @@ + +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "polaris-p3-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/qcom/polaris-mp-v2.1.dts b/arch/arm64/boot/dts/qcom/polaris-mp-v2.1.dts new file mode 100644 index 0000000000000..5f64cafa953de --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-mp-v2.1.dts @@ -0,0 +1,27 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm845-v2.1.dtsi" +#include "sdm845-sde-display.dtsi" +#include "polaris-mp-pinctrl.dtsi" +#include "polaris-mp.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris MP v2.1"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,board-id = <44 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-mp-v2.dts b/arch/arm64/boot/dts/qcom/polaris-mp-v2.dts new file mode 100644 index 0000000000000..94a75149f2adf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-mp-v2.dts @@ -0,0 +1,27 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm845-v2.dtsi" +#include "sdm845-sde-display.dtsi" +#include "polaris-mp-pinctrl.dtsi" +#include "polaris-mp.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris MP V2"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,board-id = <44 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-mp.dts b/arch/arm64/boot/dts/qcom/polaris-mp.dts new file mode 100644 index 0000000000000..1101ff64484b4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-mp.dts @@ -0,0 +1,27 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm845.dtsi" +#include "sdm845-sde-display.dtsi" +#include "polaris-mp-pinctrl.dtsi" +#include "polaris-mp.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris MP"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,board-id = <44 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-mp.dtsi b/arch/arm64/boot/dts/qcom/polaris-mp.dtsi new file mode 100644 index 0000000000000..bd1cbd744a2c6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-mp.dtsi @@ -0,0 +1,14 @@ + +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "polaris-p3.dtsi" diff --git a/arch/arm64/boot/dts/qcom/polaris-p0-overlay.dts b/arch/arm64/boot/dts/qcom/polaris-p0-overlay.dts new file mode 100644 index 0000000000000..3394e59eb5c52 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p0-overlay.dts @@ -0,0 +1,33 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "sdm845-sde-display.dtsi" +#include "polaris-p0-pinctrl.dtsi" +#include "polaris-p0.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P0"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,msm-id = <321 0x10000>; + qcom,board-id = <40 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p0-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/polaris-p0-pinctrl.dtsi new file mode 100644 index 0000000000000..b2e4a07f4a9f8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p0-pinctrl.dtsi @@ -0,0 +1,632 @@ + +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&tlmm { + idt { + idt_int_active: idt_int_active { + /* active state */ + mux { + /* GPIO 78 idt Read Interrupt */ + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + + idt_int_suspend: idt_int_suspend { + /* sleep state */ + mux { + /* GPIO 78 idt Read Interrupt */ + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + input-enable; + }; + }; + + idt_enable_active: idt_enable_active { + /* active state */ + mux { + /* GPIO 36 idt enable pin */ + pins = "gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio36"; + drive-strength = <2>; + bias-disable; + bias-pull-down; + output-low; + }; + }; + + idt_enable_suspend: idt_enable_suspend { + /* sleep state */ + mux { + /* GPIO 36 idt enable pin */ + pins = "gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + ts_mux { + ts_active: ts_active { + mux { + pins = "gpio99", "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio99", "gpio125"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; + bias-disable; + }; + }; + + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + sbu_mic_oe_ctrl { + sbu_mic_oe_idle: hw-auto-sw-en_idle { + mux { + pins = "gpio43"; + function = "gpio"; + }; + config { + pins = "gpio43"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + sbu_mic_oe_active: hw-auto-sw-en_active { + mux { + pins = "gpio43"; + function = "gpio"; + }; + config { + pins = "gpio43"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + sbu_uart_en_ctrl { + sbu_uart_en_idle: uart_audio_en_idle { + mux { + pins = "gpio51"; + function = "gpio"; + }; + config { + pins = "gpio51"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + sbu_uart_en_active: uart_audio_en_active { + mux { + pins = "gpio51"; + function = "gpio"; + }; + config { + pins = "gpio51"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + adc2_switch_gpio_ctrl { + adc2_switch_gpio_idle: adc2_switch_idle { + mux { + pins = "gpio104"; + function = "gpio"; + }; + config { + pins = "gpio104"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + adc2_switch_gpio_active: adc2_switch_active { + mux { + pins = "gpio104"; + function = "gpio"; + }; + config { + pins = "gpio104"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + cam_sensor_ir_active: cam_sensor_ir_active { + /* RESET AVDD_LDO*/ + mux { + pins = "gpio25", "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio25", "gpio91"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_ir_suspend: cam_sensor_ir_suspend { + /* RESET */ + mux { + pins = "gpio25", "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio25", "gpio91"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_iris_active: cam_sensor_iris_active { + /* RESET AVDD_LDO*/ + mux { + pins = "gpio9", "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio9", "gpio8"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_iris_suspend: cam_sensor_iris_suspend { + /* RESET */ + mux { + pins = "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio9"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + output-low; + }; + }; + + fp_mux { + fp_active: fp_active { + mux { + pins = "gpio121"; + function = "gpio"; + }; + config { + pins = "gpio121"; + drive-strength = <8>; + bias-disable; + }; + }; + + fp_suspend: fp_suspend { + mux { + pins = "gpio121"; + function = "gpio"; + }; + config { + pins = "gpio121"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + /* GPIO_37 : FP_RESET_N */ + msm_gpio_37: msm_gpio_37 { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + /* GPIO_37 : FP_RESET_N, state device active*/ + msm_gpio_37_output_high: msm_gpio_37_output_high { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + /* GPIO_121 : FP_INT_N */ + msm_gpio_121: msm_gpio_121 { + mux { + pins = "gpio121"; + function = "gpio"; + }; + + config { + pins = "gpio121"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + spk_id_no_pull: spk_id_no_pull { + mux { + pins = "gpio44"; + function = "gpio"; + }; + config { + pins = "gpio44"; + drive-strength = <8>; + bias-disable; + input-enable; + }; + }; + spk_id_pull_up: spk_id_pull_up { + mux { + pins = "gpio44"; + function = "gpio"; + }; + config { + pins = "gpio44"; + drive-strength = <8>; + bias-pull-up; + input-enable; + }; + }; + spk_id_pull_down: spk_id_pull_down { + mux { + pins = "gpio44"; + function = "gpio"; + }; + config { + pins = "gpio44"; + drive-strength = <8>; + bias-pull-down; + input-enable; + }; + }; + + +}; + +&nfc_enable_active { + /* active state */ + mux { + /* 12: NFC ENABLE 116:ESE Enable */ + pins = "gpio12", "gpio88", "gpio116"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio88", "gpio116"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; +}; + +&cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + output-low; + }; +}; + +&cam_sensor_mclk2_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk2_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <4>; /* 2 MA */ + }; +}; + +&cam_sensor_rear_active { + /* RESET, AVDD LDO */ + mux { + pins = "gpio80","gpio87","gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio80","gpio87","gpio102"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_rear_suspend { + /* RESET, AVDD LDO */ + mux { + pins = "gpio80","gpio87","gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio80","gpio87","gpio102"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; + +&cam_sensor_rear2_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28","gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio28","gpio79"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_rear2_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28","gpio79"; + function = "gpio"; + }; + config { + pins = "gpio28","gpio79"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; +}; + +&cam_sensor_front_active { + /* RESET AVDD_LDO*/ + mux { + pins = "gpio9", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio9", "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&cam_sensor_front_suspend { + /* RESET */ + mux { + pins = "gpio9", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio9", "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; +}; + +&camera_dvdd_en_default { + pins = "gpio9"; + function = "normal"; + power-source = <0>; + output-low; +}; + +&camera_rear_dvdd_en_default { + pins = "gpio11"; + function = "normal"; + power-source = <0>; + output-low; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p0-v2-overlay.dts b/arch/arm64/boot/dts/qcom/polaris-p0-v2-overlay.dts new file mode 100644 index 0000000000000..2d54f95e0df02 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p0-v2-overlay.dts @@ -0,0 +1,33 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "sdm845-sde-display.dtsi" +#include "polaris-p0.dtsi" +#include "polaris-p0-pinctrl.dtsi" +#include "sdm845-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P0 v2"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,msm-id = <321 0x20000>; + qcom,board-id = <40 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p0-v2.dts b/arch/arm64/boot/dts/qcom/polaris-p0-v2.dts new file mode 100644 index 0000000000000..eb04bc5ee2e2a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p0-v2.dts @@ -0,0 +1,27 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm845-v2.dtsi" +#include "sdm845-sde-display.dtsi" +#include "polaris-p0-pinctrl.dtsi" +#include "polaris-p0.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P0 v2"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,board-id = <40 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p0.dts b/arch/arm64/boot/dts/qcom/polaris-p0.dts new file mode 100644 index 0000000000000..624e64f9ae213 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p0.dts @@ -0,0 +1,27 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm845.dtsi" +#include "sdm845-sde-display.dtsi" +#include "polaris-p0-pinctrl.dtsi" +#include "polaris-p0.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P0"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,board-id = <40 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p0.dtsi b/arch/arm64/boot/dts/qcom/polaris-p0.dtsi new file mode 100644 index 0000000000000..d9873d06ed410 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p0.dtsi @@ -0,0 +1,851 @@ + +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "sdm845-pmic-overlay.dtsi" +#include "sdm845-pinctrl-overlay.dtsi" +#include "polaris-camera-sensor-mtp.dtsi" +#include "smb1355.dtsi" +#include "xiaomi-sde-display.dtsi" + +&removed_region { + reg = <0 0x85fc0000 0 0x3a40000>; +}; + +&qcom_seecom { + reg = <0x86d00000 0x02d00000>; +}; + +&reserved_memory { + ramdump_fb_mem: ramdump_fb_region@af000000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0xaf000000 0 0x1000000>; + }; +}; + +&vendor { + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-io-supply = <&pm8998_s3>; + qca,bt-vdd-xtal-supply = <&pm8998_s5>; + qca,bt-vdd-core-supply = <&pm8998_l7>; + qca,bt-vdd-pa-supply = <&pm8998_l17>; + qca,bt-vdd-ldo-supply = <&pm8998_l25>; + + qca,bt-vdd-io-voltage-level = <1352000 1352000>; + qca,bt-vdd-xtal-voltage-level = <2040000 2040000>; + qca,bt-vdd-core-voltage-level = <1800000 1800000>; + qca,bt-vdd-pa-voltage-level = <1304000 1304000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; + + qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + hall_key { + label = "hall_key"; + gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; + linux,input-type = <5>; + linux,code = <0>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + disp_vci_vreg: disp_vci_vreg { + compatible = "regulator-fixed"; + regulator-name = "disp_vci_vreg"; + start-delay-us = <4000>; + enable-active-high; + regulator-boot-on; + gpio = <&tlmm 35 0>; + }; + + disp_vddio_vreg: disp_vddio_vreg { + compatible = "regulator-fixed"; + regulator-name = "disp_vddio_vreg"; + startup-delay-us = <4000>; + enable-active-high; + regulator-boot-on; + gpio = <&tlmm 90 0>; + }; + + fp_vdd_vreg: fp_vdd_vreg { + compatible = "regulator-fixed"; + regulator-name = "fp_vdd_vreg"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 39 0>; + regulator-always-on; + }; + + fingerprint_fpc { + status = "ok"; + compatible = "fpc,fpc1020"; + interrupt-parent = <&tlmm>; + interrupts = <121 0x0>; + fpc,gpio_irq = <&tlmm 121 0x0>; + /* fpc,enable-on-boot; */ + /* fpc,enable-wakeup; */ + + pinctrl-names = "fpc1020_reset_reset", + "fpc1020_reset_active"; + + pinctrl-0 = <&msm_gpio_37>; + pinctrl-1 = <&msm_gpio_37_output_high>; + }; + + fingerprint_goodix { + compatible = "goodix,fingerprint"; + gooidx,gpio-reset = <&tlmm 37 0x0>; + goodix,gpio-irq = <&tlmm 121 0x0>; + fp-gpio-pwr = <&tlmm 39 0>; + status = "ok"; + }; + + tp_vddio_vreg: tp_vddio_vreg { + compatible = "regulator-fixed"; + regulator-name = "tp_vddio_vreg"; + startup-delay-us = <4000>; + enable-active-high; + regulator-boot-on; + gpio = <&tlmm 23 0>; + }; + + thermal-message { + thermal,batt-array-size = "13"; + thermal,batt-level-screen-on = "0 2 4 6 8 9 10 11 12 13 14 14 16"; + thermal,batt-level-screen-off = "0 1 1 1 3 4 5 5 5 7 9 14 16"; + }; + +}; + +&labibb { + status = "ok"; + qcom,qpnp-labibb-mode = "lcd"; +}; + +&dsi_jdi_fhd_nt35596s_video { + qcom,panel-supply-entries = <&dsi_nt35596s_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_jdi_fhd_nt35596s_video_display { + qcom,dsi-display-active; +}; + +&pmi8998_wled { + status = "okay"; + qcom,fs-curr-ua = <20000>; + qcom,led-strings-list = [00 01 02 03]; + qcom,ovp-mv = <19600>; + qcom,en-cabc; + qcom,switch-freq-khz = <600>; +}; + +&red_led { + linux,name = "white"; + qcom,start-idx = <1>; + qcom,idx-len = <18>; + qcom,duty-pcts = [00 01 02 03 04 05 06 07 08 + 08 07 06 05 04 03 02 01 00]; + qcom,lut-flags = <3>; + qcom,pause-lo = <0>; + qcom,pause-hi = <0>; + qcom,ramp-step-ms = <142>; + qcom,use-blink; + status = "okay"; +}; + +&green_led { + status = "disabled"; +}; + +&blue_led { + status = "disabled"; +}; + +&sde_dp { + status = "disabled"; +}; + +&disp_vci_vreg { + status = "disabled"; +}; + +&pmi8998_haptics { + qcom,vmax-mv = <2552>; + qcom,lra-auto-mode; + qcom,wave-play-rate-us = <4878>; + qcom,wave-shape = "sine"; + qcom,lra-high-z = "opt1"; + qcom,lra-auto-res-mode = "qwd"; + qcom,lra-res-cal-period = <4>; + qcom,effect-max = <3>; + qcom,effect-arry = [3e 3e be a0 00 00 00 00 + 3e 3e 3e be be 00 00 00 + 3e 3e 3e 3e be be a0 90]; + status = "okay"; +}; + +&mdss_mdp { + #cooling-cells = <2>; + connectors = <&sde_rscc &sde_wb>; +}; + +&pm8998_l28{ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <3300000>; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3"; + + vdda-phy-supply = <&pm8998_l1>; /* 0.88v */ + vdda-pll-supply = <&pm8998_l26>; /* 1.2v */ + vdda-phy-max-microamp = <62900>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8998_l20>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm8998_s4>; + vcc-max-microamp = <600000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm8998_l2>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8998_l21>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8998_l13>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep", "ds_400KHz", + "ds_50MHz", "ds_100MHz", "ds_200MHz"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>; + pinctrl-2 = <&sdc2_clk_ds_400KHz + &sdc2_cmd_ds_400KHz &sdc2_data_ds_400KHz>; + pinctrl-3 = <&sdc2_clk_ds_50MHz + &sdc2_cmd_ds_50MHz &sdc2_data_ds_50MHz>; + pinctrl-4 = <&sdc2_clk_ds_100MHz + &sdc2_cmd_ds_100MHz &sdc2_data_ds_100MHz>; + pinctrl-5 = <&sdc2_clk_ds_200MHz + &sdc2_cmd_ds_200MHz &sdc2_data_ds_200MHz>; + + cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + +&pmi8998_switch2 { + pinctrl-names = "led_enable", "led_disable"; + pinctrl-0 = <&flash_led3_iris_en>; + pinctrl-1 = <&flash_led3_iris_dis>; +}; + +&vendor{ + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "batterydata-d5-atl-3400mAh.dtsi" + #include "batterydata-d5-cos-3400mAh.dtsi" + #include "batterydata-itech-3020mAh.dtsi" + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + vbus-gpio = <&pmi8998_gpios 8 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_det_default>; + }; +}; +&pmi8998_charger { + qcom,usb-icl-ua = <2800000>; + qcom,fcc-max-ua = <3300000>; + qcom,dc-icl-ua = <950000>; + qcom,fcc-low-temp-delta = <2970000>; + qcom,fcc-hot-temp-delta = <1650000>; + qcom,fcc-cool-temp-delta = <2310000>; + qcom,auto-recharge-soc; + qcom,sw-jeita-enable; + qcom,thermal-mitigation + = <1800000 1600000 1400000 1200000 1000000 1000000 1000000>; + qcom,thermal-mitigation-dc + = <800000 550000 450000 325000>; + qcom,thermal-mitigation-dcp + = <1800000 1800000 1800000 1800000 1800000 1800000 1800000 + 1800000 1800000 1800000 1800000 1800000 1600000 1400000 + 1200000 1000000>; + qcom,thermal-mitigation-qc3 + = <2800000 2725000 2575000 2425000 2275000 2125000 2000000 + 1800000 1650000 1500000 1360000 1200000 1060000 900000 + 752500 525000>; + qcom,thermal-mitigation-qc2 + = <1625000 1625000 1625000 1625000 1625000 1525000 1425000 + 1325000 1225000 1125000 10255000 925000 825000 725000 + 625000 525000>; + + io-channels = <&pmi8998_rradc 8>, + <&pmi8998_rradc 10>, + <&pmi8998_rradc 3>, + <&pmi8998_rradc 4>, + <&pmi8998_rradc 5>; + io-channel-names = "charger_temp", + "charger_temp_max", + "usbin_i", + "usbin_v", + "dcin_i"; +}; + +&pmi8998_fg { + qcom,fg-force-load-profile; + qcom,fg-sys-term-current = <(-300)>; + qcom,fg-chg-term-current = <200>; + qcom,fg-auto-recharge-soc; + qcom,fg-recharge-soc-thr = <99>; + qcom,fg-cutoff-voltage = <3400>; + qcom,fg-cutoff-current = <200>; + qcom,fg-empty-voltage = <3100>; + qcom,fg-jeita-hyst-temp = <2>; + qcom,fg-jeita-thresholds = <0 15 45 60>; + qcom,fg-esr-clamp-mohms = <60>; + qcom,fg-batt-temp-delta = <6>; + qcom,battery-data = <&mtp_batterydata>; +}; + +&smb1355_charger_0 { + status = "ok"; +}; + +&smb1355_charger_1 { + status = "ok"; +}; + +&qupv3_se9_2uart { + status = "ok"; +}; + +&qupv3_se8_spi { + status = "ok"; +}; + +&qupv3_se3_i2c { + status = "ok"; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 63 0x00>; + qcom,nq-ven = <&tlmm 12 0x00>; + qcom,nq-firm = <&tlmm 88 0x00>; + qcom,nq-clkreq = <&pm8998_gpios 21 0x00>; + qcom,nq-esepwr = <&tlmm 116 0x00>; + interrupt-parent = <&tlmm>; + qcom,clk-src = "BBCLK3"; + interrupts = <63 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active + &nfc_enable_active + &nfc_clk_default>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + clocks = <&clock_rpmh RPMH_LN_BB_CLK3>; + clock-names = "ref_clk"; + }; +}; + +&qupv3_se5_i2c { + status = "ok"; + /*smart PA*/ + tas2559@4c{ + compatible = "ti,tas2559"; + reg = <0x4c>; + ti,tas2559-reset-gpio = <&tlmm 8 0>; + ti,tas2560-reset-gpio = <&tlmm 25 0>; + ti,tas2559-irq-gpio = <&tlmm 24 0>; + ti,tas2560-irq-gpio = <&tlmm 30 0>; + ti,tas2559-addr = <0x4c>; + ti,tas2560-addr = <0x4d>; + ti,tas2559-channel = <0>; /* 0, left; 1, right */ + ti,tas2560-channel = <1>; /* 0, left; 1, right */ + ti,ycrc-enable = <1>; /* 0, disable; non-zero, enable */ + ti,echo-ref = <0>; /* 0, left channel; 1, right channel; 2, both */ + ti,bit-rate = <16>; /* 16, 20, 24, 32 */ + status = "ok"; + }; + +}; + +&qupv3_se10_i2c { + status = "ok"; + idtp9220: idtp9220@61 { + compatible = "idt,p9220"; + reg = <0x61>; + idt,irq = <&tlmm 78 0x00>; + idt,enable = <&tlmm 36 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <78 0>; + interrupt-names = "idt_irq"; + pinctrl-names = "idt_active", "idt_suspend"; + pinctrl-0 = <&idt_int_active &idt_enable_active>; + pinctrl-1 = <&idt_int_suspend &idt_enable_suspend>; + }; +}; + +&qupv3_se14_i2c { + status = "ok"; + synaptics_dsi_i2c@20 { + compatible = "synaptics,dsx-i2c-force"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <125 0x2008>; + vdd-supply = <&tp_vddio_vreg>; + lab-supply = <&lab_regulator>; + ibb-supply = <&ibb_regulator>; + disp-supply = <&pm8998_l14>; + avdd-supply = <&pm8998_l28>; + synaptics,pwr-reg-name = "vdd"; + synaptics,lab-reg-name = "lab"; + synaptics,ibb-reg-name = "ibb"; + synaptics,disp-reg-name = "disp"; + synaptics,bus-reg-name = "avdd"; + synaptics,disp-power-hold; + synaptics,ub-i2c-addr = <0x2c>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + synaptics,drm-dsi-reset = <&tlmm 6 0>; + synaptics,reset-gpio = <&tlmm 99 0x00>; + synaptics,irq-gpio = <&tlmm 125 0x2008>; + synaptics,reset-gpio-name = "dsx_reset"; + synaptics,irq-gpio-name = "dsx_irq"; + synaptics,irq-on-state = <0>; + synaptics,irq-flags = <0x2008>; /* IRQF_ONESHOT | IRQF_TRIGGER_LOW */ + synaptics,power-delay-ms = <5>; + synaptics,reset-delay-ms = <200>; + synaptics,reset-active-ms = <5>; + synaptics,power-on-state = <1>; + synaptics,reset-on-state = <0>; + synaptics,drm-reset-state = <1>; + synaptics,panel-is-incell; + synaptics,dump-click-count; + synaptics,short-jdi-25 = "000: 0xff\n001: 0xff\n002: 0xff\n003: 0xf7\n004: 0x03\n005: 0x00\n006: 0x00"; + synaptics,short-jdi-26 = "000: 0x03\n001: 0x00\n002: 0x00\n003: 0x00\n004: 0x03\n005: 0x00\n006: 0x00"; + /*clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, + <&clock_gcc clk_gcc_blsp1_qup5_i2c_apps_clk>; + */ + synaptics,guest-serialization-as-lockdown; + synaptics,tp-id-byte = /bits/ 8 <0>; + synaptics,config-array-size = <1>; + synaptics,cfg_1 { + synaptics,chip-id = <0>; + synaptics,chip-id-name = "S3330"; + synaptics,tp-id = /bits/ 8 <0x31>; + synaptics,fw-name = "synaptics_jdi_3330_d5x.fw"; + synaptics,clicknum-file-name = "syna+jdi"; + }; + }; +}; + +&qupv3_se6_4uart { + status = "ok"; +}; + +&usb1 { + status = "okay"; + extcon = <&extcon_usb1>; +}; + +&qusb_phy1 { + status = "okay"; +}; + +&ext_5v_boost { + status = "ok"; +}; + +&usb_qmp_phy { + status = "okay"; +}; + +&wil6210 { + status = "ok"; +}; + +&flash_led { + pmi8998_flashlight: qcom,flashlight { + label = "flash"; + qcom,led-name = "flashlight"; + qcom,max-current = <750>; + qcom,default-led-trigger = "flashlight_trigger"; + qcom,id = <3>; + qcom,current-ma = <500>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; +}; + +&pm8998_l14 { + regulator-boot-on; +}; + +&qcom_qbt1000 { + status = "disabled"; +}; + +&pm8998_vadc { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@85 { + label = "vcoin"; + reg = <0x85>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@4d { + label = "cam_therm0"; + reg = <0x4d>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@4e { + label = "cam_therm1"; + reg = <0x4e>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@4f { + label = "pa_therm0"; + reg = <0x4f>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@50 { + label = "pa_therm1"; + reg = <0x50>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8998_adc_tm { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,btm-channel-number = <0x60>; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x68>; + qcom,thermal-node; + }; + + chan@4d { + label = "cam_therm0"; + reg = <0x4d>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x88>; + qcom,thermal-node; + }; + + chan@4e { + label = "cam_therm1"; + reg = <0x4e>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x70>; + qcom,thermal-node; + }; + + chan@4f { + label = "pa_therm0"; + reg = <0x4f>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x78>; + qcom,thermal-node; + }; + + chan@50 { + label = "pa_therm1"; + reg = <0x50>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x90>; + qcom,thermal-node; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x80>; + qcom,thermal-node; + }; +}; + +&thermal_zones { + xo_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8998_adc_tm 0x4c>; + thermal-governor = "user_space"; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam_therm0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8998_adc_tm 0x4d>; + thermal-governor = "user_space"; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam_therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8998_adc_tm 0x4e>; + thermal-governor = "user_space"; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa_therm0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8998_adc_tm 0x4f>; + thermal-governor = "user_space"; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa_therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8998_adc_tm 0x50>; + thermal-governor = "user_space"; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8998_adc_tm 0x51>; + thermal-governor = "user_space"; + + trips { + active-config0 { + temperature = <65000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&usb0 { + dwc3@a600000 { + maximum-speed = "high-speed"; + }; +}; + +&usb1 { + dwc3@a800000 { + maximum-speed = "high-speed"; + }; +}; + +&pcie0 { + status = "disabled"; +}; + +&pcie1 { + status = "disabled"; +}; + +&qusb_phy0 { + qcom,qusb-phy-init-seq = + /* */ + <0x23 0x210 /* PWR_CTRL1 */ + 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */ + 0x7c 0x18c /* PLL_CLOCK_INVERTERS */ + 0x80 0x2c /* PLL_CMODE */ + 0x0a 0x184 /* PLL_LOCK_DELAY */ + 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ + 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ + 0x12 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x21 0x214 /* PWR_CTRL2 */ + 0x08 0x220 /* IMP_CTRL1 */ + 0x58 0x224 /* IMP_CTRL2 */ + 0x07 0x240 /* TUNE1 */ + 0x29 0x244 /* TUNE2 */ + 0xca 0x248 /* TUNE3 */ + 0x04 0x24c /* TUNE4 */ + 0x03 0x250 /* TUNE5 */ + 0x00 0x23c /* CHG_CTRL2 */ + 0x22 0x210>; /* PWR_CTRL1 */ +}; + +&pmi8998_pdphy { + vbus-supply = <&smb2_vbus>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p1-camera-sensor-mtp.dtsi b/arch/arm64/boot/dts/qcom/polaris-p1-camera-sensor-mtp.dtsi new file mode 100644 index 0000000000000..df04c09c9dc54 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p1-camera-sensor-mtp.dtsi @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + camera_vio_ldo: gpio-regulator@6 { + compatible = "regulator-fixed"; + reg = <0x06 0x00>; + regulator-name = "camera_vio_ldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 21 0>; + vin-supply = <&pm8998_s4>; + }; +}; + +&eeprom_rear { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,eeprom"; + slave-addr = <0xa0>; + i2c-freq-mode = <1>; + num-blocks = <1>; + page0 = <0 0 0 0 0 0>; + poll0 = <0 0 0 0 0 0>; + mem0 = <8192 0x00 2 0 1 0>; + qcom,cam-power-seq-type = "cam_vio"; + qcom,cam-power-seq-cfg-val = <1>; + qcom,cam-power-seq-delay = <1>; + cam_vio-supply = <&camera_vio_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <180000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK0"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; +}; + +&eeprom_rear_aux { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + slave-addr = <0xa0>; + i2c-freq-mode = <1>; + num-blocks = <1>; + page0 = <0 0 0 0 0 0>; + poll0 = <0 0 0 0 0 0>; + mem0 = <8192 0x00 2 0 1 0>; + qcom,cam-power-seq-type = "cam_vio"; + qcom,cam-power-seq-cfg-val = <1>; + qcom,cam-power-seq-delay = <1>; + cam_vio-supply = <&camera_vio_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <180000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 13 0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <1>; + gpio-req-tbl-label = "CAMIF_MCLK0"; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; +}; + +&eeprom_front { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + slave-addr = <0x6c>; + i2c-freq-mode = <1>; + cam_vio-supply = <&camera_vio_ldo>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3312000 1050000 0>; + rgltr-max-voltage = <1800000 3600000 1050000 0>; + rgltr-load-current = <180000 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 9 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA2"; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; +}; + +&cam_cci { + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear>; + eeprom-src = <&eeprom_rear>; + ois-src = <&ois_rear>; + cam_vio-supply = <&camera_vio_ldo>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&camera_rear_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3312000 1050000 0>; + rgltr-max-voltage = <1800000 3600000 1050000 0>; + rgltr-load-current = <180000 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 80 0>, + <&tlmm 87 0>, + <&tlmm 102 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-custom1 = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VANA0", + "CAM_CUSTOM0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux>; + actuator-src = <&actuator_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vdig-supply = <&camera_aux_vdig_ldo>; + cam_vio-supply = <&camera_vio_ldo>; + cam_vana-supply = <&pmi8998_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1000000 1800000 3312000 0>; + rgltr-max-voltage = <1000000 1800000 3600000 0>; + rgltr-load-current = <105000 180000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 28 0>, + <&tlmm 79 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET1", + "CAM_VANA1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&camera_vio_ldo>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3312000 1050000 0>; + rgltr-max-voltage = <1800000 3600000 1050000 0>; + rgltr-load-current = <180000 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 9 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p1-overlay.dts b/arch/arm64/boot/dts/qcom/polaris-p1-overlay.dts new file mode 100644 index 0000000000000..413fb43a7547c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p1-overlay.dts @@ -0,0 +1,33 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "sdm845-sde-display.dtsi" +#include "polaris-p1-pinctrl.dtsi" +#include "polaris-p1.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P1"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,msm-id = <321 0x10000>; + qcom,board-id = <41 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p1-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/polaris-p1-pinctrl.dtsi new file mode 100644 index 0000000000000..0411904c1e580 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p1-pinctrl.dtsi @@ -0,0 +1,14 @@ + +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "polaris-p0-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/qcom/polaris-p1-v2-overlay.dts b/arch/arm64/boot/dts/qcom/polaris-p1-v2-overlay.dts new file mode 100644 index 0000000000000..7b90d5e41f24f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p1-v2-overlay.dts @@ -0,0 +1,33 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "sdm845-sde-display.dtsi" +#include "polaris-p1-pinctrl.dtsi" +#include "polaris-p1.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P1 v2"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,msm-id = <321 0x20000>; + qcom,board-id = <41 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p1-v2.1-overlay.dts b/arch/arm64/boot/dts/qcom/polaris-p1-v2.1-overlay.dts new file mode 100644 index 0000000000000..b36ed6815d978 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p1-v2.1-overlay.dts @@ -0,0 +1,33 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "sdm845-sde-display.dtsi" +#include "polaris-p1-pinctrl.dtsi" +#include "polaris-p1.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P1 v2.1"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,msm-id = <321 0x20001>; + qcom,board-id = <41 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p1-v2.1.dts b/arch/arm64/boot/dts/qcom/polaris-p1-v2.1.dts new file mode 100644 index 0000000000000..65d2a4b4028fc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p1-v2.1.dts @@ -0,0 +1,27 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm845-v2.1.dtsi" +#include "sdm845-sde-display.dtsi" +#include "polaris-p1-pinctrl.dtsi" +#include "polaris-p1.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P1 v2.1"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,board-id = <41 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p1-v2.dts b/arch/arm64/boot/dts/qcom/polaris-p1-v2.dts new file mode 100644 index 0000000000000..7bff1e6ed3bb6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p1-v2.dts @@ -0,0 +1,27 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm845-v2.dtsi" +#include "sdm845-sde-display.dtsi" +#include "polaris-p1-pinctrl.dtsi" +#include "polaris-p1.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P1 v2"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,board-id = <41 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p1.dts b/arch/arm64/boot/dts/qcom/polaris-p1.dts new file mode 100644 index 0000000000000..844120ef6b70e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p1.dts @@ -0,0 +1,27 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm845.dtsi" +#include "sdm845-sde-display.dtsi" +#include "polaris-p1-pinctrl.dtsi" +#include "polaris-p1.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P1"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,board-id = <41 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p1.dtsi b/arch/arm64/boot/dts/qcom/polaris-p1.dtsi new file mode 100644 index 0000000000000..9e5a7e3b883a4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p1.dtsi @@ -0,0 +1,15 @@ + +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "polaris-p0.dtsi" +#include "polaris-p1-camera-sensor-mtp.dtsi" diff --git a/arch/arm64/boot/dts/qcom/polaris-p2-overlay.dts b/arch/arm64/boot/dts/qcom/polaris-p2-overlay.dts new file mode 100644 index 0000000000000..3aaeb188f1141 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p2-overlay.dts @@ -0,0 +1,33 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "sdm845-sde-display.dtsi" +#include "polaris-p2-pinctrl.dtsi" +#include "polaris-p2.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P2"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,msm-id = <321 0x10000>; + qcom,board-id = <42 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p2-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/polaris-p2-pinctrl.dtsi new file mode 100644 index 0000000000000..3ed1bbfa5d459 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p2-pinctrl.dtsi @@ -0,0 +1,41 @@ + +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "polaris-p1-pinctrl.dtsi" + +&tlmm { + atest_usb13_active: atest_usb13_active { + mux { + pins = "gpio8"; + function = "gpio"; + }; + config { + pins = "gpio8"; + drive-strength = <12>; + bias-pull-up; + }; + }; + + atest_usb13_suspend: atest_usb13_suspend { + mux { + pins = "gpio8"; + function = "gpio"; + }; + config { + pins = "gpio8"; + bias-pull-down; + drive-strength = <2>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/polaris-p2-v2-overlay.dts b/arch/arm64/boot/dts/qcom/polaris-p2-v2-overlay.dts new file mode 100644 index 0000000000000..6ee979f88804b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p2-v2-overlay.dts @@ -0,0 +1,33 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "sdm845-sde-display.dtsi" +#include "polaris-p2-pinctrl.dtsi" +#include "polaris-p2.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P2 V2"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,msm-id = <321 0x20000>; + qcom,board-id = <42 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p2-v2.1-overlay.dts b/arch/arm64/boot/dts/qcom/polaris-p2-v2.1-overlay.dts new file mode 100644 index 0000000000000..089d8db5dd749 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p2-v2.1-overlay.dts @@ -0,0 +1,33 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "sdm845-sde-display.dtsi" +#include "polaris-p2-pinctrl.dtsi" +#include "polaris-p2.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P2 V2.1"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,msm-id = <321 0x20001>; + qcom,board-id = <42 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p2-v2.1.dts b/arch/arm64/boot/dts/qcom/polaris-p2-v2.1.dts new file mode 100644 index 0000000000000..e57695cae2bc4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p2-v2.1.dts @@ -0,0 +1,27 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm845-v2.1.dtsi" +#include "sdm845-sde-display.dtsi" +#include "polaris-p2-pinctrl.dtsi" +#include "polaris-p2.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P2 v2.1"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,board-id = <42 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p2-v2.dts b/arch/arm64/boot/dts/qcom/polaris-p2-v2.dts new file mode 100644 index 0000000000000..938b73e14881e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p2-v2.dts @@ -0,0 +1,27 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm845-v2.dtsi" +#include "sdm845-sde-display.dtsi" +#include "polaris-p2-pinctrl.dtsi" +#include "polaris-p2.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P2 v2"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,board-id = <42 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p2.dts b/arch/arm64/boot/dts/qcom/polaris-p2.dts new file mode 100644 index 0000000000000..4451fc820c1fb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p2.dts @@ -0,0 +1,27 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm845.dtsi" +#include "sdm845-sde-display.dtsi" +#include "polaris-p2-pinctrl.dtsi" +#include "polaris-p2.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P2"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,board-id = <42 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p2.dtsi b/arch/arm64/boot/dts/qcom/polaris-p2.dtsi new file mode 100644 index 0000000000000..1f0bd8e534c01 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p2.dtsi @@ -0,0 +1,27 @@ + +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "polaris-p1.dtsi" +&qupv3_se5_i2c { + /*smart PA*/ + tas2559@4c{ + ti,tas2559-reset-gpio = <&tlmm 14 0>; + }; + +}; + +&qusb_phy0 { + pinctrl-names = "atest_usb13_suspend","atest_usb13_active"; + pinctrl-0 = <&atest_usb13_suspend>; + pinctrl-1 = <&atest_usb13_active>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p3-overlay.dts b/arch/arm64/boot/dts/qcom/polaris-p3-overlay.dts new file mode 100644 index 0000000000000..b6f4934f2febc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p3-overlay.dts @@ -0,0 +1,33 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "sdm845-sde-display.dtsi" +#include "polaris-p3-pinctrl.dtsi" +#include "polaris-p3.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P3"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,msm-id = <321 0x10000>; + qcom,board-id = <43 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p3-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/polaris-p3-pinctrl.dtsi new file mode 100644 index 0000000000000..d83c4098f755f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p3-pinctrl.dtsi @@ -0,0 +1,46 @@ + +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "polaris-p2-pinctrl.dtsi" + +&idt_enable_active { + /* active state */ + mux { + /* GPIO 62 idt enable pin */ + pins = "gpio62"; + function = "gpio"; + }; + + config { + pins = "gpio62"; + drive-strength = <2>; + bias-disable; + bias-pull-down; + output-low; + }; +}; + +&idt_enable_suspend { + /* sleep state */ + mux { + /* GPIO 62 idt enable pin */ + pins = "gpio62"; + function = "gpio"; + }; + + config { + pins = "gpio62"; + drive-strength = <2>; + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p3-v2-overlay.dts b/arch/arm64/boot/dts/qcom/polaris-p3-v2-overlay.dts new file mode 100644 index 0000000000000..673c96a3f1653 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p3-v2-overlay.dts @@ -0,0 +1,33 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "sdm845-sde-display.dtsi" +#include "polaris-p3-pinctrl.dtsi" +#include "polaris-p3.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P3 V2"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,msm-id = <321 0x20000>; + qcom,board-id = <43 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p3-v2.1-overlay.dts b/arch/arm64/boot/dts/qcom/polaris-p3-v2.1-overlay.dts new file mode 100644 index 0000000000000..9f7b7654969c1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p3-v2.1-overlay.dts @@ -0,0 +1,33 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "sdm845-sde-display.dtsi" +#include "polaris-p3-pinctrl.dtsi" +#include "polaris-p3.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P3 V2.1"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,msm-id = <321 0x20001>; + qcom,board-id = <43 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p3-v2.1.dts b/arch/arm64/boot/dts/qcom/polaris-p3-v2.1.dts new file mode 100644 index 0000000000000..e4654e9b52801 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p3-v2.1.dts @@ -0,0 +1,27 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm845-v2.1.dtsi" +#include "sdm845-sde-display.dtsi" +#include "polaris-p3-pinctrl.dtsi" +#include "polaris-p3.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P3 v2.1"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,board-id = <43 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p3-v2.dts b/arch/arm64/boot/dts/qcom/polaris-p3-v2.dts new file mode 100644 index 0000000000000..6b4b025317473 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p3-v2.dts @@ -0,0 +1,27 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm845-v2.dtsi" +#include "sdm845-sde-display.dtsi" +#include "polaris-p3-pinctrl.dtsi" +#include "polaris-p3.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P3 v2"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,board-id = <43 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p3.dts b/arch/arm64/boot/dts/qcom/polaris-p3.dts new file mode 100644 index 0000000000000..ef6b6a0bea0a2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p3.dts @@ -0,0 +1,27 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm845.dtsi" +#include "sdm845-sde-display.dtsi" +#include "polaris-p3-pinctrl.dtsi" +#include "polaris-p3.dtsi" +#include "polaris-audio-overlay.dtsi" + +/ { + model = "Xiaomi Technologies, Inc. Polaris P3"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + qcom,board-id = <43 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/polaris-p3.dtsi b/arch/arm64/boot/dts/qcom/polaris-p3.dtsi new file mode 100644 index 0000000000000..969d4178f2116 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/polaris-p3.dtsi @@ -0,0 +1,50 @@ + +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "polaris-p2.dtsi" + +&qusb_phy0 { + qcom,qusb-phy-init-seq = + /* */ + <0x23 0x210 /* PWR_CTRL1 */ + 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */ + 0x7c 0x18c /* PLL_CLOCK_INVERTERS */ + 0x80 0x2c /* PLL_CMODE */ + 0x0a 0x184 /* PLL_LOCK_DELAY */ + 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ + 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ + 0x17 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x21 0x214 /* PWR_CTRL2 */ + 0x08 0x220 /* IMP_CTRL1 */ + 0x58 0x224 /* IMP_CTRL2 */ + 0x07 0x240 /* TUNE1 */ + 0x29 0x244 /* TUNE2 */ + 0xca 0x248 /* TUNE3 */ + 0x04 0x24c /* TUNE4 */ + 0x03 0x250 /* TUNE5 */ + 0x00 0x23c /* CHG_CTRL2 */ + 0x22 0x210>; /* PWR_CTRL1 */ + mi,efuse-pll-bias; +}; + +&idtp9220 { + idt,enable = <&tlmm 62 0x00>; +}; + +&smb1355_charger_0 { + qcom,enable-ctm; +}; + +&smb1355_charger_1 { + qcom,enable-ctm; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm670-camera.dtsi b/arch/arm64/boot/dts/qcom/sdm670-camera.dtsi index 715affdb0ec35..1f40e20a19f2a 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670-camera.dtsi @@ -229,7 +229,6 @@ qcom,cam_smmu { compatible = "qcom,msm-cam-smmu"; status = "ok"; - non-fatal-fault-disabled; msm_cam_smmu_lrme { compatible = "qcom,msm-cam-smmu-cb"; diff --git a/arch/arm64/boot/dts/qcom/sdm670-pm.dtsi b/arch/arm64/boot/dts/qcom/sdm670-pm.dtsi index 5bf8df72c99df..b330cf5afe1d1 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-pm.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670-pm.dtsi @@ -185,8 +185,4 @@ reg = <0xc300000 0x1000>, <0xc3f0004 0x4>; reg-names = "phys_addr_base", "offset_addr"; }; - - qcom,rpmh-master-stats { - compatible = "qcom,rpmh-master-stats"; - }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-670-usb-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-670-usb-common.dtsi index f6fa948a35308..1b6ef9b65c08c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-670-usb-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-670-usb-common.dtsi @@ -125,6 +125,7 @@ qcom,efuse-bit-pos = <25>; qcom,efuse-num-bits = <3>; + qcom,tune-efuse-correction = <0x00000000>; /* you can adjust this from 0xffff,fff9(-7) to 0x0000,0007(+7), 80-P6348-5D*/ vdd-supply = <&pm8998_l1>; vdda18-supply = <&pm8998_l12>; vdda33-supply = <&pm8998_l24>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/sdm845-audio-overlay.dtsi index 9d485b5dbba08..3e1a222a6dc8b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-audio-overlay.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -47,8 +48,6 @@ qcom,msm-mbhc-hphl-swh = <1>; qcom,msm-mbhc-gnd-swh = <1>; - qcom,msm-mbhc-hs-mic-max-threshold-mv = <1700>; - qcom,msm-mbhc-hs-mic-min-threshold-mv = <50>; qcom,hph-en0-gpio = <&tavil_hph_en0>; qcom,hph-en1-gpio = <&tavil_hph_en1>; qcom,tavil-mclk-clk-freq = <9600000>; @@ -160,10 +159,10 @@ "cdc-vdd-rx-h", "cdc-vddpx-1"; - qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias1-mv = <2700>; qcom,cdc-micbias2-mv = <1800>; - qcom,cdc-micbias3-mv = <1800>; - qcom,cdc-micbias4-mv = <1800>; + qcom,cdc-micbias3-mv = <2700>; + qcom,cdc-micbias4-mv = <2700>; qcom,cdc-mclk-clk-rate = <9600000>; qcom,cdc-slim-ifd = "tavil-slim-ifd"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-qrd.dtsi b/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-qrd.dtsi new file mode 100644 index 0000000000000..cf24e02a29084 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-camera-sensor-qrd.dtsi @@ -0,0 +1,378 @@ +/* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pmi8998_flash0 &pmi8998_flash1>; + torch-source = <&pmi8998_torch0 &pmi8998_torch1>; + switch-source = <&pmi8998_switch0>; + status = "ok"; + }; + + led_flash_front: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pmi8998_flash2>; + torch-source = <&pmi8998_torch2>; + switch-source = <&pmi8998_switch1>; + status = "ok"; + }; + + actuator_regulator: gpio-regulator@0 { + compatible = "regulator-fixed"; + reg = <0x00 0x00>; + regulator-name = "actuator_regulator"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <100>; + enable-active-high; + gpio = <&tlmm 27 0>; + vin-supply = <&pmi8998_bob>; + }; + + camera_rear_ldo: gpio-regulator@1 { + compatible = "regulator-fixed"; + reg = <0x01 0x00>; + regulator-name = "camera_rear_ldo"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&pm8998_gpios 12 0>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_rear_dvdd_en_default>; + vin-supply = <&pm8998_s3>; + }; + + camera_ldo: gpio-regulator@2 { + compatible = "regulator-fixed"; + reg = <0x02 0x00>; + regulator-name = "camera_ldo"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <233>; + enable-active-high; + gpio = <&pm8998_gpios 9 0>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_dvdd_en_default>; + vin-supply = <&pm8998_s3>; + }; +}; + +&cam_cci { + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&actuator_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + }; + + actuator_front: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&actuator_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + }; + + ois_rear: qcom,ois@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,ois"; + cci-master = <0>; + cam_vaf-supply = <&actuator_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <0>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&camera_rear_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3312000 1050000 0>; + rgltr-max-voltage = <0 3600000 1050000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 80 0>, + <&tlmm 79 0>, + <&tlmm 27 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vaf = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VANA0", + "CAM_VAF"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&camera_ldo>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1050000 0 3312000 0>; + rgltr-max-voltage = <1050000 0 3600000 0>; + rgltr-load-current = <105000 0 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 9 0>, + <&tlmm 8 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_VANA1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2812000 1050000 0>; + rgltr-max-voltage = <0 3600000 1050000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 9 0>, + <&tlmm 8 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA1"; + sensor-position = <1>; + sensor-mode = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear>; + ois-src = <&ois_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&camera_rear_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3312000 1050000 0>; + rgltr-max-voltage = <0 3600000 1050000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 80 0>, + <&tlmm 79 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VANA"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_rear_aux>; + cam_vdig-supply = <&camera_ldo>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vdig", "cam_vio", "cam_vana", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1050000 0 3312000 0>; + rgltr-max-voltage = <1050000 0 3600000 0>; + rgltr-load-current = <105000 0 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 9 0>, + <&tlmm 8 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_VANA1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + actuator-src = <&actuator_front>; + led-flash-src = <&led_flash_front>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2812000 1050000 0>; + rgltr-max-voltage = <0 3600000 1050000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 9 0>, + <&tlmm 8 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA1"; + sensor-mode = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi b/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi index 35a777405be2c..4968a969791d1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -173,7 +173,7 @@ hw-thd-dat = <22>; hw-thd-sta = <162>; hw-tbuf = <227>; - hw-scl-stretch-en = <0>; + hw-scl-stretch-en = <1>; hw-trdhld = <6>; hw-tsp = <3>; cci-clk-src = <37500000>; @@ -188,7 +188,7 @@ hw-thd-dat = <22>; hw-thd-sta = <35>; hw-tbuf = <62>; - hw-scl-stretch-en = <0>; + hw-scl-stretch-en = <1>; hw-trdhld = <6>; hw-tsp = <3>; cci-clk-src = <37500000>; @@ -218,7 +218,7 @@ hw-thd-dat = <16>; hw-thd-sta = <15>; hw-tbuf = <24>; - hw-scl-stretch-en = <0>; + hw-scl-stretch-en = <1>; hw-trdhld = <3>; hw-tsp = <3>; cci-clk-src = <37500000>; @@ -309,13 +309,23 @@ }; iova-mem-region-io { - /* IO region is approximately 3.3 GB */ + /* IO region is approximately 3 GB */ iova-region-name = "io"; - iova-region-start = <0xd900000>; - iova-region-len = <0xd2700000>; + iova-region-start = <0xd911000>; + iova-region-len = <0xd26ef000>; iova-region-id = <0x3>; status = "ok"; }; + + iova-mem-qdss-region { + /* qdss region is approximately 64K */ + iova-region-name = "qdss"; + iova-region-start = <0xd900000>; + iova-region-len = <0x10000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; }; }; @@ -863,7 +873,7 @@ <0 0 200000000 0 0 0 0 600000000>; clock-cntl-level = "svs", "turbo"; fw_name = "CAMERA_ICP.elf"; - ubwc-cfg = <0x7F 0x1FF>; + ubwc-cfg = <0x7B 0x1EF>; status = "ok"; }; @@ -885,12 +895,11 @@ <&clock_camcc CAM_CC_IPE_0_CLK_SRC>; clock-rates = - <0 0 0 0 240000000>, <0 0 0 0 404000000>, <0 0 0 0 480000000>, <0 0 0 0 538000000>, <0 0 0 0 600000000>; - clock-cntl-level = "lowsvs", "svs", + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; status = "ok"; }; @@ -912,12 +921,12 @@ <&clock_camcc CAM_CC_IPE_1_CLK>, <&clock_camcc CAM_CC_IPE_1_CLK_SRC>; - clock-rates = <0 0 0 0 240000000>, + clock-rates = <0 0 0 0 404000000>, <0 0 0 0 480000000>, <0 0 0 0 538000000>, <0 0 0 0 600000000>; - clock-cntl-level = "lowsvs", "svs", + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; status = "ok"; }; @@ -939,12 +948,12 @@ <&clock_camcc CAM_CC_BPS_CLK>, <&clock_camcc CAM_CC_BPS_CLK_SRC>; - clock-rates = <0 0 0 0 200000000>, + clock-rates = <0 0 0 0 404000000>, <0 0 0 0 480000000>, <0 0 0 0 600000000>, <0 0 0 0 600000000>; - clock-cntl-level = "lowsvs", "svs", + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; status = "ok"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cdp.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cdp.dtsi index 5a88dc2405920..b8ba81954ae83 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cdp.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cdp.dtsi @@ -1,4 +1,5 @@ /* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -488,8 +489,8 @@ trips { active-config0 { - temperature = <125000>; - hysteresis = <10000>; + temperature = <65000>; + hysteresis = <1000>; type = "passive"; }; }; @@ -503,8 +504,8 @@ trips { active-config0 { - temperature = <125000>; - hysteresis = <10000>; + temperature = <65000>; + hysteresis = <1000>; type = "passive"; }; }; @@ -518,8 +519,8 @@ trips { active-config0 { - temperature = <125000>; - hysteresis = <10000>; + temperature = <65000>; + hysteresis = <1000>; type = "passive"; }; }; @@ -533,8 +534,8 @@ trips { active-config0 { - temperature = <125000>; - hysteresis = <10000>; + temperature = <65000>; + hysteresis = <1000>; type = "passive"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi index 90e1f242eb5d0..7a1f2ca361cbb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -166,15 +166,6 @@ }; port@1 { - reg = <6>; - funnel_swao_in_sensor_etm0: endpoint { - slave-mode; - remote-endpoint= - <&sensor_etm0_out_funnel_swao>; - }; - }; - - port@2 { reg = <7>; funnel_swao_in_tpda_swao: endpoint { slave-mode; @@ -556,9 +547,7 @@ clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; - status = "disabled"; - ports { #address-cells = <1>; #size-cells = <0>; @@ -2058,20 +2047,6 @@ }; }; - sensor_etm0 { - compatible = "qcom,coresight-remote-etm"; - - coresight-name = "coresight-sensor-etm0"; - qcom,inst-id = <8>; - - port { - sensor_etm0_out_funnel_swao: endpoint { - remote-endpoint = - <&funnel_swao_in_sensor_etm0>; - }; - }; - }; - modem_etm0 { compatible = "qcom,coresight-remote-etm"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-interposer-pm660.dtsi b/arch/arm64/boot/dts/qcom/sdm845-interposer-pm660.dtsi index 1c7269ab2b33f..383a6c21f0b88 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-interposer-pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-interposer-pm660.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -248,11 +248,6 @@ /delete-property/ vdd_gfx-supply; }; -&clock_cpucc { - /delete-property/ vdd_l3_mx_ao-supply; - /delete-property/ vdd_pwrcl_mx_ao-supply; -}; - &pil_modem { /delete-property/ vdd_cx-supply; /delete-property/ vdd_mx-supply; @@ -328,13 +323,6 @@ /delete-property/ pinctrl-0; }; - gpio-regulator@4 { - /delete-property/ gpio; - /delete-property/ vin-supply; - /delete-property/ pinctrl-names; - /delete-property/ pinctrl-0; - }; - /delete-node/ qcom,spmi-debug@6b22000; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi b/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi index fc4b674f3b63c..071442715d3a0 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi @@ -1,4 +1,5 @@ /* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -490,8 +491,8 @@ trips { active-config0 { - temperature = <125000>; - hysteresis = <10000>; + temperature = <65000>; + hysteresis = <1000>; type = "passive"; }; }; @@ -505,8 +506,8 @@ trips { active-config0 { - temperature = <125000>; - hysteresis = <10000>; + temperature = <65000>; + hysteresis = <1000>; type = "passive"; }; }; @@ -520,8 +521,8 @@ trips { active-config0 { - temperature = <125000>; - hysteresis = <10000>; + temperature = <65000>; + hysteresis = <1000>; type = "passive"; }; }; @@ -535,8 +536,8 @@ trips { active-config0 { - temperature = <125000>; - hysteresis = <10000>; + temperature = <65000>; + hysteresis = <1000>; type = "passive"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-pcie.dtsi b/arch/arm64/boot/dts/qcom/sdm845-pcie.dtsi index daf56877cd09b..088cc48ede5bf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-pcie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-pcie.dtsi @@ -196,7 +196,6 @@ qcom,vreg-cx-voltage-level = ; - qcom,l1-supported; qcom,l1ss-supported; qcom,aux-clk-sync; @@ -527,7 +526,6 @@ qcom,vreg-cx-voltage-level = ; - qcom,l1-supported; qcom,l1ss-supported; qcom,aux-clk-sync; diff --git a/arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi index d482cbf72f32f..cacee89dbcf33 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi @@ -1,4 +1,5 @@ /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -3116,12 +3117,12 @@ cam_res_mgr_active: cam_res_mgr_active { /* AVDD_LDO*/ mux { - pins = "gpio8"; + pins = ""; function = "gpio"; }; config { - pins = "gpio8"; + pins = ""; bias-disable; /* No PULL */ drive-strength = <2>; /* 2 MA */ }; @@ -3130,12 +3131,12 @@ cam_res_mgr_suspend: cam_res_mgr_suspend { /* AVDD_LDO */ mux { - pins = "gpio8"; + pins = ""; function = "gpio"; }; config { - pins = "gpio8"; + pins = ""; bias-disable; /* No PULL */ drive-strength = <2>; /* 2 MA */ output-low; diff --git a/arch/arm64/boot/dts/qcom/sdm845-pm.dtsi b/arch/arm64/boot/dts/qcom/sdm845-pm.dtsi index ee10cfcd60417..99aceecae4245 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-pm.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-pm.dtsi @@ -95,6 +95,7 @@ #size-cells = <0>; qcom,psci-mode-shift = <0>; qcom,psci-mode-mask = <0xf>; + qcom,use-prediction; qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>; qcom,pm-cpu-level@0 { /* C1 */ @@ -139,8 +140,4 @@ reg = <0xC300000 0x1000>, <0xC3F0004 0x4>; reg-names = "phys_addr_base", "offset_addr"; }; - - qcom,rpmh-master-stats { - compatible = "qcom,rpmh-master-stats"; - }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-regulator.dtsi b/arch/arm64/boot/dts/qcom/sdm845-regulator.dtsi index f215eca36aded..0c3a0f1f5d22b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-regulator.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-regulator.dtsi @@ -1,4 +1,5 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -432,7 +433,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1880000>; qcom,init-voltage = <1800000>; - qcom,init-mode = ; + qcom,init-mode = ; }; }; @@ -540,7 +541,7 @@ regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2960000>; qcom,init-voltage = <2704000>; - qcom,init-mode = ; + qcom,init-mode = ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-v2-camera.dtsi b/arch/arm64/boot/dts/qcom/sdm845-v2-camera.dtsi index 05d77d329851b..4aa6927a37436 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-v2-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-v2-camera.dtsi @@ -248,13 +248,23 @@ }; iova-mem-region-io { - /* IO region is approximately 3.3 GB */ + /* IO region is approximately 3 GB */ iova-region-name = "io"; - iova-region-start = <0xd900000>; - iova-region-len = <0xd2700000>; + iova-region-start = <0xd911000>; + iova-region-len = <0xd26ef000>; iova-region-id = <0x3>; status = "ok"; }; + + iova-mem-qdss-region { + /* qdss region is approximately 64K */ + iova-region-name = "qdss"; + iova-region-start = <0xd900000>; + iova-region-len = <0x10000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 1b83977579433..0d953d48c60d5 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1,4 +1,5 @@ /* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -495,25 +496,28 @@ firmware: firmware { android { compatible = "android,firmware"; - vbmeta { - compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo"; - }; - fstab { compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,verify"; + status = "ok"; + }; vendor { compatible = "android,vendor"; dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; type = "ext4"; mnt_flags = "ro,barrier=1,discard"; - fsmgr_flags = "wait,slotselect,avb"; + fsmgr_flags = "wait,verify"; }; }; }; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; @@ -566,49 +570,49 @@ pil_adsp_mem: adsp_region@0x8c500000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x8c500000 0 0x1a00000>; + reg = <0 0x8c500000 0 0x1e00000>; }; - wlan_fw_region: wlan_fw_region@0x8df00000 { + wlan_fw_region: wlan_fw_region@0x8e300000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x8df00000 0 0x100000>; + reg = <0 0x8e300000 0 0x100000>; }; - pil_modem_mem: modem_region@0x8e000000 { + pil_modem_mem: modem_region@0x8e400000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x8e000000 0 0x7800000>; + reg = <0 0x8e400000 0 0x7800000>; }; - pil_video_mem: video_region@0x95800000 { + pil_video_mem: video_region@0x95c00000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x95800000 0 0x500000>; + reg = <0 0x95c00000 0 0x500000>; }; - pil_cdsp_mem: cdsp_region@0x95d00000 { + pil_cdsp_mem: cdsp_region@0x96100000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x95d00000 0 0x800000>; + reg = <0 0x96100000 0 0x800000>; }; - pil_mba_mem: mba_region@0x96500000 { + pil_mba_mem: mba_region@0x96900000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x96500000 0 0x200000>; + reg = <0 0x96900000 0 0x200000>; }; - pil_slpi_mem: slpi_region@0x96700000 { + pil_slpi_mem: slpi_region@0x96b00000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x96700000 0 0x1400000>; + reg = <0 0x96b00000 0 0x1400000>; }; - pil_spss_mem: pil_spss_region@0x97b00000 { + pil_spss_mem: pil_spss_region@0x97f00000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x97b00000 0 0x100000>; + reg = <0 0x97f00000 0 0x100000>; }; adsp_mem: adsp_region { @@ -1748,8 +1752,8 @@ reg = <0x17980000 0x1000>; reg-names = "wdt-base"; interrupts = <0 0 0>, <0 1 0>; - qcom,bark-time = <11000>; - qcom,pet-time = <9360>; + qcom,bark-time = <20000>; + qcom,pet-time = <15000>; qcom,ipi-ping; qcom,wakeup-enable; }; @@ -1903,6 +1907,11 @@ reg = <0x10 8>; }; + dload_type@18 { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x18 4>; + }; + restart_reason@65c { compatible = "qcom,msm-imem-restart_reason"; reg = <0x65c 4>; @@ -2480,7 +2489,7 @@ qcom,pipe-attr-ee; }; - qcom,qbt1000 { + qcom_qbt1000: qcom,qbt1000 { compatible = "qcom,qbt1000"; clock-names = "core", "iface"; clock-frequency = <25000000>; @@ -3914,6 +3923,7 @@ qcom,smmu-s1-bypass; iommus = <&apps_smmu 0x20 0x0f>; }; + }; &clock_cpucc { diff --git a/arch/arm64/boot/dts/qcom/smb1355.dtsi b/arch/arm64/boot/dts/qcom/smb1355.dtsi index 3412b25decaa1..aad4ddecc9fc4 100644 --- a/arch/arm64/boot/dts/qcom/smb1355.dtsi +++ b/arch/arm64/boot/dts/qcom/smb1355.dtsi @@ -15,7 +15,7 @@ &qupv3_se10_i2c { smb1355_0: qcom,smb1355@8 { compatible = "qcom,i2c-pmic"; - reg = <0x8>; + reg = <0x08>; #address-cells = <1>; #size-cells = <0>; interrupt-parent = <&spmi_bus>; diff --git a/arch/arm64/boot/dts/qcom/xiaomi-sde-display.dtsi b/arch/arm64/boot/dts/qcom/xiaomi-sde-display.dtsi new file mode 100644 index 0000000000000..b81bbfa9531c0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/xiaomi-sde-display.dtsi @@ -0,0 +1,234 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "dsi-panel-jdi-fhd-r63452-cmd.dtsi" +#include "dsi-panel-jdi-fhd-nt35596s-video.dtsi" +#include "dsi-panel-tianma-fhd-nt36672a-video.dtsi" + +&soc { + dsi_amoled_panel_pwr_supply: dsi_amoled_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vci"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <10>; + }; + }; + + dsi_nt35596s_panel_pwr_supply: dsi_nt35596s_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <1>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + }; + + qcom,panel-supply-entry@1 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@2 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-pre-off-sleep = <5>; + }; + }; + + dsi_nt36672a_panel_pwr_supply: dsi_nt36672a_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <1>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <5>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <5>; + }; + + qcom,panel-supply-entry@1 { + reg = <2>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <5500000>; + qcom,supply-max-voltage = <5500000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <15>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <15>; + }; + + qcom,panel-supply-entry@2 { + reg = <3>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <5500000>; + qcom,supply-max-voltage = <5500000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <15>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <15>; + }; + }; + + dsi_jdi_fhd_r63452_cmd_display: qcom,dsi-display@16 { + compatible = "qcom,dsi-display"; + label = "dsi_jdi_fhd_r63452_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, + <&mdss_dsi0_pll PCLK_MUX_0_CLK>; + clock-names = "src_byte_clk", "src_pixel_clk"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + /* qcom,panel-mode-gpio = <&tlmm 52 0>; */ + + qcom,dsi-panel = <&dsi_jdi_fhd_r63452_cmd>; + vddts-supply = <&pm8998_l28>; + vddio-supply = <&pm8998_l14>; + lab-supply = <&lab_regulator>; + ibb-supply = <&ibb_regulator>; + }; + + dsi_jdi_fhd_nt35596s_video_display: qcom,dsi-display@18 { + compatible = "qcom,dsi-display"; + label = "dsi_jdi_fhd_nt35596s_video_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, + <&mdss_dsi0_pll PCLK_MUX_0_CLK>; + clock-names = "src_byte_clk", "src_pixel_clk"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + /* qcom,panel-errfg-gpio = <&tlmm 52 0>; */ + + qcom,dsi-panel = <&dsi_jdi_fhd_nt35596s_video>; + vddio-supply = <&pm8998_l14>; + lab-supply = <&lab_regulator>; + ibb-supply = <&ibb_regulator>; + }; + + dsi_tianma_fhd_nt36672a_video_display: qcom,dsi-display@21 { + compatible = "qcom,dsi-display"; + label = "dsi_tianma_fhd_nt36672a_video_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, + <&mdss_dsi0_pll PCLK_MUX_0_CLK>; + clock-names = "src_byte_clk", "src_pixel_clk"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + /* qcom,panel-errfg-gpio = <&tlmm 52 0>; */ + + qcom,dsi-panel = <&dsi_tianma_fhd_nt36672a_video>; + vddio-supply = <&pm8998_l14>; + lab-supply = <&lab_regulator>; + ibb-supply = <&ibb_regulator>; + }; +}; + +&dsi_jdi_fhd_r63452_cmd { + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1a 04 06 0a 0a 05 + 06 05 03 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_jdi_fhd_nt35596s_video { + qcom,mdss-dsi-t-clk-post = <0x0E>; + qcom,mdss-dsi-t-clk-pre = <0x34>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 22 08 08 24 24 08 08 05 03 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_tianma_fhd_nt36672a_video { + qcom,mdss-dsi-t-clk-post = <0x0E>; + qcom,mdss-dsi-t-clk-pre = <0x34>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 21 08 08 25 23 08 08 06 03 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + + +&ibb_regulator { + qcom,qpnp-ibb-discharge-resistor = <300>; +}; diff --git a/arch/arm64/configs/polaris_user_defconfig b/arch/arm64/configs/polaris_user_defconfig new file mode 100644 index 0000000000000..6f085f894da26 --- /dev/null +++ b/arch/arm64/configs/polaris_user_defconfig @@ -0,0 +1,668 @@ +CONFIG_LOCALVERSION="-perf" +# CONFIG_FHANDLE is not set +CONFIG_AUDIT=y +# CONFIG_AUDITSYSCALL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_SCHED_WALT=y +CONFIG_TASKSTATS=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_RCU_EXPERT=y +CONFIG_RCU_FAST_NO_HZ=y +CONFIG_RCU_NOCB_CPU=y +CONFIG_RCU_NOCB_CPU_ALL=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_SCHEDTUNE=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_BPF=y +CONFIG_SCHED_CORE_CTL=y +CONFIG_SCHED_CORE_ROTATE=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_PID_NS is not set +CONFIG_SCHED_AUTOGROUP=y +CONFIG_SCHED_TUNE=y +CONFIG_DEFAULT_USE_ENERGY_AWARE=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_KALLSYMS_ALL=y +CONFIG_BPF_SYSCALL=y +# CONFIG_AIO is not set +# CONFIG_MEMBARRIER is not set +CONFIG_EMBEDDED=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_PROFILING=y +CONFIG_CC_STACKPROTECTOR_STRONG=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=16 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SIG +# CONFIG_MODULE_SIG_FORCE +# CONFIG_MODULE_SIG_SHA512 +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_SDM845=y +CONFIG_PCI=y +CONFIG_PCI_MSM=y +CONFIG_SCHED_MC=y +CONFIG_NR_CPUS=8 +CONFIG_PREEMPT=y +CONFIG_HZ_100=y +CONFIG_CMA=y +CONFIG_ZSMALLOC=y +CONFIG_BALANCE_ANON_FILE_RECLAIM=y +CONFIG_SECCOMP=y +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y +# CONFIG_ARM64_VHE is not set +CONFIG_RANDOMIZE_BASE=y +# CONFIG_RANDOMIZE_MODULE_REGION_FULL is not set +# CONFIG_EFI is not set +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_COMPAT=y +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_BOOST=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_DIAG_DESTROY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_NOTRACK=y +CONFIG_NETFILTER_XT_TARGET_TEE=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_TARGET_SECMARK=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_DSCP=y +CONFIG_NETFILTER_XT_MATCH_ESP=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_RPFILTER=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_SECURITY=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_IPTABLES_128=y +CONFIG_IP6_NF_MATCH_RPFILTER=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_BROUTE=y +CONFIG_L2TP=y +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=y +CONFIG_L2TP_ETH=y +CONFIG_BRIDGE=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_SCH_MULTIQ=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_CLS_FW=y +CONFIG_NET_CLS_U32=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=y +CONFIG_NET_EMATCH_NBYTE=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_EMATCH_META=y +CONFIG_NET_EMATCH_TEXT=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_GACT=y +CONFIG_NET_ACT_MIRRED=y +CONFIG_NET_ACT_SKBEDIT=y +CONFIG_RMNET_DATA=y +CONFIG_RMNET_DATA_FC=y +CONFIG_RMNET_DATA_DEBUG_PKT=y +CONFIG_BT=y +CONFIG_MSM_BT_POWER=y +CONFIG_CFG80211=y +CONFIG_CFG80211_INTERNAL_REGDB=y +CONFIG_RFKILL=y +CONFIG_NFC_NQ=y +CONFIG_IPC_ROUTER=y +CONFIG_IPC_ROUTER_SECURITY=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y +CONFIG_DMA_CMA=y +CONFIG_ZRAM=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_QSEECOM=y +CONFIG_UID_SYS_STATS=y +CONFIG_UID_CPUTIME=y +CONFIG_MEMORY_STATE_TIME=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_UFSHCD=y +CONFIG_SCSI_UFSHCD_PLATFORM=y +CONFIG_SCSI_UFS_QCOM=y +CONFIG_SCSI_UFS_QCOM_ICE=y +CONFIG_SCSI_UFSHCD_CMD_LOGGING=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_DEBUG=y +CONFIG_DM_CRYPT=y +CONFIG_DM_REQ_CRYPT=y +CONFIG_DM_UEVENT=y +CONFIG_DM_VERITY=y +CONFIG_DM_VERITY_FEC=y +CONFIG_NETDEVICES=y +CONFIG_BONDING=y +CONFIG_DUMMY=y +CONFIG_TUN=y +CONFIG_SKY2=y +CONFIG_SMSC911X=y +CONFIG_PPP=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=y +CONFIG_PPPOL2TP=y +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y +CONFIG_PPP_ASYNC=y +CONFIG_PPP_SYNC_TTY=y +CONFIG_USB_USBNET=y +CONFIG_WIL6210=m +# CONFIG_WIL6210_TRACING is not set +CONFIG_WCNSS_MEM_PRE_ALLOC=y +CONFIG_CLD_LL_CORE=y +CONFIG_CNSS_GENL=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCH_COUNT_DUMP=y +CONFIG_LAST_TOUCH_EVENTS=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FORCE=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C_FORCE=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_FORCE=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV_FORCE=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_FORCE=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_TEST_REPORTING_FORCE=y +CONFIG_TOUCHSCREEN_ST_FTS=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_QPNP_POWER_ON=y +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_FINGERPRINT=y +CONFIG_FINGERPRINT_GOODIX_TA=y +CONFIG_FINGERPRINT_FPC_TEE=y +# CONFIG_SERIO_SERPORT is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVMEM is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_MSM_GENI=y +CONFIG_DIAG_CHAR=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM_LEGACY=y +# CONFIG_DEVPORT is not set +CONFIG_MSM_ADSPRPC=y +CONFIG_MSM_RDBG=m +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_QCOM_GENI=y +CONFIG_SPI=y +CONFIG_SPI_QUP=y +CONFIG_SPI_QCOM_GENI=y +CONFIG_SPI_SPIDEV=y +CONFIG_SLIMBUS_MSM_NGD=y +CONFIG_SPMI=y +CONFIG_SPMI_MSM_PMIC_ARB_DEBUG=y +CONFIG_PINCTRL_SDM845=y +CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_RESET_QCOM=y +CONFIG_QCOM_DLOAD_MODE=y +CONFIG_POWER_RESET_XGENE=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_QPNP_FG_GEN3=y +CONFIG_SMB1355_SLAVE_CHARGER=y +CONFIG_QPNP_SMB2=y +CONFIG_QPNP_QNOVO=y +CONFIG_IDT_P9220=y +CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y +CONFIG_THERMAL=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_LOW_LIMITS=y +CONFIG_CPU_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y +CONFIG_QCOM_SPMI_TEMP_ALARM=y +CONFIG_THERMAL_QPNP=y +CONFIG_THERMAL_QPNP_ADC_TM=y +CONFIG_THERMAL_TSENS=y +CONFIG_MSM_BCL_PERIPHERAL_CTL=y +CONFIG_QTI_THERMAL_LIMITS_DCVS=y +CONFIG_QTI_VIRTUAL_SENSOR=y +CONFIG_QTI_AOP_REG_COOLING_DEVICE=y +CONFIG_QTI_QMI_COOLING_DEVICE=y +CONFIG_REGULATOR_COOLING_DEVICE=y +CONFIG_MFD_I2C_PMIC=y +CONFIG_MFD_SPMI_PMIC=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_PROXY_CONSUMER=y +CONFIG_REGULATOR_QPNP_LABIBB=y +CONFIG_REGULATOR_QPNP=y +CONFIG_REGULATOR_REFGEN=y +CONFIG_REGULATOR_RPMH=y +CONFIG_REGULATOR_STUB=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_ADV_DEBUG=y +CONFIG_VIDEO_FIXED_MINOR_RANGES=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SPECTRA_CAMERA=y +CONFIG_MSM_VIDC_V4L2=y +CONFIG_MSM_VIDC_GOVERNORS=y +CONFIG_MSM_SDE_ROTATOR=y +CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG=y +CONFIG_DVB_MPQ=m +CONFIG_DVB_MPQ_DEMUX=m +CONFIG_DVB_MPQ_TSPP1=y +CONFIG_TSPP=m +CONFIG_QCOM_KGSL=y +CONFIG_DRM=y +CONFIG_DRM_SDE_EVTLOG_DEBUG=y +CONFIG_DRM_SDE_RSC=y +# CONFIG_DRM_SDE_XLOG_DEBUG is not set +CONFIG_FB_VIRTUAL=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_USB_AUDIO=y +CONFIG_SND_USB_AUDIO_QMI=y +CONFIG_SND_SOC=y +CONFIG_UHID=y +CONFIG_HID_APPLE=y +CONFIG_HID_ELECOM=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MULTITOUCH=y +CONFIG_HID_PLANTRONICS=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_MSM=y +CONFIG_USB_ISP1760=y +CONFIG_USB_ISP1760_HOST_ROLE=y +CONFIG_USB_PD_POLICY=y +CONFIG_QPNP_USB_PDPHY=y +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_LINK_LAYER_TEST=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_DUAL_ROLE_USB_INTF=y +CONFIG_USB_MSM_SSPHY_QMP=y +CONFIG_MSM_QUSB_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_MTP=y +CONFIG_USB_CONFIGFS_F_PTP=y +CONFIG_USB_CONFIGFS_F_ACC=y +CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y +CONFIG_USB_CONFIGFS_UEVENT=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_DIAG=y +CONFIG_USB_CONFIGFS_F_CDEV=y +CONFIG_USB_CONFIGFS_F_CCID=y +CONFIG_USB_CONFIGFS_F_GSI=y +CONFIG_USB_CONFIGFS_F_QDSS=y +CONFIG_MMC=y +CONFIG_MMC_PERF_PROFILING=y +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_BLOCK_DEFERRED_RESUME=y +CONFIG_MMC_TEST=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_QPNP=y +CONFIG_LEDS_QPNP_FLASH_V2=y +CONFIG_LEDS_QPNP_WLED=y +CONFIG_LEDS_QPNP_HAPTICS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_QPNP=y +CONFIG_DMADEVICES=y +CONFIG_QCOM_GPI_DMA=y +CONFIG_UIO=y +CONFIG_UIO_MSM_SHAREDMEM=y +CONFIG_STAGING=y +CONFIG_ASHMEM=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_MULTIPLE_LMK=y +CONFIG_ION=y +CONFIG_ION_MSM=y +CONFIG_GSI=y +CONFIG_IPA3=y +CONFIG_RMNET_IPA3=y +CONFIG_RNDIS_IPA=y +CONFIG_IPA_UT=y +CONFIG_SPS=y +CONFIG_SPS_SUPPORT_NDP_BAM=y +CONFIG_QPNP_COINCELL=y +CONFIG_QPNP_REVID=y +CONFIG_USB_BAM=y +CONFIG_MSM_11AD=m +CONFIG_SEEMP_CORE=y +CONFIG_QCOM_GENI_SE=y +CONFIG_MSM_GCC_SDM845=y +CONFIG_MSM_VIDEOCC_SDM845=y +CONFIG_MSM_CAMCC_SDM845=y +CONFIG_MSM_DISPCC_SDM845=y +CONFIG_CLOCK_QPNP_DIV=y +CONFIG_MSM_CLK_RPMH=y +CONFIG_CLOCK_CPU_OSM=y +CONFIG_MSM_GPUCC_SDM845=y +CONFIG_MSM_CLK_AOP_QMP=y +CONFIG_QCOM_MDSS_PLL=y +CONFIG_REMOTE_SPINLOCK_MSM=y +CONFIG_MSM_QMP=y +CONFIG_IOMMU_IO_PGTABLE_FAST=y +CONFIG_ARM_SMMU=y +CONFIG_QCOM_LAZY_MAPPING=y +CONFIG_IOMMU_DEBUG=y +CONFIG_IOMMU_DEBUG_TRACKING=y +CONFIG_IOMMU_TESTS=y +CONFIG_QCOM_RUN_QUEUE_STATS=y +CONFIG_QCOM_LLCC=y +CONFIG_QCOM_SDM845_LLCC=y +CONFIG_QCOM_LLCC_PERFMON=m +CONFIG_MSM_SERVICE_LOCATOR=y +CONFIG_MSM_SERVICE_NOTIFIER=y +CONFIG_MSM_BOOT_STATS=y +CONFIG_QCOM_EUD=y +CONFIG_QCOM_WATCHDOG_V2=y +CONFIG_QCOM_MEMORY_DUMP_V2=y +CONFIG_MINIDUMP=y +# CONFIG_COMMON_LOG is not set +CONFIG_QCOM_BUS_SCALING=y +CONFIG_QCOM_BUS_CONFIG_RPMH=y +CONFIG_QCOM_SECURE_BUFFER=y +CONFIG_QCOM_EARLY_RANDOM=y +CONFIG_MSM_SMEM=y +CONFIG_MSM_GLINK=y +CONFIG_MSM_GLINK_LOOPBACK_SERVER=y +CONFIG_MSM_GLINK_SMEM_NATIVE_XPRT=y +CONFIG_MSM_GLINK_SPI_XPRT=y +CONFIG_MSM_SPCOM=y +CONFIG_MSM_SPSS_UTILS=y +CONFIG_TRACER_PKT=y +CONFIG_QTI_RPMH_API=y +CONFIG_MSM_SMP2P=y +CONFIG_MSM_IPC_ROUTER_GLINK_XPRT=y +CONFIG_MSM_QMI_INTERFACE=y +CONFIG_MSM_GLINK_PKT=y +CONFIG_MSM_SUBSYSTEM_RESTART=y +CONFIG_MSM_PIL=y +CONFIG_MSM_SYSMON_GLINK_COMM=y +CONFIG_MSM_PIL_SSR_GENERIC=y +CONFIG_MSM_PIL_MSS_QDSP6V5=y +CONFIG_ICNSS=y +CONFIG_QCOM_COMMAND_DB=y +CONFIG_MSM_PERFORMANCE=y +CONFIG_MSM_CDSP_LOADER=y +CONFIG_QCOM_SMCINVOKE=y +CONFIG_MSM_EVENT_TIMER=y +CONFIG_MSM_PM=y +CONFIG_MSM_QBT1000=y +CONFIG_QTI_RPM_STATS_LOG=y +CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y +CONFIG_QMP_DEBUGFS_CLIENT=y +CONFIG_MEM_SHARE_QMI_SERVICE=y +CONFIG_QSEE_IPC_IRQ_BRIDGE=y +CONFIG_QCOM_BIMC_BWMON=y +CONFIG_ARM_MEMLAT_MON=y +CONFIG_QCOMCCI_HWMON=y +CONFIG_QCOM_M4M_HWMON=y +CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y +CONFIG_DEVFREQ_GOV_QCOM_CACHE_HWMON=y +CONFIG_DEVFREQ_GOV_MEMLAT=y +CONFIG_DEVFREQ_SIMPLE_DEV=y +CONFIG_QCOM_DEVFREQ_DEVBW=y +CONFIG_EXTCON_USB_GPIO=y +CONFIG_IIO=y +CONFIG_QCOM_RRADC=y +CONFIG_PWM=y +CONFIG_PWM_QPNP=y +CONFIG_ARM_GIC_V3_ACL=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_SENSORS_SSC=y +CONFIG_MSM_TZ_LOG=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_ENCRYPTION=y +CONFIG_EXT4_FS_ENCRYPTION=y +CONFIG_EXT4_FS_ICE_ENCRYPTION=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_QFMT_V2=y +CONFIG_FUSE_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=y +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_SDCARD_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_SCHEDSTATS=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_IPC_LOGGING=y +CONFIG_CPU_FREQ_SWITCH_PROFILER=y +CONFIG_DEBUG_ALIGN_RODATA=y +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_QCOM_REPLICATOR=y +CONFIG_CORESIGHT_STM=y +CONFIG_CORESIGHT_TPDA=y +CONFIG_CORESIGHT_TPDM=y +CONFIG_CORESIGHT_CTI=y +CONFIG_CORESIGHT_EVENT=y +CONFIG_CORESIGHT_HWEVENT=y +CONFIG_CORESIGHT_DUMMY=y +CONFIG_PFK=y +CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y +CONFIG_SECURITY=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_FORTIFY_SOURCE=y +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SMACK=y +# CONFIG_CRYPTO_CTR is not set +CONFIG_CRYPTO_XCBC=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y +CONFIG_CRYPTO_DEV_QCRYPTO=y +CONFIG_CRYPTO_DEV_QCEDEV=y +CONFIG_CRYPTO_DEV_QCOM_ICE=y +CONFIG_ARM64_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y +CONFIG_CRYPTO_CRC32_ARM64=y +CONFIG_QMI_ENCDEC=y +CONFIG_LOG_BUF_SHIFT=21 +CONFIG_PSTORE=y +CONFIG_PSTORE_RAM=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_PMSG=y +CONFIG_CMDLINE="ramoops_memreserve=4M" +CONFIG_CMDLINE_EXTEND=y +CONFIG_SDCARD_FS=y +CONFIG_F2FS_FS=y +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_FS_ENCRYPTION=y +CONFIG_F2FS_FS_ENCRYPTION=y +CONFIG_EXT4_ANDROID_FS_ENCRYPTION=y + +#Add CIFS Config +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_CIFS=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_UTF8=y + +CONFIG_BOOT_INFO=y +CONFIG_OF_FLATTREE=y + +CONFIG_QCOM_DCC_V2=y diff --git a/arch/arm64/configs/sdm845-perf_defconfig b/arch/arm64/configs/sdm845-perf_defconfig index 0734d0f0f29c8..f34f9831376a9 100644 --- a/arch/arm64/configs/sdm845-perf_defconfig +++ b/arch/arm64/configs/sdm845-perf_defconfig @@ -64,7 +64,6 @@ CONFIG_CMA=y CONFIG_ZSMALLOC=y CONFIG_BALANCE_ANON_FILE_RECLAIM=y CONFIG_SECCOMP=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y CONFIG_ARMV8_DEPRECATED=y CONFIG_SWP_EMULATION=y CONFIG_CP15_BARRIER_EMULATION=y diff --git a/arch/arm64/configs/sdm845_defconfig b/arch/arm64/configs/sdm845_defconfig index 798e697ee1548..56a99304b42fc 100644 --- a/arch/arm64/configs/sdm845_defconfig +++ b/arch/arm64/configs/sdm845_defconfig @@ -68,7 +68,6 @@ CONFIG_CMA_DEBUGFS=y CONFIG_ZSMALLOC=y CONFIG_BALANCE_ANON_FILE_RECLAIM=y CONFIG_SECCOMP=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y CONFIG_ARMV8_DEPRECATED=y CONFIG_SWP_EMULATION=y CONFIG_CP15_BARRIER_EMULATION=y @@ -302,7 +301,6 @@ CONFIG_INPUT_UINPUT=y # CONFIG_VT is not set # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_MSM_GENI=y -CONFIG_SERIAL_MSM_GENI_CONSOLE=y CONFIG_DIAG_CHAR=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_MSM_LEGACY=y @@ -455,6 +453,7 @@ CONFIG_LEDS_TRIGGERS=y CONFIG_EDAC=y CONFIG_EDAC_MM_EDAC=y CONFIG_EDAC_KRYO3XX_ARM64=y +CONFIG_EDAC_KRYO3XX_ARM64_PANIC_ON_CE=y CONFIG_EDAC_KRYO3XX_ARM64_PANIC_ON_UE=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_QPNP=y @@ -605,6 +604,7 @@ CONFIG_DEBUG_OBJECTS=y CONFIG_DEBUG_OBJECTS_FREE=y CONFIG_DEBUG_OBJECTS_TIMERS=y CONFIG_DEBUG_OBJECTS_WORK=y +CONFIG_DEBUG_OBJECTS_RCU_HEAD=y CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y CONFIG_SLUB_DEBUG_ON=y CONFIG_DEBUG_KMEMLEAK=y diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 46d04485c999a..ef5970e11c447 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -452,4 +452,17 @@ alternative_endif mrs \rd, sp_el0 .endm +/* + * Errata workaround post TTBR0_EL1 update. + */ + .macro post_ttbr0_update_workaround +#ifdef CONFIG_CAVIUM_ERRATUM_27456 +alternative_if ARM64_WORKAROUND_CAVIUM_27456 + ic iallu + dsb nsh + isb +alternative_else_nop_endif +#endif + .endm + #endif /* __ASM_ASSEMBLER_H */ diff --git a/arch/arm64/include/asm/bootinfo.h b/arch/arm64/include/asm/bootinfo.h new file mode 100644 index 0000000000000..0d02d476c90c6 --- /dev/null +++ b/arch/arm64/include/asm/bootinfo.h @@ -0,0 +1,94 @@ +/* + * bootinfo.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASMARM_BOOTINFO_H +#define __ASMARM_BOOTINFO_H + +#define HW_DEVID_VERSION_SHIFT 8 +#define HW_DEVID_VERSION_MASK 0xF00UL +#define HW_MAJOR_VERSION_SHIFT 4 +#define HW_MAJOR_VERSION_MASK 0xF0 +#define HW_MINOR_VERSION_SHIFT 0 +#define HW_MINOR_VERSION_MASK 0x0F + +typedef enum { + PU_REASON_EVENT_HWRST, + PU_REASON_EVENT_SMPL, + PU_REASON_EVENT_RTC, + PU_REASON_EVENT_DC_CHG, + PU_REASON_EVENT_USB_CHG, + PU_REASON_EVENT_PON1, + PU_REASON_EVENT_CABLE, + PU_REASON_EVENT_KPD, + PU_REASON_EVENT_WARMRST, + PU_REASON_EVENT_LPK, + PU_REASON_MAX +} powerup_reason_t; + +enum { + RS_REASON_EVENT_WDOG, + RS_REASON_EVENT_KPANIC, + RS_REASON_EVENT_NORMAL, + RS_REASON_EVENT_OTHER, + RS_REASON_MAX +}; + +typedef enum { + POFF_REASON_EVENT_SOFT, + POFF_REASON_EVENT_PS_HOLD, + POFF_REASON_EVENT_PMIC_WD, + POFF_REASON_EVENT_GP1_KPD1, + POFF_REASON_EVENT_GP2_KPD2, + POFF_REASON_EVENT_KPDPWR_AND_RESIN, + POFF_REASON_EVENT_RESIN_N, + POFF_REASON_EVENT_KPDPWR_N, + POFF_REASON_EVENT_RESEVER1, + POFF_REASON_EVENT_RESEVER2, + POFF_REASON_EVENT_RESEVER3, + POFF_REASON_EVENT_CHARGER, + POFF_REASON_EVENT_TFT, + POFF_REASON_EVENT_UVLO, + POFF_REASON_EVENT_OTST3, + POFF_REASON_EVENT_STAGE3, + POFF_REASON_EVENT_GP_FAULT0, + POFF_REASON_EVENT_GP_FAULT1, + POFF_REASON_EVENT_GP_FAULT2, + POFF_REASON_EVENT_GP_FAULT3, + POFF_REASON_EVENT_MBG_FAULT, + POFF_REASON_EVENT_OVLO, + POFF_REASON_EVENT_GEN2_UVLO, + POFF_REASON_EVENT_AVDD_RB, + POFF_REASON_EVENT_RESEVER4, + POFF_REASON_EVENT_RESEVER5, + POFF_REASON_EVENT_RESEVER6, + POFF_REASON_EVENT_FAULT_FAULT_N, + POFF_REASON_EVENT_FAULT_PBS_WATCHDOG_TO, + POFF_REASON_EVENT_FAULT_PBS_NACK, + POFF_REASON_EVENT_FAULT_RESTART_PON, + POFF_REASON_EVENT_GEN2_OTST3, + POFF_REASON_EVENT_RESEVER7, + POFF_REASON_EVENT_RESEVER8, + POFF_REASON_EVENT_RESEVER9, + POFF_REASON_EVENT_RESEVER10, + POFF_REASON_EVENT_S3_RESET_FAULT_N, + POFF_REASON_EVENT_S3_RESET_PBS_WATCHDOG_TO, + POFF_REASON_EVENT_S3_RESET_PBS_NACK, + POFF_REASON_EVENT_S3_RESET_KPDPWR_ANDOR_RESIN, + POFF_REASON_MAX +} poweroff_reason_t; + +#define RESTART_EVENT_WDOG 0x10000 +#define RESTART_EVENT_KPANIC 0x20000 +#define RESTART_EVENT_NORMAL 0x40000 +#define RESTART_EVENT_OTHER 0x80000 + +void set_poweroff_reason(int poweroff_reason); +unsigned int get_powerup_reason(void); +int is_abnormal_powerup(void); +void set_powerup_reason(unsigned int powerup_reason); +#endif diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index d64bf94a79a1e..87b4465351855 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -35,10 +35,6 @@ #define ARM64_HYP_OFFSET_LOW 14 #define ARM64_MISMATCHED_CACHE_LINE_SIZE 15 -#define ARM64_UNMAP_KERNEL_AT_EL0 16 - -#define ARM64_HARDEN_BRANCH_PREDICTOR 17 - -#define ARM64_NCAPS 18 +#define ARM64_NCAPS 16 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index ddbf3b12b9153..f8682a3277009 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -63,6 +63,7 @@ ({ \ u32 _model = (midr) & MIDR_CPU_MODEL_MASK; \ u32 rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \ + \ _model == (model) && rv >= (rv_min) && rv <= (rv_max); \ }) @@ -75,11 +76,7 @@ #define ARM_CPU_PART_AEM_V8 0xD0F #define ARM_CPU_PART_FOUNDATION 0xD00 #define ARM_CPU_PART_CORTEX_A57 0xD07 -#define ARM_CPU_PART_CORTEX_A72 0xD08 #define ARM_CPU_PART_CORTEX_A53 0xD03 -#define ARM_CPU_PART_CORTEX_A73 0xD09 -#define ARM_CPU_PART_CORTEX_A75 0xD0A -#define ARM_CPU_PART_KRYO3G 0x802 #define APM_CPU_PART_POTENZA 0x000 @@ -90,10 +87,6 @@ #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) -#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) -#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) -#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) -#define MIDR_KRYO3G MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO3G) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h index 1fb023076dfcb..9e46782d0107c 100644 --- a/arch/arm64/include/asm/elf.h +++ b/arch/arm64/include/asm/elf.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2012 ARM Ltd. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -113,11 +114,12 @@ #define ELF_EXEC_PAGESIZE PAGE_SIZE /* - * This is the base location for PIE (ET_DYN with INTERP) loads. On - * 64-bit, this is above 4GB to leave the entire 32-bit address - * space open for things that want to use the area for 32-bit pointers. + * This is the location that an ET_DYN program is loaded if exec'ed. Typical + * use of this is to invoke "./ld.so someprog" to test out a new version of + * the loader. We need to make sure that it is out of the way of the program + * that it will "exec", and that there is sufficient room for the brk. */ -#define ELF_ET_DYN_BASE (2 * TASK_SIZE_64 / 3) +#define ELF_ET_DYN_BASE (2 * TASK_SIZE_64 / 3) #ifndef __ASSEMBLY__ @@ -168,8 +170,7 @@ extern int arch_setup_additional_pages(struct linux_binprm *bprm, #ifdef CONFIG_COMPAT -/* PIE load location for compat arm. Must match ARM ELF_ET_DYN_BASE. */ -#define COMPAT_ELF_ET_DYN_BASE 0x000400000UL +#define COMPAT_ELF_ET_DYN_BASE (2 * TASK_SIZE_32 / 3) /* AArch32 registers. */ #define COMPAT_ELF_NGREG 18 diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index 85997c0e54431..d14c478976d0a 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -175,12 +175,6 @@ #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ ESR_ELx_SYS64_ISS_DIR_READ) -#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ - ESR_ELx_SYS64_ISS_DIR_READ) - -#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \ - ESR_ELx_SYS64_ISS_DIR_READ) - #ifndef __ASSEMBLY__ #include diff --git a/arch/arm64/include/asm/fixmap.h b/arch/arm64/include/asm/fixmap.h index d8e58051f32d4..caf86be815ba2 100644 --- a/arch/arm64/include/asm/fixmap.h +++ b/arch/arm64/include/asm/fixmap.h @@ -51,12 +51,6 @@ enum fixed_addresses { FIX_EARLYCON_MEM_BASE, FIX_TEXT_POKE0, - -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 - FIX_ENTRY_TRAMP_DATA, - FIX_ENTRY_TRAMP_TEXT, -#define TRAMP_VALIAS (__fix_to_virt(FIX_ENTRY_TRAMP_TEXT)) -#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ __end_of_permanent_fixed_addresses, /* diff --git a/arch/arm64/include/asm/kernel-pgtable.h b/arch/arm64/include/asm/kernel-pgtable.h index 77a27af013710..7803343e5881f 100644 --- a/arch/arm64/include/asm/kernel-pgtable.h +++ b/arch/arm64/include/asm/kernel-pgtable.h @@ -78,16 +78,8 @@ /* * Initial memory map attributes. */ -#define _SWAPPER_PTE_FLAGS (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) -#define _SWAPPER_PMD_FLAGS (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) - -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 -#define SWAPPER_PTE_FLAGS (_SWAPPER_PTE_FLAGS | PTE_NG) -#define SWAPPER_PMD_FLAGS (_SWAPPER_PMD_FLAGS | PMD_SECT_NG) -#else -#define SWAPPER_PTE_FLAGS _SWAPPER_PTE_FLAGS -#define SWAPPER_PMD_FLAGS _SWAPPER_PMD_FLAGS -#endif +#define SWAPPER_PTE_FLAGS (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) +#define SWAPPER_PMD_FLAGS (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) #if ARM64_SWAPPER_USES_SECTION_MAPS #define SWAPPER_MM_MMUFLAGS (PMD_ATTRINDX(MT_NORMAL) | SWAPPER_PMD_FLAGS) diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h index 35ea9c1206f0e..ef305f89a73e2 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -313,43 +313,5 @@ static inline unsigned int kvm_get_vmid_bits(void) return (cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR1_VMIDBITS_SHIFT) == 2) ? 16 : 8; } -#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR -#include - -static inline void *kvm_get_hyp_vector(void) -{ - struct bp_hardening_data *data = arm64_get_bp_hardening_data(); - void *vect = kvm_ksym_ref(__kvm_hyp_vector); - - if (data->fn) { - vect = __bp_harden_hyp_vecs_start + - data->hyp_vectors_slot * SZ_2K; - - if (!has_vhe()) - vect = lm_alias(vect); - } - - return vect; -} - -static inline int kvm_map_vectors(void) -{ - return create_hyp_mappings(kvm_ksym_ref(__bp_harden_hyp_vecs_start), - kvm_ksym_ref(__bp_harden_hyp_vecs_end), - PAGE_HYP_EXEC); -} - -#else -static inline void *kvm_get_hyp_vector(void) -{ - return kvm_ksym_ref(__kvm_hyp_vector); -} - -static inline int kvm_map_vectors(void) -{ - return 0; -} -#endif - #endif /* __ASSEMBLY__ */ #endif /* __ARM64_KVM_MMU_H__ */ diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h index f543df3a59218..8d9fce037b2fc 100644 --- a/arch/arm64/include/asm/mmu.h +++ b/arch/arm64/include/asm/mmu.h @@ -16,13 +16,6 @@ #ifndef __ASM_MMU_H #define __ASM_MMU_H -#define USER_ASID_FLAG (UL(1) << 48) -#define TTBR_ASID_MASK (UL(0xffff) << 48) - -#ifndef __ASSEMBLY__ - -#include - typedef struct { atomic64_t id; void *vdso; @@ -35,49 +28,6 @@ typedef struct { */ #define ASID(mm) ((mm)->context.id.counter & 0xffff) -static inline bool arm64_kernel_unmapped_at_el0(void) -{ - return IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0) && - cpus_have_cap(ARM64_UNMAP_KERNEL_AT_EL0); -} - -typedef void (*bp_hardening_cb_t)(void); - -struct bp_hardening_data { - int hyp_vectors_slot; - bp_hardening_cb_t fn; -}; - -#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR -extern char __bp_harden_hyp_vecs_start[], __bp_harden_hyp_vecs_end[]; - -DECLARE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); - -static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void) -{ - return raw_cpu_ptr(&bp_hardening_data); -} - -static inline void arm64_apply_bp_hardening(void) -{ - struct bp_hardening_data *d; - - if (!cpus_have_cap(ARM64_HARDEN_BRANCH_PREDICTOR)) - return; - - d = arm64_get_bp_hardening_data(); - if (d->fn) - d->fn(); -} -#else -static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void) -{ - return NULL; -} - -static inline void arm64_apply_bp_hardening(void) { } -#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ - extern void paging_init(void); extern void bootmem_init(void); extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt); @@ -87,5 +37,4 @@ extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys, pgprot_t prot, bool allow_block_mappings); extern void *fixmap_remap_fdt(phys_addr_t dt_phys); -#endif /* !__ASSEMBLY__ */ #endif diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index af0215ac4d52a..8f8dde1790170 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -57,13 +57,6 @@ static inline void cpu_set_reserved_ttbr0(void) isb(); } -static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm) -{ - BUG_ON(pgd == swapper_pg_dir); - cpu_set_reserved_ttbr0(); - cpu_do_switch_mm(virt_to_phys(pgd),mm); -} - /* * TCR.T0SZ value to use when the ID map is active. Usually equals * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index 8df4cb6ac6f71..eb0c2bd90de90 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -272,7 +272,6 @@ #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT) #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT) -#define TCR_A1 (UL(1) << 22) #define TCR_ASID16 (UL(1) << 36) #define TCR_TBI0 (UL(1) << 37) #define TCR_HA (UL(1) << 39) diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h index 84b5283d2e7fe..d6dae29133991 100644 --- a/arch/arm64/include/asm/pgtable-prot.h +++ b/arch/arm64/include/asm/pgtable-prot.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 ARM Ltd. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -34,16 +35,8 @@ #include -#define _PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) -#define _PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) - -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 -#define PROT_DEFAULT (_PROT_DEFAULT | PTE_NG) -#define PROT_SECT_DEFAULT (_PROT_SECT_DEFAULT | PMD_SECT_NG) -#else -#define PROT_DEFAULT _PROT_DEFAULT -#define PROT_SECT_DEFAULT _PROT_SECT_DEFAULT -#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ +#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED) +#define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S) #define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE)) #define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE)) @@ -56,7 +49,6 @@ #define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL)) #define _PAGE_DEFAULT (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL)) -#define _HYP_PAGE_DEFAULT (_PAGE_DEFAULT & ~PTE_NG) #define PAGE_KERNEL __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE) #define PAGE_KERNEL_RO __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_RDONLY) @@ -64,15 +56,15 @@ #define PAGE_KERNEL_EXEC __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE) #define PAGE_KERNEL_EXEC_CONT __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_CONT) -#define PAGE_HYP __pgprot(_HYP_PAGE_DEFAULT | PTE_HYP | PTE_HYP_XN) -#define PAGE_HYP_EXEC __pgprot(_HYP_PAGE_DEFAULT | PTE_HYP | PTE_RDONLY) -#define PAGE_HYP_RO __pgprot(_HYP_PAGE_DEFAULT | PTE_HYP | PTE_RDONLY | PTE_HYP_XN) +#define PAGE_HYP __pgprot(_PAGE_DEFAULT | PTE_HYP | PTE_HYP_XN) +#define PAGE_HYP_EXEC __pgprot(_PAGE_DEFAULT | PTE_HYP | PTE_RDONLY) +#define PAGE_HYP_RO __pgprot(_PAGE_DEFAULT | PTE_HYP | PTE_RDONLY | PTE_HYP_XN) #define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP) #define PAGE_S2 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY) #define PAGE_S2_DEVICE __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN) -#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_NG | PTE_PXN | PTE_UXN) +#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_PXN | PTE_UXN) #define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE) #define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE) #define PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 0adb30ad1330d..c05ee84d98eb4 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -707,7 +707,6 @@ static inline void pmdp_set_wrprotect(struct mm_struct *mm, extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; -extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; /* * Encode and decode a swap entry: diff --git a/arch/arm64/include/asm/proc-fns.h b/arch/arm64/include/asm/proc-fns.h index 9da52c2c6c5c3..e1d4f2906cae2 100644 --- a/arch/arm64/include/asm/proc-fns.h +++ b/arch/arm64/include/asm/proc-fns.h @@ -4,6 +4,7 @@ * Copyright (C) 1997-1999 Russell King * Copyright (C) 2000 Deep Blue Solutions Ltd * Copyright (C) 2012 ARM Ltd. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -39,6 +40,12 @@ extern u64 cpu_do_resume(phys_addr_t ptr, u64 idmap_ttbr); #include +#define cpu_switch_mm(pgd, mm) \ +do { \ + BUG_ON(pgd == swapper_pg_dir); \ + cpu_do_switch_mm(virt_to_phys(pgd), mm); \ +} while (0) + #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ #endif /* __ASM_PROCFNS_H */ diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 88bbe364b6ae0..7393cc767edb7 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -117,9 +117,6 @@ #define ID_AA64ISAR0_AES_SHIFT 4 /* id_aa64pfr0 */ -#define ID_AA64PFR0_CSV3_SHIFT 60 -#define ID_AA64PFR0_CSV2_SHIFT 56 -#define ID_AA64PFR0_SVE_SHIFT 32 #define ID_AA64PFR0_GIC_SHIFT 24 #define ID_AA64PFR0_ASIMD_SHIFT 20 #define ID_AA64PFR0_FP_SHIFT 16 diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index ad6bd8b26ada0..deab523741197 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -23,7 +23,6 @@ #include #include -#include /* * Raw TLBI operations. @@ -43,11 +42,6 @@ #define __tlbi(op, ...) __TLBI_N(op, ##__VA_ARGS__, 1, 0) -#define __tlbi_user(op, arg) do { \ - if (arm64_kernel_unmapped_at_el0()) \ - __tlbi(op, (arg) | USER_ASID_FLAG); \ -} while (0) - /* * TLB Management * ============== @@ -109,7 +103,6 @@ static inline void flush_tlb_mm(struct mm_struct *mm) dsb(ishst); __tlbi(aside1is, asid); - __tlbi_user(aside1is, asid); dsb(ish); } @@ -120,7 +113,6 @@ static inline void flush_tlb_page(struct vm_area_struct *vma, dsb(ishst); __tlbi(vale1is, addr); - __tlbi_user(vale1is, addr); dsb(ish); } @@ -147,13 +139,10 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, dsb(ishst); for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) { - if (last_level) { + if (last_level) __tlbi(vale1is, addr); - __tlbi_user(vale1is, addr); - } else { + else __tlbi(vae1is, addr); - __tlbi_user(vae1is, addr); - } } dsb(ish); } @@ -193,7 +182,6 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, unsigned long addr = uaddr >> 12 | (ASID(mm) << 48); __tlbi(vae1is, addr); - __tlbi_user(vae1is, addr); dsb(ish); } diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 8b38b0de3e8bb..6829e5e589d45 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -20,7 +20,6 @@ #include #include -#include #include #ifndef __ASSEMBLY__ @@ -134,19 +133,15 @@ static inline void __uaccess_ttbr0_disable(void) { unsigned long ttbr; - ttbr = read_sysreg(ttbr1_el1); /* reserved_ttbr0 placed at the end of swapper_pg_dir */ - write_sysreg(ttbr + SWAPPER_DIR_SIZE, ttbr0_el1); - isb(); - /* Set reserved ASID */ - ttbr &= ~TTBR_ASID_MASK; - write_sysreg(ttbr, ttbr1_el1); + ttbr = read_sysreg(ttbr1_el1) + SWAPPER_DIR_SIZE; + write_sysreg(ttbr, ttbr0_el1); isb(); } static inline void __uaccess_ttbr0_enable(void) { - unsigned long flags, ttbr0, ttbr1; + unsigned long flags; /* * Disable interrupts to avoid preemption between reading the 'ttbr0' @@ -154,16 +149,7 @@ static inline void __uaccess_ttbr0_enable(void) * roll-over and an update of 'ttbr0'. */ local_irq_save(flags); - ttbr0 = current_thread_info()->ttbr0; - - /* Restore active ASID */ - ttbr1 = read_sysreg(ttbr1_el1); - ttbr1 |= ttbr0 & TTBR_ASID_MASK; - write_sysreg(ttbr1, ttbr1_el1); - isb(); - - /* Restore user page table */ - write_sysreg(ttbr0, ttbr0_el1); + write_sysreg(current_thread_info()->ttbr0, ttbr0_el1); isb(); local_irq_restore(flags); } @@ -453,20 +439,11 @@ extern __must_check long strnlen_user(const char __user *str, long n); add \tmp1, \tmp1, #SWAPPER_DIR_SIZE // reserved_ttbr0 at the end of swapper_pg_dir msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 isb - sub \tmp1, \tmp1, #SWAPPER_DIR_SIZE - bic \tmp1, \tmp1, #TTBR_ASID_MASK - msr ttbr1_el1, \tmp1 // set reserved ASID - isb .endm - .macro __uaccess_ttbr0_enable, tmp1, tmp2 + .macro __uaccess_ttbr0_enable, tmp1 get_thread_info \tmp1 ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 - mrs \tmp2, ttbr1_el1 - extr \tmp2, \tmp2, \tmp1, #48 - ror \tmp2, \tmp2, #16 - msr ttbr1_el1, \tmp2 // set the active ASID - isb msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1 isb .endm @@ -477,18 +454,18 @@ alternative_if_not ARM64_HAS_PAN alternative_else_nop_endif .endm - .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 + .macro uaccess_ttbr0_enable, tmp1, tmp2 alternative_if_not ARM64_HAS_PAN - save_and_disable_irq \tmp3 // avoid preemption - __uaccess_ttbr0_enable \tmp1, \tmp2 - restore_irq \tmp3 + save_and_disable_irq \tmp2 + __uaccess_ttbr0_enable \tmp1 + restore_irq \tmp2 alternative_else_nop_endif .endm #else .macro uaccess_ttbr0_disable, tmp1 .endm - .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 + .macro uaccess_ttbr0_enable, tmp1, tmp2 .endm #endif @@ -502,8 +479,8 @@ alternative_if ARM64_ALT_PAN_NOT_UAO alternative_else_nop_endif .endm - .macro uaccess_enable_not_uao, tmp1, tmp2, tmp3 - uaccess_ttbr0_enable \tmp1, \tmp2, \tmp3 + .macro uaccess_enable_not_uao, tmp1, tmp2 + uaccess_ttbr0_enable \tmp1, \tmp2 alternative_if ARM64_ALT_PAN_NOT_UAO SET_PSTATE_PAN(0) alternative_else_nop_endif diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 446eabd3bc2a2..27d51e10f015c 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -40,6 +40,7 @@ arm64-obj-$(CONFIG_CPU_PM) += sleep.o suspend.o arm64-obj-$(CONFIG_CPU_IDLE) += cpuidle.o arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o arm64-obj-$(CONFIG_KGDB) += kgdb.o +arm64-obj-$(CONFIG_BOOT_INFO) += bootinfo.o arm64-obj-$(CONFIG_EFI) += efi.o efi-entry.stub.o arm64-obj-$(CONFIG_PCI) += pci.o arm64-obj-$(CONFIG_ARMV8_DEPRECATED) += armv8_deprecated.o @@ -52,10 +53,6 @@ arm64-obj-$(CONFIG_HIBERNATION) += hibernate.o hibernate-asm.o arm64-obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o \ cpu-reset.o -ifeq ($(CONFIG_KVM),y) -arm64-obj-$(CONFIG_HARDEN_BRANCH_PREDICTOR) += bpi.o -endif - obj-y += $(arm64-obj-y) vdso/ probes/ obj-m += $(arm64-obj-m) head-y := head.o diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c index 5d2d3560f1869..b3bb7ef97bc85 100644 --- a/arch/arm64/kernel/asm-offsets.c +++ b/arch/arm64/kernel/asm-offsets.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -148,14 +147,11 @@ int main(void) DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2)); DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id)); DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state)); + BLANK(); DEFINE(HIBERN_PBE_ORIG, offsetof(struct pbe, orig_address)); DEFINE(HIBERN_PBE_ADDR, offsetof(struct pbe, address)); DEFINE(HIBERN_PBE_NEXT, offsetof(struct pbe, next)); DEFINE(ARM64_FTR_SYSVAL, offsetof(struct arm64_ftr_reg, sys_val)); - BLANK(); -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 - DEFINE(TRAMP_VALIAS, TRAMP_VALIAS); -#endif return 0; } diff --git a/arch/arm64/kernel/bootinfo.c b/arch/arm64/kernel/bootinfo.c new file mode 100644 index 0000000000000..d63b6bed535db --- /dev/null +++ b/arch/arm64/kernel/bootinfo.c @@ -0,0 +1,270 @@ +/* + * bootinfo.c + * + * Copyright (C) 2011-2018 XiaoMi, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PMIC_NUM (16) +static int pmic_v[PMIC_NUM]; +static const char * const poweroff_reasons[POFF_REASON_MAX] = { + [POFF_REASON_EVENT_SOFT] = "soft", + [POFF_REASON_EVENT_PS_HOLD] = "ps_hold", + [POFF_REASON_EVENT_PMIC_WD] = "pmic_wd", + [POFF_REASON_EVENT_GP1_KPD1] = "keypad_reset1", + [POFF_REASON_EVENT_GP2_KPD2] = "keypad_reset2", + [POFF_REASON_EVENT_KPDPWR_AND_RESIN] = "kpdpwr_resin", + [POFF_REASON_EVENT_RESIN_N] = "resin_n", + [POFF_REASON_EVENT_KPDPWR_N] = "kpdpwr_n", + [POFF_REASON_EVENT_RESEVER1] = "resever1", + [POFF_REASON_EVENT_RESEVER2] = "resever2", + [POFF_REASON_EVENT_RESEVER3] = "resever3", + [POFF_REASON_EVENT_CHARGER] = "charger", + [POFF_REASON_EVENT_TFT] = "tft", + [POFF_REASON_EVENT_UVLO] = "uvlo", + [POFF_REASON_EVENT_OTST3] = "otst3", + [POFF_REASON_EVENT_STAGE3] = "stage3", + [POFF_REASON_EVENT_GP_FAULT0] = "gp_fault0", + [POFF_REASON_EVENT_GP_FAULT1] = "gp_fault1", + [POFF_REASON_EVENT_GP_FAULT2] = "gp_fault2", + [POFF_REASON_EVENT_GP_FAULT3] = "gp_fault3", + [POFF_REASON_EVENT_MBG_FAULT] = "mbg_fault", + [POFF_REASON_EVENT_OVLO] = "ovlo", + [POFF_REASON_EVENT_GEN2_UVLO] = "gen2_uvlo", + [POFF_REASON_EVENT_AVDD_RB] = "avdd_rb", + [POFF_REASON_EVENT_RESEVER4] = "resever4", + [POFF_REASON_EVENT_RESEVER5] = "resever5", + [POFF_REASON_EVENT_RESEVER6] = "resever6", + [POFF_REASON_EVENT_FAULT_FAULT_N] = "fault_n", + [POFF_REASON_EVENT_FAULT_PBS_WATCHDOG_TO] = "fault_pbs_watchdog", + [POFF_REASON_EVENT_FAULT_PBS_NACK] = "fault_pbs_nack", + [POFF_REASON_EVENT_FAULT_RESTART_PON] = "fault_restart_pon", + [POFF_REASON_EVENT_GEN2_OTST3] = "otst3", + [POFF_REASON_EVENT_RESEVER7] = "resever7", + [POFF_REASON_EVENT_RESEVER8] = "resever8", + [POFF_REASON_EVENT_RESEVER9] = "resever9", + [POFF_REASON_EVENT_RESEVER10] = "resever10", + [POFF_REASON_EVENT_S3_RESET_FAULT_N] = "s3_reset_fault_n", + [POFF_REASON_EVENT_S3_RESET_PBS_WATCHDOG_TO] = "s3_reset_pbs_watchdog", + [POFF_REASON_EVENT_S3_RESET_PBS_NACK] = "s3_reset_pbs_nack", + [POFF_REASON_EVENT_S3_RESET_KPDPWR_ANDOR_RESIN] = "s3_reset_kpdpwr_andor_resin", +}; + +static const char * const powerup_reasons[PU_REASON_MAX] = { + [PU_REASON_EVENT_KPD] = "keypad", + [PU_REASON_EVENT_RTC] = "rtc", + [PU_REASON_EVENT_CABLE] = "cable", + [PU_REASON_EVENT_SMPL] = "smpl", + [PU_REASON_EVENT_PON1] = "pon1", + [PU_REASON_EVENT_USB_CHG] = "usb_chg", + [PU_REASON_EVENT_DC_CHG] = "dc_chg", + [PU_REASON_EVENT_HWRST] = "hw_reset", + [PU_REASON_EVENT_LPK] = "long_power_key", +}; + +static const char * const reset_reasons[RS_REASON_MAX] = { + [RS_REASON_EVENT_WDOG] = "wdog", + [RS_REASON_EVENT_KPANIC] = "kpanic", + [RS_REASON_EVENT_NORMAL] = "reboot", + [RS_REASON_EVENT_OTHER] = "other", +}; + +static struct kobject *bootinfo_kobj; +static powerup_reason_t powerup_reason; + +#define bootinfo_attr(_name) \ +static struct kobj_attribute _name##_attr = { \ + .attr = { \ + .name = __stringify(_name), \ + .mode = 0644, \ + }, \ + .show = _name##_show, \ + .store = NULL, \ +} + +#define bootinfo_func_init(type, name, initval) \ +static type name = (initval); \ +type get_##name(void) \ +{ \ + return name; \ +} \ +void set_##name(type __##name) \ +{ \ + name = __##name; \ +} + +int is_abnormal_powerup(void) +{ + u32 pu_reason = get_powerup_reason(); + + return (pu_reason & (RESTART_EVENT_KPANIC | RESTART_EVENT_WDOG)) | + (pu_reason & BIT(PU_REASON_EVENT_HWRST) & RESTART_EVENT_OTHER); +} + +static ssize_t powerup_reason_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + char *s = buf; + u32 pu_reason; + int pu_reason_index = PU_REASON_MAX; + u32 reset_reason; + int reset_reason_index = RS_REASON_MAX; + + pu_reason = get_powerup_reason(); + if (((pu_reason & BIT(PU_REASON_EVENT_HWRST)) + && qpnp_pon_is_ps_hold_reset()) || + (pu_reason & BIT(PU_REASON_EVENT_WARMRST))) { + reset_reason = pu_reason >> 16; + reset_reason_index = find_first_bit((unsigned long *)&reset_reason, + sizeof(reset_reason)*BITS_PER_BYTE); + if (reset_reason_index < RS_REASON_MAX && reset_reason_index >= 0) { + s += snprintf(s, strlen(reset_reasons[reset_reason_index]) + 2, + "%s\n", reset_reasons[reset_reason_index]); + pr_debug("%s: rs_reason [0x%x], first non-zero bit %d\n", + __func__, reset_reason, reset_reason_index); + goto out; + }; + } + if (qpnp_pon_is_lpk() && + (pu_reason & BIT(PU_REASON_EVENT_HWRST))) + pu_reason_index = PU_REASON_EVENT_LPK; + else if (pu_reason & BIT(PU_REASON_EVENT_HWRST)) + pu_reason_index = PU_REASON_EVENT_HWRST; + else if (pu_reason & BIT(PU_REASON_EVENT_SMPL)) + pu_reason_index = PU_REASON_EVENT_SMPL; + else if (pu_reason & BIT(PU_REASON_EVENT_RTC)) + pu_reason_index = PU_REASON_EVENT_RTC; + else if (pu_reason & BIT(PU_REASON_EVENT_USB_CHG)) + pu_reason_index = PU_REASON_EVENT_USB_CHG; + else if (pu_reason & BIT(PU_REASON_EVENT_DC_CHG)) + pu_reason_index = PU_REASON_EVENT_DC_CHG; + else if (pu_reason & BIT(PU_REASON_EVENT_KPD)) + pu_reason_index = PU_REASON_EVENT_KPD; + else if (pu_reason & BIT(PU_REASON_EVENT_PON1)) + pu_reason_index = PU_REASON_EVENT_PON1; + if (pu_reason_index < PU_REASON_MAX && pu_reason_index >= 0) { + s += snprintf(s, strlen(powerup_reasons[pu_reason_index]) + 2, + "%s\n", powerup_reasons[pu_reason_index]); + pr_debug("%s: pu_reason [0x%x] index %d\n", + __func__, pu_reason, pu_reason_index); + goto out; + } + s += snprintf(s, 15, "unknown reboot\n"); +out: + return (s - buf); +} + +static ssize_t powerup_reason_details_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + u32 pu_reason; + + pu_reason = get_powerup_reason(); + + return snprintf(buf, 11, "0x%x\n", pu_reason); +} + +void set_poweroff_reason(int pmicv) +{ + int i = 0; + + while (i < PMIC_NUM) { + if (pmic_v[i] != -1) + i++; + else { + pmic_v[i] = pmicv; + break; + } + } +} + +static ssize_t poweroff_reason_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + int i = 0; + int l = 0; + int v = pmic_v[0]; + + if (v == -1) + return snprintf(buf, 10, " unknown \n"); + + while ((i < PMIC_NUM) && (pmic_v[i] != -1)) { + v = pmic_v[i]; + i++; + if (v >= 0 && v < POFF_REASON_MAX) + l += snprintf(buf + l, + (strlen(poweroff_reasons[v]) + 10), + " PNo.%d-%s ", i - 1, poweroff_reasons[v]); + else + l += snprintf(buf + l, 17, " PNo.%d-%s ", i - 1, "unknown"); + } + l += snprintf(buf + l, 2, "\n"); + + return l; +} + +bootinfo_attr(poweroff_reason); +bootinfo_attr(powerup_reason); +bootinfo_attr(powerup_reason_details); +bootinfo_func_init(u32, powerup_reason, 0); + +static struct attribute *g[] = { + &poweroff_reason_attr.attr, + &powerup_reason_attr.attr, + &powerup_reason_details_attr.attr, + NULL, +}; + +static struct attribute_group attr_group = { + .attrs = g, +}; + +static int __init bootinfo_init(void) +{ + int ret = -ENOMEM; + + bootinfo_kobj = kobject_create_and_add("bootinfo", NULL); + if (bootinfo_kobj == NULL) { + pr_err("bootinfo_init: subsystem_register failed\n"); + goto fail; + } + + memset(pmic_v, -1, sizeof(pmic_v)); + ret = sysfs_create_group(bootinfo_kobj, &attr_group); + if (ret) { + pr_err("bootinfo_init: subsystem_register failed\n"); + goto sys_fail; + } + + return ret; + +sys_fail: + kobject_del(bootinfo_kobj); +fail: + return ret; + +} + +static void __exit bootinfo_exit(void) +{ + if (bootinfo_kobj) { + sysfs_remove_group(bootinfo_kobj, &attr_group); + kobject_del(bootinfo_kobj); + } +} + +core_initcall(bootinfo_init); +module_exit(bootinfo_exit); diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S deleted file mode 100644 index dec95bd82e319..0000000000000 --- a/arch/arm64/kernel/bpi.S +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Contains CPU specific branch predictor invalidation sequences - * - * Copyright (C) 2018 ARM Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -.macro ventry target - .rept 31 - nop - .endr - b \target -.endm - -.macro vectors target - ventry \target + 0x000 - ventry \target + 0x080 - ventry \target + 0x100 - ventry \target + 0x180 - - ventry \target + 0x200 - ventry \target + 0x280 - ventry \target + 0x300 - ventry \target + 0x380 - - ventry \target + 0x400 - ventry \target + 0x480 - ventry \target + 0x500 - ventry \target + 0x580 - - ventry \target + 0x600 - ventry \target + 0x680 - ventry \target + 0x700 - ventry \target + 0x780 -.endm - - .align 11 -ENTRY(__bp_harden_hyp_vecs_start) - .rept 4 - vectors __kvm_hyp_vector - .endr -ENTRY(__bp_harden_hyp_vecs_end) -ENTRY(__psci_hyp_bp_inval_start) - sub sp, sp, #(8 * 18) - stp x16, x17, [sp, #(16 * 0)] - stp x14, x15, [sp, #(16 * 1)] - stp x12, x13, [sp, #(16 * 2)] - stp x10, x11, [sp, #(16 * 3)] - stp x8, x9, [sp, #(16 * 4)] - stp x6, x7, [sp, #(16 * 5)] - stp x4, x5, [sp, #(16 * 6)] - stp x2, x3, [sp, #(16 * 7)] - stp x0, x1, [sp, #(16 * 8)] - mov x0, #0x84000000 - smc #0 - ldp x16, x17, [sp, #(16 * 0)] - ldp x14, x15, [sp, #(16 * 1)] - ldp x12, x13, [sp, #(16 * 2)] - ldp x10, x11, [sp, #(16 * 3)] - ldp x8, x9, [sp, #(16 * 4)] - ldp x6, x7, [sp, #(16 * 5)] - ldp x4, x5, [sp, #(16 * 6)] - ldp x2, x3, [sp, #(16 * 7)] - ldp x0, x1, [sp, #(16 * 8)] - add sp, sp, #(8 * 18) -ENTRY(__psci_hyp_bp_inval_end) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 653359ba55bfe..b75e917aac464 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -46,100 +46,6 @@ static int cpu_enable_trap_ctr_access(void *__unused) return 0; } -#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR -#include -#include - -DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); - -#ifdef CONFIG_KVM -extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; - -static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, - const char *hyp_vecs_end) -{ - void *dst = lm_alias(__bp_harden_hyp_vecs_start + slot * SZ_2K); - int i; - - for (i = 0; i < SZ_2K; i += 0x80) - memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start); - - flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K); -} - -static void __install_bp_hardening_cb(bp_hardening_cb_t fn, - const char *hyp_vecs_start, - const char *hyp_vecs_end) -{ - static int last_slot = -1; - static DEFINE_SPINLOCK(bp_lock); - int cpu, slot = -1; - - spin_lock(&bp_lock); - for_each_possible_cpu(cpu) { - if (per_cpu(bp_hardening_data.fn, cpu) == fn) { - slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu); - break; - } - } - - if (slot == -1) { - last_slot++; - BUG_ON(((__bp_harden_hyp_vecs_end - __bp_harden_hyp_vecs_start) - / SZ_2K) <= last_slot); - slot = last_slot; - __copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end); - } - - __this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot); - __this_cpu_write(bp_hardening_data.fn, fn); - spin_unlock(&bp_lock); -} -#else -#define __psci_hyp_bp_inval_start NULL -#define __psci_hyp_bp_inval_end NULL - -static void __install_bp_hardening_cb(bp_hardening_cb_t fn, - const char *hyp_vecs_start, - const char *hyp_vecs_end) -{ - __this_cpu_write(bp_hardening_data.fn, fn); -} -#endif /* CONFIG_KVM */ - -static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry, - bp_hardening_cb_t fn, - const char *hyp_vecs_start, - const char *hyp_vecs_end) -{ - u64 pfr0; - - if (!entry->matches(entry, SCOPE_LOCAL_CPU)) - return; - - pfr0 = read_cpuid(ID_AA64PFR0_EL1); - if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT)) - return; - - __install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end); -} - -#include - -static int enable_psci_bp_hardening(void *data) -{ - const struct arm64_cpu_capabilities *entry = data; - - if (psci_ops.get_version) - install_bp_hardening_cb(entry, - (bp_hardening_cb_t)psci_ops.get_version, - __psci_hyp_bp_inval_start, - __psci_hyp_bp_inval_end); - - return 0; -} -#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ - #define MIDR_RANGE(model, min, max) \ .def_scope = SCOPE_LOCAL_CPU, \ .matches = is_affected_midr_range, \ @@ -147,13 +53,6 @@ static int enable_psci_bp_hardening(void *data) .midr_range_min = min, \ .midr_range_max = max -#define MIDR_ALL_VERSIONS(model) \ - .def_scope = SCOPE_LOCAL_CPU, \ - .matches = is_affected_midr_range, \ - .midr_model = model, \ - .midr_range_min = 0, \ - .midr_range_max = (MIDR_VARIANT_MASK | MIDR_REVISION_MASK) - const struct arm64_cpu_capabilities arm64_errata[] = { #if defined(CONFIG_ARM64_ERRATUM_826319) || \ defined(CONFIG_ARM64_ERRATUM_827319) || \ @@ -231,33 +130,6 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .def_scope = SCOPE_LOCAL_CPU, .enable = cpu_enable_trap_ctr_access, }, -#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR - { - .capability = ARM64_HARDEN_BRANCH_PREDICTOR, - MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), - .enable = enable_psci_bp_hardening, - }, - { - .capability = ARM64_HARDEN_BRANCH_PREDICTOR, - MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), - .enable = enable_psci_bp_hardening, - }, - { - .capability = ARM64_HARDEN_BRANCH_PREDICTOR, - MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), - .enable = enable_psci_bp_hardening, - }, - { - .capability = ARM64_HARDEN_BRANCH_PREDICTOR, - MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), - .enable = enable_psci_bp_hardening, - }, - { - .capability = ARM64_HARDEN_BRANCH_PREDICTOR, - MIDR_ALL_VERSIONS(MIDR_KRYO3G), - .enable = enable_psci_bp_hardening, - }, -#endif { } }; diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 80ff3df5f667f..0127e1bb5a7c4 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -100,7 +100,6 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0), S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), S_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), - ARM64_FTR_BITS(FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), /* Linux doesn't care about the EL3 */ ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64PFR0_EL3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0), @@ -749,44 +748,6 @@ static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry, return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode(); } -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 -static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ - -static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, - int __unused) -{ - u64 pfr0 = read_system_reg(SYS_ID_AA64PFR0_EL1); - - /* Forced on command line? */ - if (__kpti_forced) { - pr_info_once("kernel page table isolation forced %s by command line option\n", - __kpti_forced > 0 ? "ON" : "OFF"); - return __kpti_forced > 0; - } - - /* Useful for KASLR robustness */ - if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) - return true; - - /* Defer to CPU feature registers */ - return !cpuid_feature_extract_unsigned_field(pfr0, - ID_AA64PFR0_CSV3_SHIFT); -} - -static int __init parse_kpti(char *str) -{ - bool enabled; - int ret = strtobool(str, &enabled); - - if (ret) - return ret; - - __kpti_forced = enabled ? 1 : -1; - return 0; -} -__setup("kpti=", parse_kpti); -#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ - static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "GIC system register CPU interface", @@ -870,14 +831,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .def_scope = SCOPE_SYSTEM, .matches = hyp_offset_low, }, -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 - { - .desc = "Kernel page table isolation (KPTI)", - .capability = ARM64_UNMAP_KERNEL_AT_EL0, - .def_scope = SCOPE_SYSTEM, - .matches = unmap_kernel_at_el0, - }, -#endif {}, }; @@ -998,7 +951,7 @@ void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) * uses an IPI, giving us a PSTATE that disappears when * we return. */ - stop_machine(caps->enable, (void *)caps, cpu_online_mask); + stop_machine(caps->enable, NULL, cpu_online_mask); } /* @@ -1054,7 +1007,7 @@ verify_local_cpu_features(const struct arm64_cpu_capabilities *caps) cpu_die_early(); } if (caps->enable) - caps->enable((void *)caps); + caps->enable(NULL); } } diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 80305830e6eac..718c4c82820e6 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include @@ -71,31 +70,8 @@ #define BAD_FIQ 2 #define BAD_ERROR 3 - .macro kernel_ventry, el, label, regsize = 64 - .align 7 -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 -alternative_if ARM64_UNMAP_KERNEL_AT_EL0 - .if \el == 0 - .if \regsize == 64 - mrs x30, tpidrro_el0 - msr tpidrro_el0, xzr - .else - mov x30, xzr - .endif - .endif -alternative_else_nop_endif -#endif - - sub sp, sp, #S_FRAME_SIZE - b el\()\el\()_\label - .endm - - .macro tramp_alias, dst, sym - mov_q \dst, TRAMP_VALIAS - add \dst, \dst, #(\sym - .entry.tramp.text) - .endm - .macro kernel_entry, el, regsize = 64 + sub sp, sp, #S_FRAME_SIZE .if \regsize == 32 mov w0, w0 // zero upper 32 bits of x0 .endif @@ -150,8 +126,8 @@ alternative_if ARM64_HAS_PAN alternative_else_nop_endif .if \el != 0 - mrs x21, ttbr1_el1 - tst x21, #TTBR_ASID_MASK // Check for the reserved ASID + mrs x21, ttbr0_el1 + tst x21, #0xffff << 48 // Check for the reserved ASID orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR b.eq 1f // TTBR0 access already disabled and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR @@ -214,7 +190,7 @@ alternative_else_nop_endif tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set .endif - __uaccess_ttbr0_enable x0, x1 + __uaccess_ttbr0_enable x0 .if \el == 0 /* @@ -223,7 +199,7 @@ alternative_else_nop_endif * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache * corruption). */ - bl post_ttbr_update_workaround + post_ttbr0_update_workaround .endif 1: .if \el != 0 @@ -235,20 +211,18 @@ alternative_else_nop_endif .if \el == 0 ldr x23, [sp, #S_SP] // load return stack pointer msr sp_el0, x23 - tst x22, #PSR_MODE32_BIT // native task? - b.eq 3f - #ifdef CONFIG_ARM64_ERRATUM_845719 alternative_if ARM64_WORKAROUND_845719 + tbz x22, #4, 1f #ifdef CONFIG_PID_IN_CONTEXTIDR mrs x29, contextidr_el1 msr contextidr_el1, x29 #else msr contextidr_el1, xzr #endif +1: alternative_else_nop_endif #endif -3: .endif msr elr_el1, x21 // set up the return data @@ -270,21 +244,7 @@ alternative_else_nop_endif ldp x28, x29, [sp, #16 * 14] ldr lr, [sp, #S_LR] add sp, sp, #S_FRAME_SIZE // restore sp - - .if \el == 0 -alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0 -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 - bne 4f - msr far_el1, x30 - tramp_alias x30, tramp_exit_native - br x30 -4: - tramp_alias x30, tramp_exit_compat - br x30 -#endif - .else - eret - .endif + eret // return to kernel .endm .macro irq_stack_entry @@ -356,31 +316,31 @@ tsk .req x28 // current thread_info .align 11 ENTRY(vectors) - kernel_ventry 1, sync_invalid // Synchronous EL1t - kernel_ventry 1, irq_invalid // IRQ EL1t - kernel_ventry 1, fiq_invalid // FIQ EL1t - kernel_ventry 1, error_invalid // Error EL1t + ventry el1_sync_invalid // Synchronous EL1t + ventry el1_irq_invalid // IRQ EL1t + ventry el1_fiq_invalid // FIQ EL1t + ventry el1_error_invalid // Error EL1t - kernel_ventry 1, sync // Synchronous EL1h - kernel_ventry 1, irq // IRQ EL1h - kernel_ventry 1, fiq_invalid // FIQ EL1h - kernel_ventry 1, error_invalid // Error EL1h + ventry el1_sync // Synchronous EL1h + ventry el1_irq // IRQ EL1h + ventry el1_fiq_invalid // FIQ EL1h + ventry el1_error_invalid // Error EL1h - kernel_ventry 0, sync // Synchronous 64-bit EL0 - kernel_ventry 0, irq // IRQ 64-bit EL0 - kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0 - kernel_ventry 0, error_invalid // Error 64-bit EL0 + ventry el0_sync // Synchronous 64-bit EL0 + ventry el0_irq // IRQ 64-bit EL0 + ventry el0_fiq_invalid // FIQ 64-bit EL0 + ventry el0_error_invalid // Error 64-bit EL0 #ifdef CONFIG_COMPAT - kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0 - kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0 - kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0 - kernel_ventry 0, error_invalid_compat, 32 // Error 32-bit EL0 + ventry el0_sync_compat // Synchronous 32-bit EL0 + ventry el0_irq_compat // IRQ 32-bit EL0 + ventry el0_fiq_invalid_compat // FIQ 32-bit EL0 + ventry el0_error_invalid_compat // Error 32-bit EL0 #else - kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0 - kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0 - kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0 - kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0 + ventry el0_sync_invalid // Synchronous 32-bit EL0 + ventry el0_irq_invalid // IRQ 32-bit EL0 + ventry el0_fiq_invalid // FIQ 32-bit EL0 + ventry el0_error_invalid // Error 32-bit EL0 #endif END(vectors) @@ -648,14 +608,11 @@ el0_ia: mrs x26, far_el1 // enable interrupts before calling the main handler enable_dbg_and_irq -#ifdef CONFIG_TRACE_IRQFLAGS - bl trace_hardirqs_off -#endif ct_user_exit mov x0, x26 mov x1, x25 mov x2, sp - bl do_el0_ia_bp_hardening + bl do_mem_abort b ret_to_user el0_fpsimd_acc: /* @@ -902,119 +859,6 @@ __ni_sys_trace: .popsection // .entry.text -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 -/* - * Exception vectors trampoline. - */ - .pushsection ".entry.tramp.text", "ax" - - .macro tramp_map_kernel, tmp - mrs \tmp, ttbr1_el1 - sub \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) - bic \tmp, \tmp, #USER_ASID_FLAG - msr ttbr1_el1, \tmp -#ifdef CONFIG_ARCH_MSM8996 - /* ASID already in \tmp[63:48] */ - movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) - movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) - /* 2MB boundary containing the vectors, so we nobble the walk cache */ - movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) - isb - tlbi vae1, \tmp - dsb nsh -#endif /* CONFIG_ARCH_MSM8996 */ - .endm - - .macro tramp_unmap_kernel, tmp - mrs \tmp, ttbr1_el1 - add \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) - orr \tmp, \tmp, #USER_ASID_FLAG - msr ttbr1_el1, \tmp - /* - * We avoid running the post_ttbr_update_workaround here because the - * user and kernel ASIDs don't have conflicting mappings, so any - * "blessing" as described in: - * - * http://lkml.kernel.org/r/56BB848A.6060603@caviumnetworks.com - * - * will not hurt correctness. Whilst this may partially defeat the - * point of using split ASIDs in the first place, it avoids - * the hit of invalidating the entire I-cache on every return to - * userspace. - */ - .endm - - .macro tramp_ventry, regsize = 64 - .align 7 -1: - .if \regsize == 64 - msr tpidrro_el0, x30 // Restored in kernel_ventry - .endif - bl 2f - b . -2: - tramp_map_kernel x30 -#ifdef CONFIG_RANDOMIZE_BASE - adr x30, tramp_vectors + PAGE_SIZE -#ifndef CONFIG_ARCH_MSM8996 - isb -#endif - ldr x30, [x30] -#else - ldr x30, =vectors -#endif - prfm plil1strm, [x30, #(1b - tramp_vectors)] - msr vbar_el1, x30 - add x30, x30, #(1b - tramp_vectors) - isb - ret - .endm - - .macro tramp_exit, regsize = 64 - adr x30, tramp_vectors - msr vbar_el1, x30 - tramp_unmap_kernel x30 - .if \regsize == 64 - mrs x30, far_el1 - .endif - eret - .endm - - .align 11 -ENTRY(tramp_vectors) - .space 0x400 - - tramp_ventry - tramp_ventry - tramp_ventry - tramp_ventry - - tramp_ventry 32 - tramp_ventry 32 - tramp_ventry 32 - tramp_ventry 32 -END(tramp_vectors) - -ENTRY(tramp_exit_native) - tramp_exit -END(tramp_exit_native) - -ENTRY(tramp_exit_compat) - tramp_exit 32 -END(tramp_exit_compat) - - .ltorg - .popsection // .entry.tramp.text -#ifdef CONFIG_RANDOMIZE_BASE - .pushsection ".rodata", "a" - .align PAGE_SHIFT - .globl __entry_tramp_data_start -__entry_tramp_data_start: - .quad vectors - .popsection // .rodata -#endif /* CONFIG_RANDOMIZE_BASE */ -#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ - /* * Special system call wrappers. */ diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index e74ec9cbbd818..4172ec02718d3 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -4,6 +4,7 @@ * Original Copyright (C) 1995 Linus Torvalds * Copyright (C) 1996-2000 Russell King - Converted to ARM. * Copyright (C) 2012 ARM Ltd. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -366,17 +367,17 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start, static void tls_thread_switch(struct task_struct *next) { - unsigned long tpidr; + unsigned long tpidr, tpidrro; tpidr = read_sysreg(tpidr_el0); *task_user_tls(current) = tpidr; - if (is_compat_thread(task_thread_info(next))) - write_sysreg(next->thread.tp_value, tpidrro_el0); - else if (!arm64_kernel_unmapped_at_el0()) - write_sysreg(0, tpidrro_el0); + tpidr = *task_user_tls(next); + tpidrro = is_compat_thread(task_thread_info(next)) ? + next->thread.tp_value : 0; - write_sysreg(*task_user_tls(next), tpidr_el0); + write_sysreg(tpidr, tpidr_el0); + write_sysreg(tpidrro, tpidrro_el0); } /* Restore the UAO state depending on next's addr_limit */ diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index a58fb92f4dc29..8a2de2fb69f88 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -3,6 +3,7 @@ * * Copyright (C) 1995-2001 Russell King * Copyright (C) 2012 ARM Ltd. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -65,6 +66,15 @@ #include #include #include +#include + +#ifdef CONFIG_OF_FLATTREE +void __init early_init_dt_setup_pureason_arch(unsigned long pu_reason) +{ + set_powerup_reason(pu_reason); + pr_info("Powerup reason=0x%x\n", get_powerup_reason()); +} +#endif phys_addr_t __fdt_pointer __initdata; diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index cd538361b988b..19f3515230bd8 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -33,7 +33,6 @@ #include #include -#include #include #include #include @@ -541,25 +540,6 @@ static void ctr_read_handler(unsigned int esr, struct pt_regs *regs) regs->pc += 4; } -static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs) -{ - int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT; - - isb(); - if (rt != 31) - regs->regs[rt] = arch_counter_get_cntvct(); - regs->pc += 4; -} - -static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) -{ - int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT; - - if (rt != 31) - regs->regs[rt] = read_sysreg(cntfrq_el0); - regs->pc += 4; -} - struct sys64_hook { unsigned int esr_mask; unsigned int esr_val; @@ -578,18 +558,6 @@ static struct sys64_hook sys64_hooks[] = { .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ, .handler = ctr_read_handler, }, - { - /* Trap read access to CNTVCT_EL0 */ - .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, - .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT, - .handler = cntvct_read_handler, - }, - { - /* Trap read access to CNTFRQ_EL0 */ - .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, - .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ, - .handler = cntfrq_read_handler, - }, {}, }; diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S index 34d3ed64fe8ed..b8deffa9e1bf3 100644 --- a/arch/arm64/kernel/vmlinux.lds.S +++ b/arch/arm64/kernel/vmlinux.lds.S @@ -56,17 +56,6 @@ jiffies = jiffies_64; #define HIBERNATE_TEXT #endif -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 -#define TRAMP_TEXT \ - . = ALIGN(PAGE_SIZE); \ - VMLINUX_SYMBOL(__entry_tramp_text_start) = .; \ - *(.entry.tramp.text) \ - . = ALIGN(PAGE_SIZE); \ - VMLINUX_SYMBOL(__entry_tramp_text_end) = .; -#else -#define TRAMP_TEXT -#endif - /* * The size of the PE/COFF section that covers the kernel image, which * runs from stext to _edata, must be a round multiple of the PE/COFF @@ -139,7 +128,6 @@ SECTIONS HYPERVISOR_TEXT IDMAP_TEXT HIBERNATE_TEXT - TRAMP_TEXT *(.fixup) *(.gnu.warning) . = ALIGN(16); @@ -233,11 +221,6 @@ SECTIONS . += RESERVED_TTBR0_SIZE; #endif -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 - tramp_pg_dir = .; - . += PAGE_SIZE; -#endif - _end = .; STABS_DEBUG @@ -257,10 +240,7 @@ ASSERT(__idmap_text_end - (__idmap_text_start & ~(SZ_4K - 1)) <= SZ_4K, ASSERT(__hibernate_exit_text_end - (__hibernate_exit_text_start & ~(SZ_4K - 1)) <= SZ_4K, "Hibernate exit text too big or misaligned") #endif -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 -ASSERT((__entry_tramp_text_end - __entry_tramp_text_start) == PAGE_SIZE, - "Entry trampoline text too big") -#endif + /* * If padding is applied before .head.text, virt<->phys conversions will fail. */ diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index 3eab6ac18d7d3..0c848c18ca447 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -17,7 +17,6 @@ #include #include -#include #include #include @@ -51,7 +50,7 @@ static void __hyp_text __activate_traps_vhe(void) val &= ~CPACR_EL1_FPEN; write_sysreg(val, cpacr_el1); - write_sysreg(kvm_get_hyp_vector(), vbar_el1); + write_sysreg(__kvm_hyp_vector, vbar_el1); } static void __hyp_text __activate_traps_nvhe(void) @@ -309,18 +308,6 @@ int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu) if (exit_code == ARM_EXCEPTION_TRAP && !__populate_fault_info(vcpu)) goto again; - if (exit_code == ARM_EXCEPTION_TRAP && - (kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_HVC64 || - kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_HVC32) && - vcpu_get_reg(vcpu, 0) == PSCI_0_2_FN_PSCI_VERSION) { - u64 val = PSCI_RET_NOT_SUPPORTED; - if (test_bit(KVM_ARM_VCPU_PSCI_0_2, vcpu->arch.features)) - val = 2; - - vcpu_set_reg(vcpu, 0, val); - goto again; - } - if (static_branch_unlikely(&vgic_v2_cpuif_trap) && exit_code == ARM_EXCEPTION_TRAP) { bool valid; diff --git a/arch/arm64/lib/clear_user.S b/arch/arm64/lib/clear_user.S index dd65ca253eb4e..d7150e30438ae 100644 --- a/arch/arm64/lib/clear_user.S +++ b/arch/arm64/lib/clear_user.S @@ -30,7 +30,7 @@ * Alignment fixed up by hardware. */ ENTRY(__clear_user) - uaccess_enable_not_uao x2, x3, x4 + uaccess_enable_not_uao x2, x3 mov x2, x1 // save the size for fixup return subs x1, x1, #8 b.mi 2f diff --git a/arch/arm64/lib/copy_from_user.S b/arch/arm64/lib/copy_from_user.S index 7e7e687c17ac3..cfe13396085be 100644 --- a/arch/arm64/lib/copy_from_user.S +++ b/arch/arm64/lib/copy_from_user.S @@ -64,7 +64,7 @@ end .req x5 ENTRY(__arch_copy_from_user) - uaccess_enable_not_uao x3, x4, x5 + uaccess_enable_not_uao x3, x4 add end, x0, x2 #include "copy_template.S" uaccess_disable_not_uao x3 diff --git a/arch/arm64/lib/copy_in_user.S b/arch/arm64/lib/copy_in_user.S index 074d52fcd75ba..718b1c4e2f85a 100644 --- a/arch/arm64/lib/copy_in_user.S +++ b/arch/arm64/lib/copy_in_user.S @@ -65,7 +65,7 @@ end .req x5 ENTRY(__copy_in_user) - uaccess_enable_not_uao x3, x4, x5 + uaccess_enable_not_uao x3, x4 add end, x0, x2 #include "copy_template.S" uaccess_disable_not_uao x3 diff --git a/arch/arm64/lib/copy_to_user.S b/arch/arm64/lib/copy_to_user.S index 67118444cde0c..e99e31c9acac8 100644 --- a/arch/arm64/lib/copy_to_user.S +++ b/arch/arm64/lib/copy_to_user.S @@ -63,7 +63,7 @@ end .req x5 ENTRY(__arch_copy_to_user) - uaccess_enable_not_uao x3, x4, x5 + uaccess_enable_not_uao x3, x4 add end, x0, x2 #include "copy_template.S" uaccess_disable_not_uao x3 diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 9dd6d3282d2e3..97de0eb50e984 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -122,7 +122,7 @@ ENTRY(flush_icache_range) * - end - virtual end address of region */ ENTRY(__flush_cache_user_range) - uaccess_ttbr0_enable x2, x3, x4 + uaccess_ttbr0_enable x2, x3 dcache_line_size x2, x3 sub x3, x2, #1 bic x4, x0, x3 diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index da5add9d36d2a..f2f1b9143609d 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -3,6 +3,7 @@ * * Copyright (C) 2002-2003 Deep Blue Solutions Ltd, all rights reserved. * Copyright (C) 2012 ARM Ltd. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -39,16 +40,7 @@ static cpumask_t tlb_flush_pending; #define ASID_MASK (~GENMASK(asid_bits - 1, 0)) #define ASID_FIRST_VERSION (1UL << asid_bits) - -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 -#define NUM_USER_ASIDS (ASID_FIRST_VERSION >> 1) -#define asid2idx(asid) (((asid) & ~ASID_MASK) >> 1) -#define idx2asid(idx) (((idx) << 1) & ~ASID_MASK) -#else -#define NUM_USER_ASIDS (ASID_FIRST_VERSION) -#define asid2idx(asid) ((asid) & ~ASID_MASK) -#define idx2asid(idx) asid2idx(idx) -#endif +#define NUM_USER_ASIDS ASID_FIRST_VERSION /* Get the ASIDBits supported by the current CPU */ static u32 get_cpu_asid_bits(void) @@ -113,7 +105,7 @@ static void flush_context(unsigned int cpu) */ if (asid == 0) asid = per_cpu(reserved_asids, i); - __set_bit(asid2idx(asid), asid_map); + __set_bit(asid & ~ASID_MASK, asid_map); per_cpu(reserved_asids, i) = asid; } @@ -168,16 +160,16 @@ static u64 new_context(struct mm_struct *mm, unsigned int cpu) * We had a valid ASID in a previous life, so try to re-use * it if possible. */ - if (!__test_and_set_bit(asid2idx(asid), asid_map)) + asid &= ~ASID_MASK; + if (!__test_and_set_bit(asid, asid_map)) return newasid; } /* * Allocate a free ASID. If we can't find one, take a note of the - * currently active ASIDs and mark the TLBs as requiring flushes. We - * always count from ASID #2 (index 1), as we use ASID #0 when setting - * a reserved TTBR0 for the init_mm and we allocate ASIDs in even/odd - * pairs. + * currently active ASIDs and mark the TLBs as requiring flushes. + * We always count from ASID #1, as we use ASID #0 when setting a + * reserved TTBR0 for the init_mm. */ asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, cur_idx); if (asid != NUM_USER_ASIDS) @@ -194,7 +186,7 @@ static u64 new_context(struct mm_struct *mm, unsigned int cpu) set_asid: __set_bit(asid, asid_map); cur_idx = asid; - return idx2asid(asid) | generation; + return asid | generation; } void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) @@ -238,17 +230,6 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) cpu_switch_mm(mm->pgd, mm); } -/* Errata workaround post TTBRx_EL1 update. */ -asmlinkage void post_ttbr_update_workaround(void) -{ - asm(ALTERNATIVE("nop; nop; nop", - "ic iallu; dsb nsh; isb", - ARM64_WORKAROUND_CAVIUM_27456, - CONFIG_CAVIUM_ERRATUM_27456)); - - arm64_apply_bp_hardening(); -} - static int asids_init(void) { asid_bits = get_cpu_asid_bits(); diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 2b8950ed5e720..b5d88f88d9e2a 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -473,7 +473,7 @@ static int do_tlb_conf_fault(unsigned long addr, unsigned int esr, struct pt_regs *regs) { -#define SCM_TLB_CONFLICT_CMD 0x1F +#define SCM_TLB_CONFLICT_CMD 0x1B struct scm_desc desc = { .args[0] = addr, .arginfo = SCM_ARGS(1), @@ -618,22 +618,6 @@ asmlinkage void __exception do_mem_abort(unsigned long addr, unsigned int esr, arm64_notify_die("", regs, &info, esr); } -asmlinkage void __exception do_el0_ia_bp_hardening(unsigned long addr, - unsigned int esr, - struct pt_regs *regs) -{ - /* - * We've taken an instruction abort from userspace and not yet - * re-enabled IRQs. If the address is a kernel address, apply - * BP hardening prior to enabling IRQs and pre-emption. - */ - if (addr > TASK_SIZE) - arm64_apply_bp_hardening(); - - local_irq_enable(); - do_mem_abort(addr, esr, regs); -} - /* * Handle stack alignment exceptions. */ diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index c66fa93c907e4..41efd5eebb2f9 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -458,37 +458,6 @@ static void __init map_kernel_segment(pgd_t *pgd, void *va_start, void *va_end, vm_area_add_early(vma); } -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 -static int __init map_entry_trampoline(void) -{ - extern char __entry_tramp_text_start[]; - - pgprot_t prot = PAGE_KERNEL_EXEC; - phys_addr_t pa_start = __pa_symbol(__entry_tramp_text_start); - - /* The trampoline is always mapped and can therefore be global */ - pgprot_val(prot) &= ~PTE_NG; - - /* Map only the text into the trampoline page table */ - memset(tramp_pg_dir, 0, PGD_SIZE); - __create_pgd_mapping(tramp_pg_dir, pa_start, TRAMP_VALIAS, PAGE_SIZE, - prot, pgd_pgtable_alloc, 0); - - /* Map both the text and data into the kernel page table */ - __set_fixmap(FIX_ENTRY_TRAMP_TEXT, pa_start, prot); - if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) { - extern char __entry_tramp_data_start[]; - - __set_fixmap(FIX_ENTRY_TRAMP_DATA, - __pa_symbol(__entry_tramp_data_start), - PAGE_KERNEL_RO); - } - - return 0; -} -core_initcall(map_entry_trampoline); -#endif - /* * Create fine-grained mappings for the kernel. */ diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index fa20d134f2d1e..1f4d7b68dfa5e 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -4,6 +4,7 @@ * Copyright (C) 2001 Deep Blue Solutions Ltd. * Copyright (C) 2012 ARM Ltd. * Author: Catalin Marinas + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -184,14 +185,12 @@ ENDPROC(cpu_do_resume) * - pgd_phys - physical address of new TTB */ ENTRY(cpu_do_switch_mm) - mrs x2, ttbr1_el1 mmid x1, x1 // get mm->context.id - bfi x2, x1, #48, #16 // set the ASID - msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set) + bfi x0, x1, #48, #16 // set the ASID + msr ttbr0_el1, x0 // set TTBR0 isb - msr ttbr0_el1, x0 // now update TTBR0 - isb - b post_ttbr_update_workaround // Back to C code... + post_ttbr0_update_workaround + ret ENDPROC(cpu_do_switch_mm) .pushsection ".idmap.text", "ax" @@ -272,7 +271,7 @@ ENTRY(__cpu_setup) * both user and kernel. */ ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ - TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | TCR_A1 + TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 tcr_set_idmap_t0sz x10, x9 /* diff --git a/arch/arm64/xen/hypercall.S b/arch/arm64/xen/hypercall.S index f5422520cb01c..b41aff25426d6 100644 --- a/arch/arm64/xen/hypercall.S +++ b/arch/arm64/xen/hypercall.S @@ -100,7 +100,7 @@ ENTRY(privcmd_call) * need the explicit uaccess_enable/disable if the TTBR0 PAN emulation * is enabled (it implies that hardware UAO and PAN disabled). */ - uaccess_ttbr0_enable x6, x7, x8 + uaccess_ttbr0_enable x6, x7 hvc XEN_IMM /* diff --git a/block/blk-cgroup.c b/block/blk-cgroup.c index 8ba0af780e880..35648229f0e27 100644 --- a/block/blk-cgroup.c +++ b/block/blk-cgroup.c @@ -3,6 +3,7 @@ * * Based on ideas and code from CFQ, CFS and BFQ: * Copyright (C) 2003 Jens Axboe + * Copyright (C) 2018 XiaoMi, Inc. * * Copyright (C) 2008 Fabio Checconi * Paolo Valente @@ -185,8 +186,7 @@ static struct blkcg_gq *blkg_create(struct blkcg *blkcg, } wb_congested = wb_congested_get_create(&q->backing_dev_info, - blkcg->css.id, - GFP_NOWAIT | __GFP_NOWARN); + blkcg->css.id, GFP_NOWAIT); if (!wb_congested) { ret = -ENOMEM; goto err_put_css; @@ -194,7 +194,7 @@ static struct blkcg_gq *blkg_create(struct blkcg *blkcg, /* allocate */ if (!new_blkg) { - new_blkg = blkg_alloc(blkcg, q, GFP_NOWAIT | __GFP_NOWARN); + new_blkg = blkg_alloc(blkcg, q, GFP_NOWAIT); if (unlikely(!new_blkg)) { ret = -ENOMEM; goto err_put_congested; @@ -1023,7 +1023,7 @@ blkcg_css_alloc(struct cgroup_subsys_state *parent_css) } spin_lock_init(&blkcg->lock); - INIT_RADIX_TREE(&blkcg->blkg_tree, GFP_NOWAIT | __GFP_NOWARN); + INIT_RADIX_TREE(&blkcg->blkg_tree, GFP_NOWAIT); INIT_HLIST_HEAD(&blkcg->blkg_list); #ifdef CONFIG_CGROUP_WRITEBACK INIT_LIST_HEAD(&blkcg->cgwb_list); @@ -1241,7 +1241,7 @@ int blkcg_activate_policy(struct request_queue *q, if (blkg->pd[pol->plid]) continue; - pd = pol->pd_alloc_fn(GFP_NOWAIT | __GFP_NOWARN, q->node); + pd = pol->pd_alloc_fn(GFP_NOWAIT, q->node); if (!pd) swap(pd, pd_prealloc); if (!pd) { diff --git a/block/blk-core.c b/block/blk-core.c index 9fc567cde51c9..a4d48ff7f723c 100644 --- a/block/blk-core.c +++ b/block/blk-core.c @@ -323,7 +323,9 @@ inline void __blk_run_queue_uncond(struct request_queue *q) * can wait until all these request_fn calls have finished. */ q->request_fn_active++; + preempt_disable(); q->request_fn(q); + preempt_enable(); q->request_fn_active--; } EXPORT_SYMBOL_GPL(__blk_run_queue_uncond); diff --git a/block/cfq-iosched.c b/block/cfq-iosched.c index 6a901554ba50d..4ac4910afdb99 100644 --- a/block/cfq-iosched.c +++ b/block/cfq-iosched.c @@ -3868,8 +3868,7 @@ cfq_get_queue(struct cfq_data *cfqd, bool is_sync, struct cfq_io_cq *cic, goto out; } - cfqq = kmem_cache_alloc_node(cfq_pool, - GFP_NOWAIT | __GFP_ZERO | __GFP_NOWARN, + cfqq = kmem_cache_alloc_node(cfq_pool, GFP_NOWAIT | __GFP_ZERO, cfqd->queue->node); if (!cfqq) { cfqq = &cfqd->oom_cfqq; diff --git a/drivers/base/power/wakeup.c b/drivers/base/power/wakeup.c index b758633869657..84dc69162f03a 100644 --- a/drivers/base/power/wakeup.c +++ b/drivers/base/power/wakeup.c @@ -2,6 +2,7 @@ * drivers/base/power/wakeup.c - System wakeup events framework * * Copyright (c) 2010 Rafael J. Wysocki , Novell Inc. + * Copyright (C) 2018 XiaoMi, Inc. * * This file is released under the GPLv2. */ @@ -19,6 +20,7 @@ #include #include #include +#include #include "power.h" @@ -873,6 +875,7 @@ EXPORT_SYMBOL_GPL(pm_print_active_wakeup_sources); * since the old value was stored. Also return true if the current number of * wakeup events being processed is different from zero. */ +bool wakeup_irq_abort_suspend; bool pm_wakeup_pending(void) { unsigned long flags; @@ -899,6 +902,7 @@ bool pm_wakeup_pending(void) void pm_system_wakeup(void) { pm_abort_suspend = true; + wakeup_irq_abort_suspend = true; freeze_wake(); } EXPORT_SYMBOL_GPL(pm_system_wakeup); @@ -906,6 +910,7 @@ EXPORT_SYMBOL_GPL(pm_system_wakeup); void pm_wakeup_clear(void) { pm_abort_suspend = false; + wakeup_irq_abort_suspend = false; pm_wakeup_irq = 0; } @@ -925,6 +930,7 @@ void pm_system_irq_wakeup(unsigned int irq_number) pr_warn("%s: %d triggered %s\n", __func__, irq_number, name); + log_wakeup_reason(irq_number); } pm_wakeup_irq = irq_number; pm_system_wakeup(); diff --git a/drivers/base/syscore.c b/drivers/base/syscore.c index 96c34a95cc625..f1cb634b33d15 100644 --- a/drivers/base/syscore.c +++ b/drivers/base/syscore.c @@ -2,6 +2,7 @@ * syscore.c - Execution of system core operations. * * Copyright (C) 2011 Rafael J. Wysocki , Novell Inc. + * Copyright (C) 2018 XiaoMi, Inc. * * This file is released under the GPLv2. */ @@ -46,17 +47,25 @@ EXPORT_SYMBOL_GPL(unregister_syscore_ops); * * This function is executed with one CPU on-line and disabled interrupts. */ +extern bool wakeup_irq_abort_suspend; int syscore_suspend(void) { struct syscore_ops *ops; int ret = 0; + char suspend_abort[MAX_SUSPEND_ABORT_LEN]; trace_suspend_resume(TPS("syscore_suspend"), 0, true); pr_debug("Checking wakeup interrupts\n"); /* Return error code if there are any wakeup interrupts pending. */ - if (pm_wakeup_pending()) + if (pm_wakeup_pending()) { + if (wakeup_irq_abort_suspend == false) { + pm_get_active_wakeup_sources(suspend_abort, MAX_SUSPEND_ABORT_LEN); + log_suspend_abort_reason(suspend_abort); + } + pr_err("PM: Abort system core suspend, wakeup interrupt or wakeup source detected"); return -EBUSY; + } WARN_ONCE(!irqs_disabled(), "Interrupts enabled before system core suspend.\n"); diff --git a/drivers/block/zram/zram_drv.c b/drivers/block/zram/zram_drv.c index 9701cc27e95fa..a022b79dd8029 100644 --- a/drivers/block/zram/zram_drv.c +++ b/drivers/block/zram/zram_drv.c @@ -2,6 +2,7 @@ * Compressed RAM block device * * Copyright (C) 2008, 2009, 2010 Nitin Gupta + * Copyright (C) 2018 XiaoMi, Inc. * 2012, 2013 Minchan Kim * * This code is released using a dual license strategy: BSD/GPL @@ -49,6 +50,7 @@ static const char *default_compressor = "lzo"; /* Module params (documentation at end) */ static unsigned int num_devices = 1; +static struct zram **zram_devices; static inline void deprecated_attr_warn(const char *name) { @@ -400,6 +402,31 @@ static ssize_t compact_store(struct device *dev, return len; } +int zs_get_page_usage(unsigned long *total_pool_pages, + unsigned long *total_ori_pages) +{ + int i; + *total_pool_pages = *total_ori_pages = 0; + if (!zram_devices) + return 0; + for (i = 0; i < num_devices; i++) { + struct zram *zram = zram_devices[i]; + struct zram_meta *meta; + if (!zram) + return 0; + meta = zram->meta; + if (!down_read_trylock(&zram->init_lock)) + continue; + if (init_done(zram)) { + *total_pool_pages += zs_get_total_pages(meta->mem_pool); + *total_ori_pages += atomic64_read( + &zram->stats.pages_stored); + } + up_read(&zram->init_lock); + } + return 0; + } + static ssize_t io_stat_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1240,7 +1267,7 @@ static int zram_add(void) { struct zram *zram; struct request_queue *queue; - int ret, device_id; + int i, ret, device_id; zram = kzalloc(sizeof(struct zram), GFP_KERNEL); if (!zram) @@ -1323,6 +1350,13 @@ static int zram_add(void) strlcpy(zram->compressor, default_compressor, sizeof(zram->compressor)); zram->meta = NULL; + for (i = 0; i < num_devices; i++) { + if (!zram_devices[i]) { + zram_devices[i] = zram; + break; + } + } + pr_info("Added device: %s\n", zram->disk->disk_name); return device_id; @@ -1452,6 +1486,7 @@ static int zram_remove_cb(int id, void *ptr, void *data) static void destroy_devices(void) { + kfree(zram_devices); class_unregister(&zram_control_class); idr_for_each(&zram_index_idr, &zram_remove_cb, NULL); idr_destroy(&zram_index_idr); @@ -1462,6 +1497,10 @@ static int __init zram_init(void) { int ret; + zram_devices = kzalloc(num_devices * sizeof(struct zram *), GFP_KERNEL); + if (!zram_devices) + return -ENOMEM; + ret = class_register(&zram_control_class); if (ret) { pr_err("Unable to register zram-control class\n"); diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c index 11374819d4146..3058ce34da80d 100644 --- a/drivers/char/adsprpc.c +++ b/drivers/char/adsprpc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -311,8 +311,6 @@ struct fastrpc_file { struct dentry *debugfs_file; struct pm_qos_request pm_qos_req; int qos_request; - struct mutex map_mutex; - struct mutex fl_map_mutex; }; static struct fastrpc_apps gfa; @@ -419,7 +417,9 @@ static void fastrpc_mmap_add(struct fastrpc_mmap *map) } else { struct fastrpc_file *fl = map->fl; + spin_lock(&fl->hlock); hlist_add_head(&map->hn, &fl->maps); + spin_unlock(&fl->hlock); } } @@ -448,6 +448,7 @@ static int fastrpc_mmap_find(struct fastrpc_file *fl, int fd, } spin_unlock(&me->hlock); } else { + spin_lock(&fl->hlock); hlist_for_each_entry_safe(map, n, &fl->maps, hn) { if (va >= map->va && va + len <= map->va + map->len && @@ -458,6 +459,7 @@ static int fastrpc_mmap_find(struct fastrpc_file *fl, int fd, break; } } + spin_unlock(&fl->hlock); } if (match) { *ppmap = match; @@ -505,6 +507,7 @@ static int fastrpc_mmap_remove(struct fastrpc_file *fl, uintptr_t va, *ppmap = match; return 0; } + spin_lock(&fl->hlock); hlist_for_each_entry_safe(map, n, &fl->maps, hn) { if (map->raddr == va && map->raddr + map->len == va + len && @@ -514,6 +517,7 @@ static int fastrpc_mmap_remove(struct fastrpc_file *fl, uintptr_t va, break; } } + spin_unlock(&fl->hlock); if (match) { *ppmap = match; return 0; @@ -541,9 +545,11 @@ static void fastrpc_mmap_free(struct fastrpc_mmap *map, uint32_t flags) if (map->refs > 0) return; } else { + spin_lock(&fl->hlock); map->refs--; if (!map->refs) hlist_del_init(&map->hn); + spin_unlock(&fl->hlock); if (map->refs > 0 && !flags) return; } @@ -706,24 +712,13 @@ static int fastrpc_mmap_create(struct fastrpc_file *fl, int fd, goto bail; } map->phys = sg_dma_address(map->table->sgl); - if (sess->smmu.cb) { map->phys += ((uint64_t)sess->smmu.cb << 32); map->size = sg_dma_len(map->table->sgl); } else { map->size = buf_page_size(len); } - vmid = fl->apps->channel[fl->cid].vmid; - if (!sess->smmu.enabled && !vmid) { - VERIFY(err, map->phys >= me->range.addr && - map->phys + map->size <= - me->range.addr + me->range.size); - if (err) { - pr_err("adsprpc: mmap fail out of range\n"); - goto bail; - } - } if (vmid) { int srcVM[1] = {VMID_HLOS}; int destVM[2] = {VMID_HLOS, vmid}; @@ -1015,11 +1010,8 @@ static void context_free(struct smq_invoke_ctx *ctx) spin_lock(&ctx->fl->hlock); hlist_del_init(&ctx->hn); spin_unlock(&ctx->fl->hlock); - mutex_lock(&ctx->fl->fl_map_mutex); for (i = 0; i < nbufs; ++i) fastrpc_mmap_free(ctx->maps[i], 0); - - mutex_unlock(&ctx->fl->fl_map_mutex); fastrpc_buf_free(ctx->buf, 1); ctx->magic = 0; kfree(ctx); @@ -1147,26 +1139,20 @@ static int get_args(uint32_t kernel, struct smq_invoke_ctx *ctx) uintptr_t buf = (uintptr_t)lpra[i].buf.pv; size_t len = lpra[i].buf.len; - mutex_lock(&ctx->fl->fl_map_mutex); if (ctx->fds[i] && (ctx->fds[i] != -1)) fastrpc_mmap_create(ctx->fl, ctx->fds[i], ctx->attrs[i], buf, len, mflags, &ctx->maps[i]); - mutex_unlock(&ctx->fl->fl_map_mutex); ipage += 1; } handles = REMOTE_SCALARS_INHANDLES(sc) + REMOTE_SCALARS_OUTHANDLES(sc); - mutex_lock(&ctx->fl->fl_map_mutex); for (i = bufs; i < bufs + handles; i++) { VERIFY(err, !fastrpc_mmap_create(ctx->fl, ctx->fds[i], FASTRPC_ATTR_NOVA, 0, 0, 0, &ctx->maps[i])); - if (err) { - mutex_unlock(&ctx->fl->fl_map_mutex); + if (err) goto bail; - } ipage += 1; } - mutex_unlock(&ctx->fl->fl_map_mutex); metalen = copylen = (size_t)&ipage[0] + (sizeof(uint64_t) * M_FDLIST) + (sizeof(uint32_t) * M_CRCLIST); @@ -1375,13 +1361,10 @@ static int put_args(uint32_t kernel, struct smq_invoke_ctx *ctx, if (err) goto bail; } else { - mutex_lock(&ctx->fl->fl_map_mutex); fastrpc_mmap_free(ctx->maps[i], 0); - mutex_unlock(&ctx->fl->fl_map_mutex); ctx->maps[i] = NULL; } } - mutex_lock(&ctx->fl->fl_map_mutex); if (inbufs + outbufs + handles) { for (i = 0; i < M_FDLIST; i++) { if (!fdlist[i]) @@ -1391,7 +1374,6 @@ static int put_args(uint32_t kernel, struct smq_invoke_ctx *ctx, fastrpc_mmap_free(mmap, 0); } } - mutex_unlock(&ctx->fl->fl_map_mutex); if (ctx->crc && crclist && rpra) K_COPY_TO_USER(err, kernel, ctx->crc, crclist, M_CRCLIST*sizeof(uint32_t)); @@ -1686,10 +1668,8 @@ static int fastrpc_init_process(struct fastrpc_file *fl, if (err) goto bail; if (init->filelen) { - mutex_lock(&fl->fl_map_mutex); VERIFY(err, !fastrpc_mmap_create(fl, init->filefd, 0, init->file, init->filelen, mflags, &file)); - mutex_unlock(&fl->fl_map_mutex); if (err) goto bail; } @@ -1698,10 +1678,8 @@ static int fastrpc_init_process(struct fastrpc_file *fl, init->memlen)); if (err) goto bail; - mutex_lock(&fl->fl_map_mutex); VERIFY(err, !fastrpc_mmap_create(fl, init->memfd, 0, init->mem, init->memlen, mflags, &mem)); - mutex_unlock(&fl->fl_map_mutex); if (err) goto bail; inbuf.pageslen = 1; @@ -1773,11 +1751,9 @@ static int fastrpc_init_process(struct fastrpc_file *fl, inbuf.pageslen = 0; if (!me->staticpd_flags) { inbuf.pageslen = 1; - mutex_lock(&fl->fl_map_mutex); VERIFY(err, !fastrpc_mmap_create(fl, -1, 0, init->mem, init->memlen, ADSP_MMAP_REMOTE_HEAP_ADDR, &mem)); - mutex_unlock(&fl->fl_map_mutex); if (err) goto bail; phys = mem->phys; @@ -1830,15 +1806,10 @@ static int fastrpc_init_process(struct fastrpc_file *fl, if (mem->flags == ADSP_MMAP_REMOTE_HEAP_ADDR) hyp_assign_phys(mem->phys, (uint64_t)mem->size, destVM, 1, srcVM, hlosVMperm, 1); - mutex_lock(&fl->fl_map_mutex); fastrpc_mmap_free(mem, 0); - mutex_unlock(&fl->fl_map_mutex); } - if (file) { - mutex_lock(&fl->fl_map_mutex); + if (file) fastrpc_mmap_free(file, 0); - mutex_unlock(&fl->fl_map_mutex); - } return err; } @@ -2091,25 +2062,16 @@ static int fastrpc_internal_munmap(struct fastrpc_file *fl, int err = 0; struct fastrpc_mmap *map = NULL; - mutex_lock(&fl->map_mutex); - mutex_lock(&fl->fl_map_mutex); VERIFY(err, !fastrpc_mmap_remove(fl, ud->vaddrout, ud->size, &map)); - mutex_unlock(&fl->fl_map_mutex); if (err) goto bail; VERIFY(err, !fastrpc_munmap_on_dsp(fl, map)); if (err) goto bail; - mutex_lock(&fl->fl_map_mutex); fastrpc_mmap_free(map, 0); - mutex_unlock(&fl->fl_map_mutex); bail: - if (err && map) { - mutex_lock(&fl->fl_map_mutex); + if (err && map) fastrpc_mmap_add(map); - mutex_unlock(&fl->fl_map_mutex); - } - mutex_unlock(&fl->map_mutex); return err; } @@ -2121,18 +2083,16 @@ static int fastrpc_internal_munmap_fd(struct fastrpc_file *fl, VERIFY(err, (fl && ud)); if (err) goto bail; - mutex_lock(&fl->fl_map_mutex); + if (!fastrpc_mmap_find(fl, ud->fd, ud->va, ud->len, 0, 0, &map)) { pr_err("mapping not found to unamp %x va %llx %x\n", ud->fd, (unsigned long long)ud->va, (unsigned int)ud->len); err = -1; - mutex_unlock(&fl->fl_map_mutex); goto bail; } if (map) - fastrpc_mmap_free(map, 0); - mutex_unlock(&fl->fl_map_mutex); + fastrpc_mmap_free(map, 0); bail: return err; } @@ -2145,18 +2105,13 @@ static int fastrpc_internal_mmap(struct fastrpc_file *fl, struct fastrpc_mmap *map = NULL; int err = 0; - mutex_lock(&fl->map_mutex); - mutex_lock(&fl->fl_map_mutex); if (!fastrpc_mmap_find(fl, ud->fd, (uintptr_t)ud->vaddrin, - ud->size, ud->flags, 1, &map)) { - mutex_unlock(&fl->fl_map_mutex); - mutex_unlock(&fl->map_mutex); + ud->size, ud->flags, 1, &map)) return 0; - } + VERIFY(err, !fastrpc_mmap_create(fl, ud->fd, 0, (uintptr_t)ud->vaddrin, ud->size, ud->flags, &map)); - mutex_unlock(&fl->fl_map_mutex); if (err) goto bail; VERIFY(err, 0 == fastrpc_mmap_on_dsp(fl, ud->flags, map)); @@ -2164,12 +2119,8 @@ static int fastrpc_internal_mmap(struct fastrpc_file *fl, goto bail; ud->vaddrout = map->raddr; bail: - if (err && map) { - mutex_lock(&fl->fl_map_mutex); + if (err && map) fastrpc_mmap_free(map, 0); - mutex_unlock(&fl->fl_map_mutex); - } - mutex_unlock(&fl->map_mutex); return err; } @@ -2332,11 +2283,9 @@ static int fastrpc_file_free(struct fastrpc_file *fl) spin_unlock(&fl->hlock); fastrpc_context_list_dtor(fl); fastrpc_buf_list_free(fl); - mutex_lock(&fl->fl_map_mutex); hlist_for_each_entry_safe(map, n, &fl->maps, hn) { fastrpc_mmap_free(map, 1); } - mutex_unlock(&fl->fl_map_mutex); if (fl->ssrcount == fl->apps->channel[cid].ssrcount) kref_put_mutex(&fl->apps->channel[cid].kref, fastrpc_channel_close, &fl->apps->smd_mutex); @@ -2344,7 +2293,6 @@ static int fastrpc_file_free(struct fastrpc_file *fl) fastrpc_session_free(&fl->apps->channel[cid], fl->sctx); if (fl->secsctx) fastrpc_session_free(&fl->apps->channel[cid], fl->secsctx); - mutex_destroy(&fl->fl_map_mutex); kfree(fl); return 0; } @@ -2358,7 +2306,6 @@ static int fastrpc_device_release(struct inode *inode, struct file *file) pm_qos_remove_request(&fl->pm_qos_req); if (fl->debugfs_file != NULL) debugfs_remove(fl->debugfs_file); - mutex_destroy(&fl->map_mutex); fastrpc_file_free(fl); file->private_data = NULL; } @@ -2682,8 +2629,6 @@ static int fastrpc_device_open(struct inode *inode, struct file *filp) memset(&fl->perf, 0, sizeof(fl->perf)); fl->qos_request = 0; filp->private_data = fl; - mutex_init(&fl->map_mutex); - mutex_init(&fl->fl_map_mutex); spin_lock(&me->hlock); hlist_add_head(&fl->hn, &me->drivers); spin_unlock(&me->hlock); @@ -3108,8 +3053,6 @@ static int fastrpc_probe(struct platform_device *pdev) srcVM, 1, destVM, destVMperm, 4)); if (err) goto bail; - me->range.addr = range.addr; - me->range.size = range.size; } return 0; } diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 020e8addb15d5..0b1fde1d1a0b8 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -2360,7 +2360,7 @@ EXPORT_SYMBOL_GPL(clk_list_frequency); static struct dentry *rootdir; static int inited = 0; -static u32 debug_suspend; +static u32 debug_suspend = 1; static DEFINE_MUTEX(clk_debug_lock); static HLIST_HEAD(clk_debug_list); diff --git a/drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c b/drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c index 3f9fcd98815c2..b669c62b830b1 100644 --- a/drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c +++ b/drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c @@ -671,7 +671,7 @@ static int dsi_pll_10nm_lock_status(struct mdss_pll_resources *pll) ((status & BIT(0)) > 0), delay_us, timeout_us); - if (rc) + if (rc && !pll->handoff_resources) pr_err("DSI PLL(%d) lock failed, status=0x%08x\n", pll->index, status); @@ -908,7 +908,7 @@ static unsigned long vco_10nm_recalc_rate(struct clk_hw *hw, struct mdss_pll_resources *pll = vco->priv; int rc; u64 ref_clk = vco->ref_clk_rate; - u64 vco_rate; + u64 vco_rate = 0; u64 multiplier; u32 frac; u32 dec; @@ -938,8 +938,13 @@ static unsigned long vco_10nm_recalc_rate(struct clk_hw *hw, return 0; } - if (!dsi_pll_10nm_lock_status(pll)) - pll->handoff_resources = true; + pll->handoff_resources = true; + if (dsi_pll_10nm_lock_status(pll)) { + pr_debug("PLL not enabled\n"); + pll->handoff_resources = false; + goto end; + } + dec = MDSS_PLL_REG_R(pll->pll_base, PLL_DECIMAL_DIV_START_1); dec &= 0xFF; @@ -974,6 +979,7 @@ static unsigned long vco_10nm_recalc_rate(struct clk_hw *hw, (void)mdss_pll_resource_enable(pll, false); +end: return (unsigned long)vco_rate; } @@ -1639,7 +1645,7 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev, of_clk_src_onecell_get, clk_data); } if (!rc) { - pr_info("Registered DSI PLL ndx=%d, clocks successfully", ndx); + pr_info("Registered DSI PLL ndx=%d, clocks successfully\n", ndx); return rc; } diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 84b6efec91c2d..e2c6e43cf8ca3 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -315,14 +315,6 @@ config FSL_ERRATUM_A008585 value"). The workaround will only be active if the fsl,erratum-a008585 property is found in the timer node. -config ARM_ARCH_TIMER_VCT_ACCESS - bool "Support for ARM architected timer virtual counter access in userspace" - default !ARM64 - depends on ARM_ARCH_TIMER - help - This option enables support for reading the ARM architected timer's - virtual counter in userspace. - config ARM_GLOBAL_TIMER bool "Support for the ARM global timer" if COMPILE_TEST select CLKSRC_OF if OF diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 5aa9914d494ec..bb21adee98415 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -2,6 +2,7 @@ * linux/drivers/clocksource/arm_arch_timer.c * * Copyright (C) 2011 ARM Ltd. + * Copyright (C) 2018 XiaoMi, Inc. * All Rights Reserved * * This program is free software; you can redistribute it and/or modify @@ -48,8 +49,6 @@ #define CNTFRQ 0x10 #define CNTP_TVAL 0x28 #define CNTP_CTL 0x2c -#define CNTCVAL_LO 0x30 -#define CNTCVAL_HI 0x34 #define CNTV_TVAL 0x38 #define CNTV_CTL 0x3c @@ -443,18 +442,14 @@ static void arch_counter_set_user_access(void) { u32 cntkctl = arch_timer_get_cntkctl(); - /* Disable user access to the timers and the physical counter */ + /* Disable user access to the timers */ /* Also disable virtual event stream */ cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN | ARCH_TIMER_USR_VT_ACCESS_EN - | ARCH_TIMER_VIRT_EVT_EN - | ARCH_TIMER_USR_PCT_ACCESS_EN); + | ARCH_TIMER_VIRT_EVT_EN); - /* Enable user access to the virtual counter */ - if (IS_ENABLED(CONFIG_ARM_ARCH_TIMER_VCT_ACCESS)) - cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN; - else - cntkctl &= ~ARCH_TIMER_USR_VCT_ACCESS_EN; + /* Enable user access to the virtual and physical counters */ + cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN | ARCH_TIMER_USR_PCT_ACCESS_EN; arch_timer_set_cntkctl(cntkctl); } @@ -547,23 +542,6 @@ u32 arch_timer_get_rate(void) return arch_timer_rate; } -void arch_timer_mem_get_cval(u32 *lo, u32 *hi) -{ - u32 ctrl; - - *lo = *hi = ~0U; - - if (!arch_counter_base) - return; - - ctrl = readl_relaxed_no_log(arch_counter_base + CNTV_CTL); - - if (ctrl & ARCH_TIMER_CTRL_ENABLE) { - *lo = readl_relaxed_no_log(arch_counter_base + CNTCVAL_LO); - *hi = readl_relaxed_no_log(arch_counter_base + CNTCVAL_HI); - } -} - static u64 arch_counter_get_cntvct_mem(void) { u32 vct_lo, vct_hi, tmp_hi; diff --git a/drivers/cpufreq/cpu-boost.c b/drivers/cpufreq/cpu-boost.c index 6a4008c1c5269..c13c7aa02bafe 100644 --- a/drivers/cpufreq/cpu-boost.c +++ b/drivers/cpufreq/cpu-boost.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2013-2015,2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -27,21 +28,33 @@ struct cpu_sync { int cpu; unsigned int input_boost_min; unsigned int input_boost_freq; + unsigned int powerkey_input_boost_freq; +}; + +enum input_boost_type { + default_input_boost, + powerkey_input_boost }; static DEFINE_PER_CPU(struct cpu_sync, sync_info); static struct workqueue_struct *cpu_boost_wq; static struct work_struct input_boost_work; - +static struct work_struct powerkey_input_boost_work; static bool input_boost_enabled; static unsigned int input_boost_ms = 40; module_param(input_boost_ms, uint, 0644); +static unsigned int powerkey_input_boost_ms = 400; +module_param(powerkey_input_boost_ms, uint, 0644); + static unsigned int sched_boost_on_input; module_param(sched_boost_on_input, uint, 0644); +static bool sched_boost_on_powerkey_input = true; +module_param(sched_boost_on_powerkey_input, bool, 0644); + static bool sched_boost_active; static struct delayed_work input_boost_rem; @@ -54,6 +67,12 @@ static int set_input_boost_freq(const char *buf, const struct kernel_param *kp) unsigned int val, cpu; const char *cp = buf; bool enabled = false; + enum input_boost_type type; + + if (strstr(kp->name, "input_boost_freq")) + type = default_input_boost; + if (strstr(kp->name, "powerkey_input_boost_freq")) + type = powerkey_input_boost; while ((cp = strpbrk(cp + 1, " :"))) ntokens++; @@ -62,8 +81,12 @@ static int set_input_boost_freq(const char *buf, const struct kernel_param *kp) if (!ntokens) { if (sscanf(buf, "%u\n", &val) != 1) return -EINVAL; - for_each_possible_cpu(i) - per_cpu(sync_info, i).input_boost_freq = val; + for_each_possible_cpu(i) { + if (type == default_input_boost) + per_cpu(sync_info, i).input_boost_freq = val; + else if (type == powerkey_input_boost) + per_cpu(sync_info, i).powerkey_input_boost_freq = val; + } goto check_enable; } @@ -78,14 +101,18 @@ static int set_input_boost_freq(const char *buf, const struct kernel_param *kp) if (cpu >= num_possible_cpus()) return -EINVAL; - per_cpu(sync_info, cpu).input_boost_freq = val; + if (type == default_input_boost) + per_cpu(sync_info, cpu).input_boost_freq = val; + else if (type == powerkey_input_boost) + per_cpu(sync_info, cpu).powerkey_input_boost_freq = val; cp = strchr(cp, ' '); cp++; } check_enable: for_each_possible_cpu(i) { - if (per_cpu(sync_info, i).input_boost_freq) { + if (per_cpu(sync_info, i).input_boost_freq + || per_cpu(sync_info, i).powerkey_input_boost_freq) { enabled = true; break; } @@ -99,11 +126,22 @@ static int get_input_boost_freq(char *buf, const struct kernel_param *kp) { int cnt = 0, cpu; struct cpu_sync *s; + unsigned int boost_freq = 0; + enum input_boost_type type; + + if (strstr(kp->name, "input_boost_freq")) + type = default_input_boost; + if (strstr(kp->name, "powerkey_input_boost_freq")) + type = powerkey_input_boost; for_each_possible_cpu(cpu) { s = &per_cpu(sync_info, cpu); + if (type == default_input_boost) + boost_freq = s->input_boost_freq; + else if (type == powerkey_input_boost) + boost_freq = s->powerkey_input_boost_freq; cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, - "%d:%u ", cpu, s->input_boost_freq); + "%d:%u ", cpu, boost_freq); } cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, "\n"); return cnt; @@ -115,6 +153,8 @@ static const struct kernel_param_ops param_ops_input_boost_freq = { }; module_param_cb(input_boost_freq, ¶m_ops_input_boost_freq, NULL, 0644); +module_param_cb(powerkey_input_boost_freq, ¶m_ops_input_boost_freq, NULL, 0644); + /* * The CPUFREQ_ADJUST notifier is used to override the current policy min to * make sure policy min >= boost_min. The cpufreq framework then does the job @@ -221,6 +261,40 @@ static void do_input_boost(struct work_struct *work) msecs_to_jiffies(input_boost_ms)); } +static void do_powerkey_input_boost(struct work_struct *work) +{ + + unsigned int i, ret; + struct cpu_sync *i_sync_info; + cancel_delayed_work_sync(&input_boost_rem); + if (sched_boost_active) { + sched_set_boost(0); + sched_boost_active = false; + } + + /* Set the powerkey_input_boost_min for all CPUs in the system */ + pr_debug("Setting powerkey input boost min for all CPUs\n"); + for_each_possible_cpu(i) { + i_sync_info = &per_cpu(sync_info, i); + i_sync_info->input_boost_min = i_sync_info->powerkey_input_boost_freq; + } + + /* Update policies for all online CPUs */ + update_policy_online(); + + /* Enable scheduler boost to migrate tasks to big cluster */ + if (sched_boost_on_powerkey_input) { + ret = sched_set_boost(1); + if (ret) + pr_err("cpu-boost: HMP boost enable failed\n"); + else + sched_boost_active = true; + } + + queue_delayed_work(cpu_boost_wq, &input_boost_rem, + msecs_to_jiffies(powerkey_input_boost_ms)); +} + static void cpuboost_input_event(struct input_handle *handle, unsigned int type, unsigned int code, int value) { @@ -236,7 +310,11 @@ static void cpuboost_input_event(struct input_handle *handle, if (work_pending(&input_boost_work)) return; - queue_work(cpu_boost_wq, &input_boost_work); + if (type == EV_KEY && code == KEY_POWER) { + queue_work(cpu_boost_wq, &powerkey_input_boost_work); + } else { + queue_work(cpu_boost_wq, &input_boost_work); + } last_input_time = ktime_to_us(ktime_get()); } @@ -321,6 +399,7 @@ static int cpu_boost_init(void) return -EFAULT; INIT_WORK(&input_boost_work, do_input_boost); + INIT_WORK(&powerkey_input_boost_work, do_powerkey_input_boost); INIT_DELAYED_WORK(&input_boost_rem, do_input_boost_rem); for_each_possible_cpu(cpu) { diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index e8c7af52ce406..1e43e74391cff 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -2,6 +2,7 @@ * linux/drivers/cpufreq/cpufreq.c * * Copyright (C) 2001 Russell King + * Copyright (C) 2018 XiaoMi, Inc. * (C) 2002 - 2003 Dominik Brodowski * (C) 2013 Viresh Kumar * @@ -730,6 +731,9 @@ static ssize_t store_##file_name \ \ memcpy(&new_policy, policy, sizeof(*policy)); \ \ + new_policy.min = new_policy.user_policy.min; \ + new_policy.max = new_policy.user_policy.max; \ + \ ret = sscanf(buf, "%u", &new_policy.object); \ if (ret != 1) \ return -EINVAL; \ diff --git a/drivers/cpuidle/lpm-levels.c b/drivers/cpuidle/lpm-levels.c index 0ea769c9aa218..f5065940cfb6f 100755 --- a/drivers/cpuidle/lpm-levels.c +++ b/drivers/cpuidle/lpm-levels.c @@ -1043,9 +1043,18 @@ static int cluster_configure(struct lpm_cluster *cluster, int idx, } if (level->notify_rpm) { + uint64_t us; + uint32_t pred_us; + + us = get_cluster_sleep_time(cluster, NULL, from_idle, + &pred_us); + + us = us + 1; + clear_predict_history(); clear_cl_predict_history(); - if (system_sleep_enter()) + + if (system_sleep_enter(us)) return -EBUSY; } /* Notify cluster enter event after successfully config completion */ @@ -1252,13 +1261,6 @@ int get_cluster_id(struct lpm_cluster *cluster, int *aff_lvl) state_id |= (level->psci_id & cluster->psci_mode_mask) << cluster->psci_mode_shift; (*aff_lvl)++; - - /* - * We may have updated the broadcast timers, update - * the wakeup value by reading the bc timer directly. - */ - if (level->notify_rpm) - system_sleep_update_wakeup(); } unlock_and_return: spin_unlock(&cluster->sync_lock); @@ -1595,6 +1597,9 @@ static void lpm_suspend_wake(void) lpm_stats_suspend_exit(); } +extern void regulator_debug_print_enabled(bool only_enabled); +extern void system_sleep_status_print_enabled(void); +extern void gpio_debug_print(void); static int lpm_suspend_enter(suspend_state_t state) { int cpu = raw_smp_processor_id(); @@ -1621,6 +1626,9 @@ static int lpm_suspend_enter(suspend_state_t state) * LPMs(XO and Vmin). */ clock_debug_print_enabled(true); + regulator_debug_print_enabled(true); + gpio_debug_print(); + system_sleep_status_print_enabled(); psci_enter_sleep(lpm_cpu, idx, false); diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index 2b6b1122e7460..8fe8805721ac7 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -493,8 +493,6 @@ static void __init psci_init_migrate(void) static void __init psci_0_2_set_functions(void) { pr_info("Using standard PSCI v0.2 function IDs\n"); - psci_ops.get_version = psci_get_version; - psci_function_id[PSCI_FN_CPU_SUSPEND] = PSCI_FN_NATIVE(0_2, CPU_SUSPEND); psci_ops.cpu_suspend = psci_cpu_suspend; diff --git a/drivers/firmware/qcom/tz_log.c b/drivers/firmware/qcom/tz_log.c index 9c1c81b66ad6a..ab1eba5b4cb53 100644 --- a/drivers/firmware/qcom/tz_log.c +++ b/drivers/firmware/qcom/tz_log.c @@ -1,4 +1,5 @@ /* Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -23,12 +24,13 @@ #include #include #include +#include #include #include -/* QSEE_LOG_BUF_SIZE = 32K */ -#define QSEE_LOG_BUF_SIZE 0x8000 +/* QSEE_LOG_BUF_SIZE = 64K */ +#define QSEE_LOG_BUF_SIZE 0x10000 /* TZ Diagnostic Area legacy version number */ @@ -855,6 +857,36 @@ const struct file_operations tzdbg_fops = { .open = tzdbgfs_open, }; + +static ssize_t qsee_log_dump_procfs_read(struct file *file, char __user *buf, + size_t count, loff_t *offp) +{ + int len = 0; + + len = _disp_qsee_log_stats(count); + *offp = 0; + + if (len > count) + len = count; + + return simple_read_from_buffer(buf, len, offp, + tzdbg.stat[TZDBG_QSEE_LOG].data, len); +} + + +static int qsee_log_dump_procfs_open(struct inode *inode, struct file *pfile) +{ + pfile->private_data = inode->i_private; + return 0; +} + +const struct file_operations qsee_log_dump_proc_fops = { + .owner = THIS_MODULE, + .read = qsee_log_dump_procfs_read, + .open = qsee_log_dump_procfs_open, +}; + + static struct ion_client *g_ion_clnt; static struct ion_handle *g_ihandle; @@ -969,8 +1001,12 @@ static int tzdbgfs_init(struct platform_device *pdev) goto err; } } + + proc_create("qsee_log_dump", 0, NULL, &qsee_log_dump_proc_fops); + tzdbg.disp_buf = kzalloc(max(debug_rw_buf_size, tzdbg.hyp_debug_rw_buf_size), GFP_KERNEL); + if (tzdbg.disp_buf == NULL) goto err; platform_set_drvdata(pdev, dent_dir); diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 063d176baa24a..c0e58e496926b 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -60,6 +60,17 @@ static struct bus_type gpio_bus_type = { .name = "gpio", }; +static u32 gpio_debug_suspend; +#define gpio_debug_output(m, c, fmt, ...) \ +do { \ + if (m) \ + seq_printf(m, fmt, ##__VA_ARGS__); \ + else if (c) \ + pr_cont(fmt, ##__VA_ARGS__); \ + else \ + pr_info(fmt, ##__VA_ARGS__); \ +} while (0) + /* gpio_lock prevents conflicts during gpio_desc[] table updates. * While any GPIO is requested, its gpio_chip is not removable; * each GPIO's "requested" flag serves as a lock and refcount. @@ -3528,7 +3539,7 @@ static void gpiolib_dbg_show(struct seq_file *s, struct gpio_device *gdev) for (i = 0; i < gdev->ngpio; i++, gpio++, gdesc++) { if (!test_bit(FLAG_REQUESTED, &gdesc->flags)) { if (gdesc->name) { - seq_printf(s, " gpio-%-3d (%-20.20s)\n", + gpio_debug_output(s, 1, " gpio-%-3d (%-20.20s)\n", gpio, gdesc->name); } continue; @@ -3537,14 +3548,14 @@ static void gpiolib_dbg_show(struct seq_file *s, struct gpio_device *gdev) gpiod_get_direction(gdesc); is_out = test_bit(FLAG_IS_OUT, &gdesc->flags); is_irq = test_bit(FLAG_USED_AS_IRQ, &gdesc->flags); - seq_printf(s, " gpio-%-3d (%-20.20s|%-20.20s) %s %s %s", + gpio_debug_output(s, 1, " gpio-%-3d (%-20.20s|%-20.20s) %s %s %s", gpio, gdesc->name ? gdesc->name : "", gdesc->label, is_out ? "out" : "in ", chip->get ? (chip->get(chip, i) ? "hi" : "lo") : "? ", is_irq ? "IRQ" : " "); - seq_printf(s, "\n"); + gpio_debug_output(s, 1, "\n"); } } @@ -3597,24 +3608,30 @@ static int gpiolib_seq_show(struct seq_file *s, void *v) struct device *parent; if (!chip) { - seq_printf(s, "%s%s: (dangling chip)", (char *)s->private, - dev_name(&gdev->dev)); + if (s) + gpio_debug_output(s, 1, "%s%s: (dangling chip)", (char *)s->private, + dev_name(&gdev->dev)); + else + gpio_debug_output(s, 1, "%s: (dangling chip)", dev_name(&gdev->dev)); return 0; } - - seq_printf(s, "%s%s: GPIOs %d-%d", (char *)s->private, - dev_name(&gdev->dev), - gdev->base, gdev->base + gdev->ngpio - 1); + if (s) + gpio_debug_output(s, 1, "%s%s: GPIOs %d-%d", (char *)s->private, + dev_name(&gdev->dev), + gdev->base, gdev->base + gdev->ngpio - 1); + else + gpio_debug_output(s, 1, "%s: GPIOs %d-%d", dev_name(&gdev->dev), + gdev->base, gdev->base + gdev->ngpio - 1); parent = chip->parent; if (parent) - seq_printf(s, ", parent: %s/%s", + gpio_debug_output(s, 1, ", parent: %s/%s", parent->bus ? parent->bus->name : "no-bus", dev_name(parent)); if (chip->label) - seq_printf(s, ", %s", chip->label); + gpio_debug_output(s, 1, ", %s", chip->label); if (chip->can_sleep) - seq_printf(s, ", can sleep"); - seq_printf(s, ":\n"); + gpio_debug_output(s, 1, ", can sleep"); + gpio_debug_output(s, 1, ":\n"); if (chip->dbg_show) chip->dbg_show(s, chip); @@ -3631,8 +3648,31 @@ static const struct seq_operations gpiolib_seq_ops = { .show = gpiolib_seq_show, }; +void gpio_debug_print(void) +{ + struct gpio_chip *gpiochip; + int m = 0; + static const char * const gpio_chip_name[] = { + "3400000.pinctrl", + "c440000.qcom,spmi:qcom,pm8998@0:pinctrl@c000", + "c440000.qcom,spmi:qcom,pm8005@4:pinctrl@c000", + "c440000.qcom,spmi:qcom,pmi8998@2:pinctrl@c000", + }; + + if (likely(!gpio_debug_suspend)) + return; + + pr_info("GPIOs dump:\n"); + for (m = 0; m < sizeof(gpio_chip_name)/sizeof(gpio_chip_name[0]); m++) { + gpiochip = find_chip_by_name(gpio_chip_name[m]); + if (gpiochip) + gpiolib_seq_show(NULL, gpiochip->gpiodev); + } +} + static int gpiolib_open(struct inode *inode, struct file *file) { + gpio_debug_print(); return seq_open(file, &gpiolib_seq_ops); } @@ -3644,11 +3684,15 @@ static const struct file_operations gpiolib_operations = { .release = seq_release, }; +EXPORT_SYMBOL_GPL(gpio_debug_print); + static int __init gpiolib_debugfs_init(void) { /* /sys/kernel/debug/gpio */ (void) debugfs_create_file("gpio", S_IFREG | S_IRUGO, NULL, NULL, &gpiolib_operations); + + debugfs_create_u32("gpio_debug_suspend", 0644, NULL, &gpio_debug_suspend); return 0; } subsys_initcall(gpiolib_debugfs_init); diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c index 0ee052b7c21af..787ad313e1994 100644 --- a/drivers/gpu/drm/drm_bridge.c +++ b/drivers/gpu/drm/drm_bridge.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2014 Samsung Electronics Co., Ltd + * Copyright (C) 2018 XiaoMi, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -231,9 +232,15 @@ void drm_bridge_post_disable(struct drm_bridge *bridge) if (!bridge) return; + if (bridge->is_dsi_drm_bridge) + mutex_lock(&bridge->lock); + if (bridge->funcs->post_disable) bridge->funcs->post_disable(bridge); + if (bridge->is_dsi_drm_bridge) + mutex_unlock(&bridge->lock); + drm_bridge_post_disable(bridge->next); } EXPORT_SYMBOL(drm_bridge_post_disable); @@ -282,11 +289,57 @@ void drm_bridge_pre_enable(struct drm_bridge *bridge) drm_bridge_pre_enable(bridge->next); + if (bridge->is_dsi_drm_bridge) + mutex_lock(&bridge->lock); + if (bridge->funcs->pre_enable) bridge->funcs->pre_enable(bridge); + + if (bridge->is_dsi_drm_bridge) + mutex_unlock(&bridge->lock); } EXPORT_SYMBOL(drm_bridge_pre_enable); +void drm_bridge_disp_param_set(struct drm_bridge *bridge, int cmd) +{ + if (!bridge) + return; + + drm_bridge_disp_param_set(bridge->next, cmd); + + if (bridge->funcs->disp_param_set) + bridge->funcs->disp_param_set(bridge, cmd); +} +EXPORT_SYMBOL(drm_bridge_disp_param_set); + +ssize_t drm_bridge_disp_param_get(struct drm_bridge *bridge, char *pbuf) +{ + ssize_t ret = 0; + + if (!bridge) + return 0; + + ret = drm_bridge_disp_param_get(bridge->next, pbuf); + + if (bridge->funcs->disp_param_get) + ret = bridge->funcs->disp_param_get(bridge, pbuf); + return ret; +} +EXPORT_SYMBOL(drm_bridge_disp_param_get); + +int drm_get_panel_info(struct drm_bridge *bridge, char *buf) +{ + int rc = 0; + if (!bridge) + return rc; + + if (bridge->funcs->disp_get_panel_info) + return bridge->funcs->disp_get_panel_info(bridge, buf); + + return rc; +} +EXPORT_SYMBOL(drm_get_panel_info); + /** * drm_bridge_enable - calls ->enable() &drm_bridge_funcs op for all bridges * in the encoder chain. diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index 71c3473476c74..02308b92ec6da 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -468,6 +468,29 @@ static int drm_version(struct drm_device *dev, void *data, return err; } +#define MAX_TASK_NAME_LEN 30 +#define MAX_LIST_NUM 4 +char support_list[MAX_LIST_NUM][MAX_TASK_NAME_LEN] = { + "displayfeature", + "DisplayFeature", + "disp_pcc" + "displayeffect" +}; + +static bool drm_master_filter(char *task_name) +{ + unsigned int i = 0; + bool ret = false; + + for (i = 0; i < MAX_LIST_NUM; i++) { + + if (!strncmp(task_name, support_list[i], strlen(support_list[i]))) { + ret = true; + break; + } + } + return ret; +} /* * drm_ioctl_permit - Check ioctl permissions against caller * @@ -480,6 +503,7 @@ static int drm_version(struct drm_device *dev, void *data, */ int drm_ioctl_permit(u32 flags, struct drm_file *file_priv) { + struct task_struct *task = get_current(); /* ROOT_ONLY is only for CAP_SYS_ADMIN */ if (unlikely((flags & DRM_ROOT_ONLY) && !capable(CAP_SYS_ADMIN))) return -EACCES; @@ -492,8 +516,11 @@ int drm_ioctl_permit(u32 flags, struct drm_file *file_priv) /* MASTER is only for master or control clients */ if (unlikely((flags & DRM_MASTER) && !drm_is_current_master(file_priv) && - !drm_is_control_client(file_priv))) - return -EACCES; + !drm_is_control_client(file_priv))) { + if (!drm_master_filter(task->comm)) { + return -EACCES; + } + } /* Control clients must be explicitly allowed */ if (unlikely(!(flags & DRM_CONTROL_ALLOW) && diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c index d9a5762ad633f..7091b35a15721 100644 --- a/drivers/gpu/drm/drm_mipi_dsi.c +++ b/drivers/gpu/drm/drm_mipi_dsi.c @@ -362,6 +362,8 @@ static ssize_t mipi_dsi_device_transfer(struct mipi_dsi_device *dsi, msg->flags |= MIPI_DSI_MSG_USE_LPM; msg->flags |= MIPI_DSI_MSG_LASTCOMMAND; + msg->flags |= MIPI_DSI_MSG_LASTCOMMAND; + return ops->transfer(dsi->host, msg); } @@ -1044,6 +1046,20 @@ int mipi_dsi_dcs_set_tear_scanline(struct mipi_dsi_device *dsi, u16 scanline) } EXPORT_SYMBOL(mipi_dsi_dcs_set_tear_scanline); +int mipi_dsi_dcs_set_display_brightness_ss(struct mipi_dsi_device *dsi, + u16 brightness) +{ + u8 payload[2] = { brightness >> 8, brightness & 0xff}; + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, + payload, sizeof(payload)); + if (err < 0) + return err; + + return 0; +} + /** * mipi_dsi_dcs_set_display_brightness() - sets the brightness value of the * display diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c index 9a37196c1bf17..89c8e5851f4fc 100644 --- a/drivers/gpu/drm/drm_sysfs.c +++ b/drivers/gpu/drm/drm_sysfs.c @@ -30,7 +30,6 @@ static struct device_type drm_sysfs_device_minor = { }; struct class *drm_class; - static char *drm_devnode(struct device *dev, umode_t *mode) { return kasprintf(GFP_KERNEL, "dri/%s", dev_name(dev)); @@ -48,6 +47,7 @@ static CLASS_ATTR_STRING(version, S_IRUGO, "drm 1.1.0 20060810"); * * Return: 0 on success, negative error code on failure. */ + int drm_sysfs_init(void) { int err; @@ -215,16 +215,120 @@ static ssize_t modes_show(struct device *device, return written; } +extern int drm_get_panel_info(struct drm_bridge *bridge, char *name); +static ssize_t panel_info_show(struct device *device, + struct device_attribute *attr, + char *buf) +{ + int written = 0; + char pname[128] = {0}; + struct drm_connector *connector = NULL; + struct drm_encoder *encoder = NULL; + struct drm_bridge *bridge = NULL; + + connector = to_drm_connector(device); + if (!connector) + return written; + + encoder = connector->encoder; + if (!encoder) + return written; + + bridge = encoder->bridge; + if (!bridge) + return written; + + written = drm_get_panel_info(bridge, pname); + if (written) + return snprintf(buf, PAGE_SIZE, "panel_name=%s\n", pname); + + return written; +} + +static ssize_t doze_brightness_show(struct device *device, + struct device_attribute *attr, + char *buf) +{ + struct drm_connector *connector = to_drm_connector(device); + struct drm_device *dev = connector->dev; + + return snprintf(buf, PAGE_SIZE, "%d\n", + dev->doze_brightness); +} + +void drm_bridge_disp_param_set(struct drm_bridge *bridge, int cmd); +static ssize_t disp_param_store(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count) +{ + int param; + + struct drm_connector *connector = NULL; + struct drm_encoder *encoder = NULL; + struct drm_bridge *bridge = NULL; + + connector = to_drm_connector(device); + if (!connector) + return count; + + encoder = connector->encoder; + if (!encoder) + return count; + + bridge = encoder->bridge; + if (!bridge) + return count; + + sscanf(buf, "0x%x", ¶m); + + drm_bridge_disp_param_set(bridge, param); + + return count; +} + +ssize_t drm_bridge_disp_param_get(struct drm_bridge *bridge, char *pbuf); +static ssize_t disp_param_show(struct device *device, + struct device_attribute *attr, + char *buf) +{ + ssize_t ret = 0; + struct drm_connector *connector = NULL; + struct drm_encoder *encoder = NULL; + struct drm_bridge *bridge = NULL; + + connector = to_drm_connector(device); + if (!connector) + return ret; + + encoder = connector->encoder; + if (!encoder) + return ret; + + bridge = encoder->bridge; + if (!bridge) + return ret; + + ret = drm_bridge_disp_param_get(bridge, buf); + + return ret; +} + static DEVICE_ATTR_RW(status); static DEVICE_ATTR_RO(enabled); static DEVICE_ATTR_RO(dpms); static DEVICE_ATTR_RO(modes); +static DEVICE_ATTR_RO(panel_info); +static DEVICE_ATTR_RW(disp_param); +static DEVICE_ATTR_RO(doze_brightness); static struct attribute *connector_dev_attrs[] = { &dev_attr_status.attr, &dev_attr_enabled.attr, &dev_attr_dpms.attr, &dev_attr_modes.attr, + &dev_attr_panel_info.attr, + &dev_attr_disp_param.attr, + &dev_attr_doze_brightness.attr, NULL }; @@ -249,7 +353,6 @@ static const struct attribute_group *connector_dev_groups[] = { &connector_dev_group, NULL }; - /** * drm_sysfs_connector_add - add a connector to sysfs * @connector: connector to add @@ -262,7 +365,6 @@ static const struct attribute_group *connector_dev_groups[] = { int drm_sysfs_connector_add(struct drm_connector *connector) { struct drm_device *dev = connector->dev; - if (connector->kdev) return 0; @@ -273,7 +375,6 @@ int drm_sysfs_connector_add(struct drm_connector *connector) connector->name); DRM_DEBUG("adding \"%s\" to sysfs\n", connector->name); - if (IS_ERR(connector->kdev)) { DRM_ERROR("failed to register connector device: %ld\n", PTR_ERR(connector->kdev)); return PTR_ERR(connector->kdev); diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index ba71ce8466a6f..21f0590eb00ff 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -149,3 +149,8 @@ config DRM_SDE_RSC avoids the display core power collapse. A client can also register for display core power collapse events on rsc. +config DRM_SDE_XLOG_DEBUG + bool "Trigger a panic after the dumping work has completed when SDE error" + default n + depends on DRM_MSM + diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c index bfbcf5457b482..42e3b8d6f730c 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c @@ -1401,8 +1401,7 @@ static int dsi_enable_ulps(struct dsi_ctrl *dsi_ctrl) u32 lanes = 0; u32 ulps_lanes; - if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE) - lanes = dsi_ctrl->host_config.common_config.data_lanes; + lanes = dsi_ctrl->host_config.common_config.data_lanes; rc = dsi_ctrl->hw.ops.wait_for_lane_idle(&dsi_ctrl->hw, lanes); if (rc) { @@ -1443,9 +1442,7 @@ static int dsi_disable_ulps(struct dsi_ctrl *dsi_ctrl) return 0; } - if (dsi_ctrl->host_config.panel_mode == DSI_OP_CMD_MODE) - lanes = dsi_ctrl->host_config.common_config.data_lanes; - + lanes = dsi_ctrl->host_config.common_config.data_lanes; lanes |= DSI_CLOCK_LANE; ulps_lanes = dsi_ctrl->hw.ops.ulps_ops.get_lanes_in_ulps(&dsi_ctrl->hw); @@ -2420,6 +2417,31 @@ int dsi_ctrl_host_timing_update(struct dsi_ctrl *dsi_ctrl) return 0; } +/** + * dsi_ctrl_update_host_init_state() - Update the host initialization state. + * @dsi_ctrl: DSI controller handle. + * @enable: boolean signifying host state. + * + * Update the host initialization status only while exiting from ulps during + * suspend state. + * + * Return: error code. + */ +int dsi_ctrl_update_host_init_state(struct dsi_ctrl *dsi_ctrl, bool enable) +{ + int rc = 0; + u32 state = enable ? 0x1 : 0x0; + + rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, state); + if (rc) { + pr_err("[DSI_%d] Controller state check failed, rc=%d\n", + dsi_ctrl->cell_index, rc); + return rc; + } + dsi_ctrl_update_state(dsi_ctrl, DSI_CTRL_OP_HOST_INIT, state); + return rc; +} + /** * dsi_ctrl_host_init() - Initialize DSI host hardware. * @dsi_ctrl: DSI controller handle. diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h index 77df585f65e24..b6feaa0925de9 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -724,4 +725,9 @@ void dsi_ctrl_irq_update(struct dsi_ctrl *dsi_ctrl, bool enable); int dsi_ctrl_get_host_engine_init_state(struct dsi_ctrl *dsi_ctrl, bool *state); +/** + * dsi_ctrl_update_host_init_state() - Set the host initialization state + */ +int dsi_ctrl_update_host_init_state(struct dsi_ctrl *dsi_ctrl, bool en); + #endif /* _DSI_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h index d45f8493d29d4..7ec44157c651d 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -262,10 +263,49 @@ enum dsi_cmd_set_type { DSI_CMD_SET_LP1, DSI_CMD_SET_LP2, DSI_CMD_SET_NOLP, + DSI_CMD_SET_DOZE_HBM, + DSI_CMD_SET_DOZE_LBM, DSI_CMD_SET_PPS, DSI_CMD_SET_ROI, DSI_CMD_SET_TIMING_SWITCH, DSI_CMD_SET_POST_TIMING_SWITCH, + DSI_CMD_SET_DISP_WARM, + DSI_CMD_SET_DISP_DEFAULT, + DSI_CMD_SET_DISP_COLD, + DSI_CMD_SET_DISP_PAPER, + DSI_CMD_SET_DISP_PAPER1, + DSI_CMD_SET_DISP_PAPER2, + DSI_CMD_SET_DISP_PAPER3, + DSI_CMD_SET_DISP_PAPER4, + DSI_CMD_SET_DISP_PAPER5, + DSI_CMD_SET_DISP_PAPER6, + DSI_CMD_SET_DISP_PAPER7, + DSI_CMD_SET_DISP_NORMAL1, + DSI_CMD_SET_DISP_NORMAL2, + DSI_CMD_SET_DISP_SRGB, + DSI_CMD_SET_DISP_CEON, + DSI_CMD_SET_DISP_CEOFF, + DSI_CMD_SET_DISP_CABCUION, + DSI_CMD_SET_DISP_CABCSTILLON, + DSI_CMD_SET_DISP_CABCMOVIEON, + DSI_CMD_SET_DISP_CABCOFF, + DSI_CMD_SET_DISP_SKINCE_CABCUION, + DSI_CMD_SET_DISP_SKINCE_CABCSTILLON, + DSI_CMD_SET_DISP_SKINCE_CABCMOVIEON, + DSI_CMD_SET_DISP_SKINCE_CABCOFF, + DSI_CMD_SET_DISP_DIMMINGON, + DSI_CMD_SET_DISP_ACL_OFF, + DSI_CMD_SET_DISP_ACL_L1, + DSI_CMD_SET_DISP_ACL_L2, + DSI_CMD_SET_DISP_ACL_L3, + DSI_CMD_SET_DISP_HBM_ON, + DSI_CMD_SET_DISP_HBM_OFF, + DSI_CMD_SET_DISP_OFF_MODE, + DSI_CMD_SET_DISP_ON_MODE, + DSI_CMD_SET_READ_XY_COORDINATE, + DSI_CMD_SET_READ_BRIGHTNESS, + DSI_CMD_SET_READ_MAX_LUMINANCE, + DSI_CMD_SET_MAX_LUMINANCE_VALID, DSI_CMD_SET_MAX }; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c index 3d991720e94d7..64418c8457655 100755 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "msm_drv.h" #include "sde_connector.h" @@ -79,6 +80,7 @@ int dsi_display_set_backlight(void *display, u32 bl_lvl) { struct dsi_display *dsi_display = display; struct dsi_panel *panel; + struct drm_device *drm_dev; u32 bl_scale, bl_scale_ad; u64 bl_temp; int rc = 0; @@ -87,18 +89,22 @@ int dsi_display_set_backlight(void *display, u32 bl_lvl) return -EINVAL; panel = dsi_display->panel; - - if (!dsi_panel_initialized(panel)) - return -EINVAL; + drm_dev = dsi_display->drm_dev; panel->bl_config.bl_level = bl_lvl; + if (!dsi_panel_initialized(panel)) { + pr_info("[%s] set backlight before panel initialized, caching value: %d\n", + dsi_display->name, bl_lvl); + return 0; + } + /* scale backlight */ bl_scale = panel->bl_config.bl_scale; bl_temp = bl_lvl * bl_scale / MAX_BL_SCALE_LEVEL; bl_scale_ad = panel->bl_config.bl_scale_ad; - bl_temp = (u32)bl_temp * bl_scale_ad / MAX_AD_BL_SCALE_LEVEL; + pr_debug("bl_scale = %u, bl_scale_ad = %u, bl_lvl = %u\n", bl_scale, bl_scale_ad, (u32)bl_temp); @@ -111,9 +117,15 @@ int dsi_display_set_backlight(void *display, u32 bl_lvl) goto error; } - rc = dsi_panel_set_backlight(panel, (u32)bl_temp); - if (rc) - pr_err("unable to set backlight\n"); + if (drm_dev && drm_dev->doze_state == DRM_BLANK_LP1) { + rc = dsi_panel_set_doze_backlight(display, (u32)bl_temp); + if (rc) + pr_err("unable to set doze backlight\n"); + } else { + rc = dsi_panel_set_backlight(panel, (u32)bl_temp); + if (rc) + pr_err("unable to set backlight\n"); + } rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, DSI_CORE_CLK, DSI_CLK_OFF); @@ -564,6 +576,187 @@ int dsi_display_check_status(void *display) return rc; } +int dsi_display_read_panel(struct dsi_panel *panel, struct dsi_read_config *read_config) +{ + struct mipi_dsi_host *host; + struct dsi_display *display; + struct dsi_display_ctrl *ctrl; + struct dsi_cmd_desc *cmds; + int i, rc = 0, count = 0; + u32 flags = 0; + + if (panel == NULL || read_config == NULL) + return -EINVAL; + + host = panel->host; + if (host) { + display = to_dsi_display(host); + if (display == NULL) + return -EINVAL; + } else + return -EINVAL; + + if (!panel->panel_initialized) { + pr_debug("Panel not initialized\n"); + return -EINVAL; + } + + if (!read_config->enabled) { + pr_info("read operation was not permitted\n"); + return -EPERM; + } + + dsi_display_clk_ctrl(display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_ON); + + ctrl = &display->ctrl[display->cmd_master_idx]; + + rc = dsi_display_cmd_engine_enable(display); + if (rc) { + pr_err("cmd engine enable failed\n"); + rc = -EPERM; + goto exit_ctrl; + } + + if (display->tx_cmd_buf == NULL) { + rc = dsi_host_alloc_cmd_tx_buffer(display); + if (rc) { + pr_err("failed to allocate cmd tx buffer memory\n"); + goto exit; + } + } + + count = read_config->read_cmd.count; + cmds = read_config->read_cmd.cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + + memset(read_config->rbuf, 0x0, sizeof(read_config->rbuf)); + cmds->msg.rx_buf = read_config->rbuf; + cmds->msg.rx_len = read_config->cmds_rlen; + + rc = dsi_ctrl_cmd_transfer(ctrl->ctrl, &(cmds->msg), flags); + if (rc <= 0) { + pr_err("rx cmd transfer failed rc=%d\n", rc); + goto exit; + } + + for (i = 0; i < read_config->cmds_rlen; i++) + pr_info("0x%x ", read_config->rbuf[i]); + pr_info("\n"); + +exit: + dsi_display_cmd_engine_disable(display); +exit_ctrl: + dsi_display_clk_ctrl(display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_OFF); + + return rc; +} + +int dsi_display_read_cmd(struct dsi_panel *panel, u32 packet_count, + u32 length, const char *data, const char *state, u32 rlen) +{ + struct dsi_read_config read_config; + struct dsi_panel_cmd_set *read_cmd; + struct dsi_cmd_desc *cmds; + struct mipi_dsi_host *host; + struct dsi_display *display; + + int rc = 0; + u32 size; + int i, j; + u8 *payload; + + if (packet_count > 1 || packet_count == 0) { + pr_info("temperary no support packet_count(%d) > 1 \n", packet_count); + return -EINVAL; + } + + if (panel == NULL) + return -EINVAL; + + host = panel->host; + if (host) { + display = to_dsi_display(host); + if (display == NULL) + return -EINVAL; + } else + return -EINVAL; + + pr_debug("%s in\n", __func__); + read_cmd = &read_config.read_cmd; + read_config.cmds_rlen = rlen; + + size = packet_count * sizeof(*read_cmd->cmds); + read_cmd->cmds = kzalloc(size, GFP_KERNEL); + if (!read_cmd->cmds) { + pr_info("no memory\n"); + rc = -ENOMEM; + goto error; + } else { + read_cmd->count = packet_count; + read_cmd->ctrl_idx = 0; + cmds = read_cmd->cmds; + for (i = 0; i < read_cmd->count; i++) { + cmds[i].msg.type = data[0]; + cmds[i].last_command = (data[1] == 1 ? true : false); + cmds[i].msg.channel = data[2]; + cmds[i].msg.flags |= (data[3] == 1 ? MIPI_DSI_MSG_REQ_ACK : 0); + cmds[i].msg.ctrl = 0; + cmds[i].post_wait_ms = data[4]; + cmds[i].msg.tx_len = ((data[5] << 8) | (data[6])); + size = cmds[i].msg.tx_len * sizeof(u8); + if (size > length - 7) { + pr_info("payload size is larger than length(%d)\n", length); + goto error_free_mem; + } + payload = kzalloc(size, GFP_KERNEL); + if (!payload) { + rc = -ENOMEM; + goto error_free_mem; + } + + for (j = 0; j < cmds[i].msg.tx_len; j++) + payload[j] = data[7 + j]; + + cmds[i].msg.tx_buf = payload; + data += (7 + cmds[i].msg.tx_len); + } + + if (!state || !strcmp(state, "dsi_lp_mode")) { + read_cmd->state = DSI_CMD_SET_STATE_LP; + } else if (!strcmp(state, "dsi_hs_mode")) { + read_cmd->state = DSI_CMD_SET_STATE_HS; + } else { + pr_err("command state unrecognized-%s\n", state); + goto error_free_payloads; + } + } + + read_config.enabled = true; + + rc = dsi_display_read_panel(display->panel, &read_config); + + if (rc < 0) { + pr_err("[%s] read cmd failed on master,rc=%d\n", + display->name, rc); + goto error_free_payloads; + } + +error_free_payloads: + for (i = i - 1; i >= 0; i--) + kfree(cmds[i].msg.tx_buf); +error_free_mem: + kfree(read_cmd->cmds); + read_cmd->cmds = NULL; +error: + pr_debug("%s out\n", __func__); + return rc; +} static int dsi_display_cmd_prepare(const char *cmd_buf, u32 cmd_buf_len, struct dsi_cmd_desc *cmd, u8 *payload, u32 payload_len) { @@ -726,14 +919,26 @@ static bool dsi_display_get_cont_splash_status(struct dsi_display *display) int dsi_display_set_power(struct drm_connector *connector, int power_mode, void *disp) { + struct drm_device *dev = NULL; struct dsi_display *display = disp; + struct drm_notify_data g_notify_data; int rc = 0; - + int event = 0; if (!display || !display->panel) { pr_err("invalid display/panel\n"); return -EINVAL; } + if (!connector || !connector->dev) { + pr_err("invalid connector/dev\n"); + return -EINVAL; + } else { + dev = connector->dev; + event = dev->doze_state; + } + + g_notify_data.data = &event; + switch (power_mode) { case SDE_MODE_DPMS_LP1: rc = dsi_panel_set_lp1(display->panel); @@ -742,7 +947,9 @@ int dsi_display_set_power(struct drm_connector *connector, rc = dsi_panel_set_lp2(display->panel); break; default: + drm_notifier_call_chain(DRM_EARLY_EVENT_BLANK, &g_notify_data); rc = dsi_panel_set_nolp(display->panel); + drm_notifier_call_chain(DRM_EVENT_BLANK, &g_notify_data); break; } return rc; @@ -1807,18 +2014,34 @@ static int dsi_display_ctrl_init(struct dsi_display *display) int i; struct dsi_display_ctrl *ctrl; - for (i = 0 ; i < display->ctrl_count; i++) { - ctrl = &display->ctrl[i]; - rc = dsi_ctrl_host_init(ctrl->ctrl, - display->is_cont_splash_enabled); - if (rc) { - pr_err("[%s] failed to init host_%d, rc=%d\n", - display->name, i, rc); - goto error_host_deinit; + /* when ULPS suspend feature is enabled, we will keep the lanes in + * ULPS during suspend state and clamp DSI phy. Hence while resuming + * we will programe DSI controller as part of core clock enable. + * After that we should not re-configure DSI controller again here for + * usecases where we are resuming from ulps suspend as it might put + * the HW in bad state. + */ + if (!display->panel->ulps_suspend_enabled || !display->ulps_enabled) { + for (i = 0 ; i < display->ctrl_count; i++) { + ctrl = &display->ctrl[i]; + rc = dsi_ctrl_host_init(ctrl->ctrl, + display->is_cont_splash_enabled); + if (rc) { + pr_err("[%s] failed to init host_%d, rc=%d\n", + display->name, i, rc); + goto error_host_deinit; + } + } + } else { + for (i = 0 ; i < display->ctrl_count; i++) { + ctrl = &display->ctrl[i]; + rc = dsi_ctrl_update_host_init_state(ctrl->ctrl, true); + if (rc) + pr_debug("host init update failed rc=%d\n", rc); } } - return 0; + return rc; error_host_deinit: for (i = i - 1; i >= 0; i--) { ctrl = &display->ctrl[i]; @@ -3851,6 +4074,7 @@ int dsi_display_dev_probe(struct platform_device *pdev) pr_debug("cmdline primary dsi: %s\n", display->name); display_from_cmdline = true; + display->is_prim_display = true; dsi_display_parse_cmdline_topology(display, DSI_PRIMARY); primary_np = pdev->dev.of_node; @@ -4065,6 +4289,7 @@ int dsi_display_drm_bridge_deinit(struct dsi_display *display) return rc; } +extern struct drm_notify_data g_notify_data; int dsi_display_get_info(struct msm_display_info *info, void *disp) { struct dsi_display *display; @@ -4121,6 +4346,8 @@ int dsi_display_get_info(struct msm_display_info *info, void *disp) if (display->panel->esd_config.esd_enabled) info->capabilities |= MSM_DISPLAY_ESD_ENABLED; + g_notify_data.is_primary = info->is_primary; + error: mutex_unlock(&display->display_lock); return rc; @@ -5194,6 +5421,16 @@ int dsi_display_enable(struct dsi_display *display) display->name, rc); goto error; } + + display->panel->dsi_panel_off_mode = false; + + /** + * if backlight level was set via backlight sysfs before the + * panel init, honor that value now + */ + if (display->panel->bl_config.bl_level) + dsi_display_set_backlight(display, + display->panel->bl_config.bl_level); } if (mode->priv_info->dsc_enabled) { diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h index 4cfd4a9ef7872..a778a6573aa6e 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2017, The Linux Foundation.All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -167,6 +168,7 @@ struct dsi_display { struct drm_connector *drm_conn; const char *name; + bool is_prim_display; const char *display_type; struct list_head list; bool is_active; @@ -530,6 +532,8 @@ void dsi_display_enable_event(struct dsi_display *display, int dsi_display_set_backlight(void *display, u32 bl_lvl); +int dsi_panel_set_doze_backlight(struct dsi_display *display, u32 bl_lvl); + /** * dsi_display_check_status() - check if panel is dead or alive * @display: Handle to display. diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c index fd502568689f5..070aa787b5526 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c @@ -16,15 +16,60 @@ #define pr_fmt(fmt) "dsi-drm:[%s] " fmt, __func__ #include #include +#include +#include +#include +#include #include "msm_kms.h" #include "sde_connector.h" #include "dsi_drm.h" #include "sde_trace.h" +static BLOCKING_NOTIFIER_HEAD(drm_notifier_list); + #define to_dsi_bridge(x) container_of((x), struct dsi_bridge, base) #define to_dsi_state(x) container_of((x), struct dsi_connector_state, base) +#define WAIT_RESUME_TIMEOUT 200 + +struct dsi_bridge *gbridge; +static struct delayed_work prim_panel_work; +static atomic_t prim_panel_is_on; +static struct wakeup_source prim_panel_wakelock; + +struct drm_notify_data g_notify_data; + +/** + * drm_register_client - register a client notifier + * @nb: notifier block to callback on events + */ +int drm_register_client(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&drm_notifier_list, nb); +} +EXPORT_SYMBOL(drm_register_client); + +/** + * drm_unregister_client - unregister a client notifier + * @nb: notifier block to callback on events + */ +int drm_unregister_client(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&drm_notifier_list, nb); +} +EXPORT_SYMBOL(drm_unregister_client); + +/** + * drm_notifier_call_chain - notify clients of drm_events + * + */ +int drm_notifier_call_chain(unsigned long val, void *v) +{ + return blocking_notifier_call_chain(&drm_notifier_list, val, v); +} +EXPORT_SYMBOL_GPL(drm_notifier_call_chain); + static void convert_to_dsi_mode(const struct drm_display_mode *drm_mode, struct dsi_display_mode *dsi_mode) { @@ -123,6 +168,10 @@ static void dsi_bridge_pre_enable(struct drm_bridge *bridge) { int rc = 0; struct dsi_bridge *c_bridge = to_dsi_bridge(bridge); + struct drm_device *dev = bridge->dev; + int event = dev->doze_state; + + g_notify_data.data = &event; if (!bridge) { pr_err("Invalid params\n"); @@ -132,6 +181,14 @@ static void dsi_bridge_pre_enable(struct drm_bridge *bridge) if (!c_bridge || !c_bridge->display) pr_err("Incorrect bridge details\n"); + if (c_bridge->display->is_prim_display && atomic_read(&prim_panel_is_on)) { + cancel_delayed_work_sync(&prim_panel_work); + __pm_relax(&prim_panel_wakelock); + pr_debug("%s panel already on\n", __func__); + return; + } + + drm_notifier_call_chain(DRM_EARLY_EVENT_BLANK, &g_notify_data); /* By this point mode should have been validated through mode_fixup */ rc = dsi_display_set_mode(c_bridge->display, &(c_bridge->dsi_mode), 0x0); @@ -163,6 +220,9 @@ static void dsi_bridge_pre_enable(struct drm_bridge *bridge) c_bridge->id, rc); (void)dsi_display_unprepare(c_bridge->display); } + + drm_notifier_call_chain(DRM_EVENT_BLANK, &g_notify_data); + SDE_ATRACE_END("dsi_display_enable"); SDE_ATRACE_END("dsi_bridge_pre_enable"); @@ -170,6 +230,120 @@ static void dsi_bridge_pre_enable(struct drm_bridge *bridge) if (rc) pr_err("Continuous splash pipeline cleanup failed, rc=%d\n", rc); + if (c_bridge->display->is_prim_display) + atomic_set(&prim_panel_is_on, true); +} + +/** + * dsi_bridge_interface_enable - Panel light on interface for fingerprint + * In order to improve panel light on performance when unlock device by + * fingerprint, export this interface for fingerprint.Once finger touch + * happened, it could light on LCD panel in advance of android resume. + * + * @timeout: DSI bridge wait time for android resume and set panel on. + * If timeout, dsi bridge will disable panel to avoid fingerprint + * touch by mistake. + */ + +int dsi_bridge_interface_enable(int timeout) +{ + int ret = 0; + + ret = wait_event_timeout(resume_wait_q, + !atomic_read(&resume_pending), + msecs_to_jiffies(WAIT_RESUME_TIMEOUT)); + if (!ret) { + pr_info("Primary fb resume timeout\n"); + return -ETIMEDOUT; + } + + mutex_lock(&gbridge->base.lock); + + if (atomic_read(&prim_panel_is_on)) { + mutex_unlock(&gbridge->base.lock); + return 0; + } + + if (gbridge->base.dev) + gbridge->base.dev->doze_state = DRM_BLANK_UNBLANK; + + __pm_stay_awake(&prim_panel_wakelock); + dsi_bridge_pre_enable(&gbridge->base); + + if (timeout > 0) + schedule_delayed_work(&prim_panel_work, msecs_to_jiffies(timeout)); + else + __pm_relax(&prim_panel_wakelock); + + mutex_unlock(&gbridge->base.lock); + return ret; +} +EXPORT_SYMBOL(dsi_bridge_interface_enable); + +int panel_disp_param_send(struct dsi_display *display, int cmd); +static void dsi_bridge_disp_param_set(struct drm_bridge *bridge, int cmd) +{ + int rc = 0; + struct dsi_bridge *c_bridge = to_dsi_bridge(bridge); + + if (!c_bridge) { + pr_err("Invalid params\n"); + return; + } + + SDE_ATRACE_BEGIN("panel_disp_param_send"); + rc = panel_disp_param_send(c_bridge->display, cmd); + if (rc) { + pr_err("[%d] DSI disp param send failed, rc=%d\n", + c_bridge->id, rc); + } + SDE_ATRACE_END("panel_disp_param_send"); +} + +static ssize_t dsi_bridge_disp_param_get(struct drm_bridge *bridge, char *buf) +{ + struct dsi_bridge *c_bridge; + struct dsi_display *display; + struct dsi_panel *panel; + ssize_t ret = 0; + + if (!bridge) { + pr_err("Invalid params\n"); + return 0; + } else { + SDE_ATRACE_BEGIN("panel_disp_param_get"); + c_bridge = to_dsi_bridge(bridge); + if (c_bridge == NULL) + return 0; + display = c_bridge->display; + if (display == NULL) + return 0; + panel = display->panel; + if (panel) { + ret = strlen(panel->panel_read_data); + ret = ret > 255 ? 255 : ret; + if (ret > 0) + memcpy(buf, panel->panel_read_data, ret); + } + SDE_ATRACE_END("panel_disp_param_get"); + } + return ret; +} + +static int dsi_bridge_get_panel_info(struct drm_bridge *bridge, char *buf) +{ + int rc = 0; + struct dsi_bridge *c_bridge = to_dsi_bridge(bridge); + + if (!c_bridge) { + pr_err("Invalid params\n"); + return rc; + } + + if (c_bridge->display->name) + return snprintf(buf, PAGE_SIZE, c_bridge->display->name); + + return rc; } static void dsi_bridge_enable(struct drm_bridge *bridge) @@ -220,12 +394,18 @@ static void dsi_bridge_post_disable(struct drm_bridge *bridge) { int rc = 0; struct dsi_bridge *c_bridge = to_dsi_bridge(bridge); + struct drm_device *dev = bridge->dev; + int event = dev->doze_state; + + g_notify_data.data = &event; if (!bridge) { pr_err("Invalid params\n"); return; } + drm_notifier_call_chain(DRM_EARLY_EVENT_BLANK, &g_notify_data); + SDE_ATRACE_BEGIN("dsi_bridge_post_disable"); SDE_ATRACE_BEGIN("dsi_display_disable"); rc = dsi_display_disable(c_bridge->display); @@ -245,6 +425,25 @@ static void dsi_bridge_post_disable(struct drm_bridge *bridge) return; } SDE_ATRACE_END("dsi_bridge_post_disable"); + + drm_notifier_call_chain(DRM_EVENT_BLANK, &g_notify_data); + + if (c_bridge->display->is_prim_display) + atomic_set(&prim_panel_is_on, false); +} + +static void prim_panel_off_delayed_work(struct work_struct *work) +{ + mutex_lock(&gbridge->base.lock); + if (atomic_read(&prim_panel_is_on)) { + if (gbridge->base.dev->doze_state == DRM_BLANK_UNBLANK) + gbridge->base.dev->doze_state = DRM_BLANK_POWERDOWN; + dsi_bridge_post_disable(&gbridge->base); + __pm_relax(&prim_panel_wakelock); + mutex_unlock(&gbridge->base.lock); + return; + } + mutex_unlock(&gbridge->base.lock); } static void dsi_bridge_mode_set(struct drm_bridge *bridge, @@ -383,6 +582,9 @@ static const struct drm_bridge_funcs dsi_bridge_ops = { .disable = dsi_bridge_disable, .post_disable = dsi_bridge_post_disable, .mode_set = dsi_bridge_mode_set, + .disp_param_set = dsi_bridge_disp_param_set, + .disp_get_panel_info = dsi_bridge_get_panel_info, + .disp_param_get = dsi_bridge_disp_param_get, }; int dsi_conn_set_info_blob(struct drm_connector *connector, @@ -733,6 +935,18 @@ struct dsi_bridge *dsi_drm_bridge_init(struct dsi_display *display, } encoder->bridge = &bridge->base; + encoder->bridge->is_dsi_drm_bridge = true; + mutex_init(&encoder->bridge->lock); + + if (display->is_prim_display) { + gbridge = bridge; + atomic_set(&resume_pending, 0); + wakeup_source_init(&prim_panel_wakelock, "prim_panel_wakelock"); + atomic_set(&prim_panel_is_on, false); + init_waitqueue_head(&resume_wait_q); + INIT_DELAYED_WORK(&prim_panel_work, prim_panel_off_delayed_work); + } + return bridge; error_free_bridge: kfree(bridge); @@ -745,5 +959,11 @@ void dsi_drm_bridge_cleanup(struct dsi_bridge *bridge) if (bridge && bridge->base.encoder) bridge->base.encoder->bridge = NULL; + if (bridge == gbridge) { + atomic_set(&prim_panel_is_on, false); + cancel_delayed_work_sync(&prim_panel_work); + wakeup_source_trash(&prim_panel_wakelock); + } + kfree(bridge); } diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h index ec58479d7b4ab..1bf320fef9b34 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h @@ -30,6 +30,7 @@ struct dsi_bridge { struct dsi_display *display; struct dsi_display_mode dsi_mode; + struct mutex lock; }; /** diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c old mode 100755 new mode 100644 index 76714965e556a..58978d52690e0 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -20,8 +21,13 @@ #include