NanoMips: OR combine optimization

Combine OR into INS when there is no masking for
the second register but it holds zero extended
value whose original width is less than equal to
the number of bits from the first register set
to zero.

Author: Nikola Peric

llvm/lib/Target/Mips/MipsISelLowering.cpp

@@ -1129,9 +1129,20 @@ static SDValue attemptOrToIns(SDValue &And, SDValue &Right, SDNode *N,
     if (!(CN = dyn_cast<ConstantSDNode>(Right.getOperand(1))))
       return SDValue();
     unsigned ShiftAmount = CN->getZExtValue();
-    // Second check makes sure that all upper bits are picked up.
-    if ((ShiftAmount != SMPos0) || (SMPos0 + SMSize0 != TSize))
+
+    if ((ShiftAmount != SMPos0))
       return SDValue();
+
+    if ((SMPos0 + SMSize0 != TSize)) {
+      // If a register holds a value that is zero extended
+      // and if the actual size of that value can fit in SMSize0
+      // then we will allow replacement with the INS instruction
+      // because we are sure that we have only leading zeros
+      KnownBits Known = DAG.computeKnownBits(Right.getOperand(0));
+      if (Known.countMaxPopulation() > SMSize0)
+        return SDValue();
+    }
+
     return DAG.getNode(MipsISD::Ins, DL, ValTy, Right.getOperand(0),
                        DAG.getConstant(SMPos0, DL, MVT::i32),
                        DAG.getConstant(SMSize0, DL, MVT::i32),

llvm/test/CodeGen/Mips/nanomips/ins.ll

@@ -60,3 +60,43 @@ define i32 @ins6(i32 %a, i32 %b) {
   %or = or i32 %and1, %shift
   ret i32 %or
 }
+
+define i32 @ins7(i32 %a, i8 %b) {
+  ; CHECK: ins $a0, $a1, 16, 8
+  %and1 = and i32 %a, 4278255615 ; 0xff00ffff
+  %conv = zext i8 %b to i32
+  %shift = shl i32 %conv, 16
+  %or = or i32 %and1, %shift
+  ret i32 %or
+}
+
+define i32 @ins8(i32 %a, i16 %b) {
+  ; CHECK: ins $a0, $a1, 8, 16
+  %and1 = and i32 %a, 4278190335 ; 0xff0000ff
+  %conv = zext i16 %b to i32
+  %shift = shl i32 %conv, 8
+  %or = or i32 %and1, %shift
+  ret i32 %or
+}
+
+define i32 @ins9(i32 %a, i8* %b) {
+  ; CHECK: ins $a0, $a1, 16, 8
+  %val = load i8, i8* %b
+  %and1 = and i32 %a, 4278255615 ; 0xff00ffff
+  %conv = zext i8 %val to i32
+  %shift = shl i32 %conv, 16
+  %or = or i32 %and1, %shift
+  ret i32 %or
+}
+
+define i32 @ins10(i32 %a, i16* %b) {
+  ; CHECK: ins $a0, $a1, 8, 16
+  %val = load i16, i16* %b
+  %and1 = and i32 %a, 4278190335 ; 0xff0000ff
+  %conv = zext i16 %val to i32
+  %shift = shl i32 %conv, 8
+  %or = or i32 %and1, %shift
+  ret i32 %or
+}
+
+