Open-source EDA × AI for chip design — graph-native, local-first tools for STA, GPU-parallelism, and hardware-security analysis.

• 🔭 Currently building Synthesis_project -- a research-prototype EDA suite that treats post-synthesis netlists as graphs and layers analysis (STA-lite, parallelism profiling, hardware-security audit) on top.
• 🎯 Headline result: 14× theoretical parallel speedup on a 1278-node 16×16 multiplier (GL0AM-regime, NVIDIA-inspired analysis).
• 📊 v0.1.0 tagged · 52 tests · CI on Python 3.10 / 3.11 / 3.12 · live Streamlit demo.
• 🌱 Learning: GNNs for circuit analysis, local-LLM agents (Ollama / Llama-3 / Phi-3), GPU-accelerated logic simulation.
• 📫 Reach me: almallikarjun55@gmail.com

EDA · RTL synthesis · static timing analysis · hardware security · GPU-accelerated logic simulation · graph algorithms · AI for chip design

_{Currently building toward an Ollama-backed local LLM agent + a GNN criticality-prediction experiment.
Open to collaboration on AI-for-EDA research.}