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ChuongGoh-armChuongGoh-arm
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[AArch64][GlobalISel] Select SHL({Z|S}EXT, DUP Imm) into {U|S}HLL Imm (llvm#96782)
First commit's PR is llvm#96780 Combines the following instructions: `ushll r0, r0, #0` `shl r0, r0, #3` Into: `ushll r0, r0, #3`
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-72
lines changed

3 files changed

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‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1108,6 +1108,13 @@ def timm32_1_7 : Operand<i32>, TImmLeaf<i32, [{
11081108
let ParserMatchClass = Imm1_7Operand;
11091109
}
11101110

1111+
// imm32_0_7 predicate - True if the 32-bit immediate is in the range [0,7]
1112+
def imm32_0_7 : Operand<i32>, ImmLeaf<i32, [{
1113+
return ((uint32_t)Imm) < 8;
1114+
}]> {
1115+
let ParserMatchClass = Imm0_7Operand;
1116+
}
1117+
11111118
// imm32_0_15 predicate - True if the 32-bit immediate is in the range [0,15]
11121119
def imm32_0_15 : Operand<i32>, ImmLeaf<i32, [{
11131120
return ((uint32_t)Imm) < 16;

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8129,6 +8129,20 @@ def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
81298129
(SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
81308130
V128:$Rn, vecshiftR32Narrow:$imm)>;
81318131

8132+
def : Pat<(shl (v8i16 (zext (v8i8 V64:$Rm))), (v8i16 (AArch64dup (i32 imm32_0_7:$size)))),
8133+
(USHLLv8i8_shift V64:$Rm, (i32 imm32_0_7:$size))>;
8134+
def : Pat<(shl (v4i32 (zext (v4i16 V64:$Rm))), (v4i32 (AArch64dup (i32 imm32_0_15:$size)))),
8135+
(USHLLv4i16_shift V64:$Rm, (i32 imm32_0_15:$size))>;
8136+
def : Pat<(shl (v2i64 (zext (v2i32 V64:$Rm))), (v2i64 (AArch64dup (i64 imm0_31:$size)))),
8137+
(USHLLv2i32_shift V64:$Rm, (trunc_imm imm0_31:$size))>;
8138+
8139+
def : Pat<(shl (v8i16 (sext (v8i8 V64:$Rm))), (v8i16 (AArch64dup (i32 imm32_0_7:$size)))),
8140+
(SSHLLv8i8_shift V64:$Rm, (i32 imm32_0_7:$size))>;
8141+
def : Pat<(shl (v4i32 (sext (v4i16 V64:$Rm))), (v4i32 (AArch64dup (i32 imm32_0_15:$size)))),
8142+
(SSHLLv4i16_shift V64:$Rm, (i32 imm32_0_15:$size))>;
8143+
def : Pat<(shl (v2i64 (sext (v2i32 V64:$Rm))), (v2i64 (AArch64dup (i64 imm0_31:$size)))),
8144+
(SSHLLv2i32_shift V64:$Rm, (trunc_imm imm0_31:$size))>;
8145+
81328146
// Vector sign and zero extensions are implemented with SSHLL and USSHLL.
81338147
// Anyexts are implemented as zexts.
81348148
def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;

‎llvm/test/CodeGen/AArch64/neon-shift-left-long.ll‎

Lines changed: 36 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -3,16 +3,10 @@
33
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
44

55
define <8 x i16> @test_sshll_v8i8(<8 x i8> %a) {
6-
; CHECK-SD-LABEL: test_sshll_v8i8:
7-
; CHECK-SD: // %bb.0:
8-
; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #3
9-
; CHECK-SD-NEXT: ret
10-
;
11-
; CHECK-GI-LABEL: test_sshll_v8i8:
12-
; CHECK-GI: // %bb.0:
13-
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
14-
; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
15-
; CHECK-GI-NEXT: ret
6+
; CHECK-LABEL: test_sshll_v8i8:
7+
; CHECK: // %bb.0:
8+
; CHECK-NEXT: sshll v0.8h, v0.8b, #3
9+
; CHECK-NEXT: ret
1610
%1 = sext <8 x i8> %a to <8 x i16>
1711
%tmp = shl <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
1812
ret <8 x i16> %tmp
@@ -36,16 +30,10 @@ define <8 x i16> @test_sshll_v8i8_big(<8 x i8> %a) {
3630
}
3731

3832
define <4 x i32> @test_sshll_v4i16(<4 x i16> %a) {
39-
; CHECK-SD-LABEL: test_sshll_v4i16:
40-
; CHECK-SD: // %bb.0:
41-
; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #9
42-
; CHECK-SD-NEXT: ret
43-
;
44-
; CHECK-GI-LABEL: test_sshll_v4i16:
45-
; CHECK-GI: // %bb.0:
46-
; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #0
47-
; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
48-
; CHECK-GI-NEXT: ret
33+
; CHECK-LABEL: test_sshll_v4i16:
34+
; CHECK: // %bb.0:
35+
; CHECK-NEXT: sshll v0.4s, v0.4h, #9
36+
; CHECK-NEXT: ret
4937
%1 = sext <4 x i16> %a to <4 x i32>
5038
%tmp = shl <4 x i32> %1, <i32 9, i32 9, i32 9, i32 9>
5139
ret <4 x i32> %tmp
@@ -69,16 +57,10 @@ define <4 x i32> @test_sshll_v4i16_big(<4 x i16> %a) {
6957
}
7058

7159
define <2 x i64> @test_sshll_v2i32(<2 x i32> %a) {
72-
; CHECK-SD-LABEL: test_sshll_v2i32:
73-
; CHECK-SD: // %bb.0:
74-
; CHECK-SD-NEXT: sshll v0.2d, v0.2s, #19
75-
; CHECK-SD-NEXT: ret
76-
;
77-
; CHECK-GI-LABEL: test_sshll_v2i32:
78-
; CHECK-GI: // %bb.0:
79-
; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #0
80-
; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
81-
; CHECK-GI-NEXT: ret
60+
; CHECK-LABEL: test_sshll_v2i32:
61+
; CHECK: // %bb.0:
62+
; CHECK-NEXT: sshll v0.2d, v0.2s, #19
63+
; CHECK-NEXT: ret
8264
%1 = sext <2 x i32> %a to <2 x i64>
8365
%tmp = shl <2 x i64> %1, <i64 19, i64 19>
8466
ret <2 x i64> %tmp
@@ -102,16 +84,10 @@ define <2 x i64> @test_sshll_v2i32_big(<2 x i32> %a) {
10284
}
10385

10486
define <8 x i16> @test_ushll_v8i8(<8 x i8> %a) {
105-
; CHECK-SD-LABEL: test_ushll_v8i8:
106-
; CHECK-SD: // %bb.0:
107-
; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #3
108-
; CHECK-SD-NEXT: ret
109-
;
110-
; CHECK-GI-LABEL: test_ushll_v8i8:
111-
; CHECK-GI: // %bb.0:
112-
; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
113-
; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
114-
; CHECK-GI-NEXT: ret
87+
; CHECK-LABEL: test_ushll_v8i8:
88+
; CHECK: // %bb.0:
89+
; CHECK-NEXT: ushll v0.8h, v0.8b, #3
90+
; CHECK-NEXT: ret
11591
%1 = zext <8 x i8> %a to <8 x i16>
11692
%tmp = shl <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
11793
ret <8 x i16> %tmp
@@ -129,16 +105,10 @@ define <8 x i16> @test_ushll_v8i8_big(<8 x i8> %a) {
129105
}
130106

131107
define <4 x i32> @test_ushll_v4i16(<4 x i16> %a) {
132-
; CHECK-SD-LABEL: test_ushll_v4i16:
133-
; CHECK-SD: // %bb.0:
134-
; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #9
135-
; CHECK-SD-NEXT: ret
136-
;
137-
; CHECK-GI-LABEL: test_ushll_v4i16:
138-
; CHECK-GI: // %bb.0:
139-
; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
140-
; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
141-
; CHECK-GI-NEXT: ret
108+
; CHECK-LABEL: test_ushll_v4i16:
109+
; CHECK: // %bb.0:
110+
; CHECK-NEXT: ushll v0.4s, v0.4h, #9
111+
; CHECK-NEXT: ret
142112
%1 = zext <4 x i16> %a to <4 x i32>
143113
%tmp = shl <4 x i32> %1, <i32 9, i32 9, i32 9, i32 9>
144114
ret <4 x i32> %tmp
@@ -156,16 +126,10 @@ define <4 x i32> @test_ushll_v4i16_big(<4 x i16> %a) {
156126
}
157127

158128
define <2 x i64> @test_ushll_v2i32(<2 x i32> %a) {
159-
; CHECK-SD-LABEL: test_ushll_v2i32:
160-
; CHECK-SD: // %bb.0:
161-
; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #19
162-
; CHECK-SD-NEXT: ret
163-
;
164-
; CHECK-GI-LABEL: test_ushll_v2i32:
165-
; CHECK-GI: // %bb.0:
166-
; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0
167-
; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
168-
; CHECK-GI-NEXT: ret
129+
; CHECK-LABEL: test_ushll_v2i32:
130+
; CHECK: // %bb.0:
131+
; CHECK-NEXT: ushll v0.2d, v0.2s, #19
132+
; CHECK-NEXT: ret
169133
%1 = zext <2 x i32> %a to <2 x i64>
170134
%tmp = shl <2 x i64> %1, <i64 19, i64 19>
171135
ret <2 x i64> %tmp
@@ -190,8 +154,8 @@ define <8 x i16> @test_sshll2_v16i8(<16 x i8> %a) {
190154
;
191155
; CHECK-GI-LABEL: test_sshll2_v16i8:
192156
; CHECK-GI: // %bb.0:
193-
; CHECK-GI-NEXT: sshll2 v0.8h, v0.16b, #0
194-
; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
157+
; CHECK-GI-NEXT: mov d0, v0.d[1]
158+
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #3
195159
; CHECK-GI-NEXT: ret
196160
%1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
197161
%2 = sext <8 x i8> %1 to <8 x i16>
@@ -225,8 +189,8 @@ define <4 x i32> @test_sshll2_v8i16(<8 x i16> %a) {
225189
;
226190
; CHECK-GI-LABEL: test_sshll2_v8i16:
227191
; CHECK-GI: // %bb.0:
228-
; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0
229-
; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
192+
; CHECK-GI-NEXT: mov d0, v0.d[1]
193+
; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #9
230194
; CHECK-GI-NEXT: ret
231195
%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
232196
%2 = sext <4 x i16> %1 to <4 x i32>
@@ -260,8 +224,8 @@ define <2 x i64> @test_sshll2_v4i32(<4 x i32> %a) {
260224
;
261225
; CHECK-GI-LABEL: test_sshll2_v4i32:
262226
; CHECK-GI: // %bb.0:
263-
; CHECK-GI-NEXT: sshll2 v0.2d, v0.4s, #0
264-
; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
227+
; CHECK-GI-NEXT: mov d0, v0.d[1]
228+
; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #19
265229
; CHECK-GI-NEXT: ret
266230
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
267231
%2 = sext <2 x i32> %1 to <2 x i64>
@@ -295,8 +259,8 @@ define <8 x i16> @test_ushll2_v16i8(<16 x i8> %a) {
295259
;
296260
; CHECK-GI-LABEL: test_ushll2_v16i8:
297261
; CHECK-GI: // %bb.0:
298-
; CHECK-GI-NEXT: ushll2 v0.8h, v0.16b, #0
299-
; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
262+
; CHECK-GI-NEXT: mov d0, v0.d[1]
263+
; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #3
300264
; CHECK-GI-NEXT: ret
301265
%1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
302266
%2 = zext <8 x i8> %1 to <8 x i16>
@@ -324,8 +288,8 @@ define <4 x i32> @test_ushll2_v8i16(<8 x i16> %a) {
324288
;
325289
; CHECK-GI-LABEL: test_ushll2_v8i16:
326290
; CHECK-GI: // %bb.0:
327-
; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0
328-
; CHECK-GI-NEXT: shl v0.4s, v0.4s, #9
291+
; CHECK-GI-NEXT: mov d0, v0.d[1]
292+
; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #9
329293
; CHECK-GI-NEXT: ret
330294
%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
331295
%2 = zext <4 x i16> %1 to <4 x i32>
@@ -353,8 +317,8 @@ define <2 x i64> @test_ushll2_v4i32(<4 x i32> %a) {
353317
;
354318
; CHECK-GI-LABEL: test_ushll2_v4i32:
355319
; CHECK-GI: // %bb.0:
356-
; CHECK-GI-NEXT: ushll2 v0.2d, v0.4s, #0
357-
; CHECK-GI-NEXT: shl v0.2d, v0.2d, #19
320+
; CHECK-GI-NEXT: mov d0, v0.d[1]
321+
; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #19
358322
; CHECK-GI-NEXT: ret
359323
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
360324
%2 = zext <2 x i32> %1 to <2 x i64>

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