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ci: cache a port's submodules in an entry of their own
Every board job of a port cloned the port's submodules over the network:
stm's 29 CMSIS and HAL repositories take 59 seconds a job, raspberrypi's
sdk, lwip, cyw43 and PicoDVI 17 seconds, 159 times per full run. The
common submodule cache holds extmod/ulab, lib/ and tools/ and stays as it
is; board jobs add a second entry with ports/<port>, keyed by the port
and the state of its submodules. espressif and zephyr-cp keep their own
arrangements.1 parent a156588 commit b8275f4
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