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This repository is created to build a single cycle processor and converting it to a 5-stage pipelined processor capable of executing a bubble sort program.

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
PiplinedProcessor		PiplinedProcessor
SingleCycleProcessor		SingleCycleProcessor
README.md		README.md

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Single-Cycle-RISCV-Processor

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This repository is created to build a single cycle processor and converting it to a 5-stage pipelined processor capable of executing a bubble sort program.

verilog computer-architecture risc-v pipelined-processors single-cycle-processor

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