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armdata.js
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armdata.js
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// [armdata.js]
// ARM instruction-set data.
//
// [License]
// Public Domain.
// This file can be parsed as pure JSON, locate ${JSON:BEGIN} and ${JSON:END}
// marks and strip everything outside, a sample JS function that would do the job:
//
// function strip(s) {
// return s.replace(/(^.*\$\{JSON:BEGIN\}\s+)|(\/\/\s*\$\{JSON:END\}\s*.*$)/g, "");
// }
// INSTRUCTION TUPLE
// -----------------
//
// Each instruction tuple consists of 5 strings:
//
// [0] - Instruction name.
// [1] - Instruction operands.
// [2] - Instruction type (specifies instruction's layout and architecture as well).
// [3] - Instruction opcode (fields separated by '|' forming the instruction word or halfword).
// [4] - Instruction metadata - CPU requirements, APSR (read/write), and other metadata.
//
// The fields should match ARM instruction reference manual as possible, however,
// it's allowed to make changes that make parsing easier and data more consistent.
// INSTRUCTION OPERANDS
// --------------------
//
// Instruction operands contain standard operand field(s) as defined by ARM
// instruction reference, and also additional metadata that is defined by
// ARM, but in notes section (instead of instruction format section). Additional
// data include:
//
// - "R?!=HI" - The register cannot be R8..R15 (most T16 instructions).
// - "R?!=PC" - The register cannot be R15 (PC).
// - "R?!=SP" - The register cannot be R13 (SP).
// - "R?!=XX" - The register cannot be R13 (SP) or R15 (PC).
// - "??<=07" - The register must be from 0..7 (some ASIMD instructions).
// - "??<=15" - The register must be from 0..15 (some ASIMD instructions).
//
// Also, all instructions that use T16 layout were normalized into 3 operand
// form to make these compatible with T32 and A32 architecturess. It was designed
// for convenience. These are easily recognizable as they always share the first
// two operands.
//
// Divergence from ARM Manual:
// - "Rdn" register (used by T16) was renamed to Rx to make the table easier to
// read when multiple instructions follow (register names have the same length).
// METADATA
// --------
//
// The following metadata is used to describe instructions:
//
// "ARMv??"
/// - Required ARM version:
// - '+' sign means it's supported by that version and above.
// - '-' sign means it's deprecated (and discontinued) by that version.
//
// "APSR"
// - The instruction reads/writes APSR register:
// - [N|Z|C|V] - Which flags are read/written
// - Since most of ARM instructions provide conditional execution the
// APSR mostly defines APSR writes, as reads are controlled by IT
// or condition code {cond}, which is part of each instruction.
//
// "APSR_IF_NOT_PC"
// - Instruction writes to APSR register only if the destination register
// is not R15 (PC). In that case APSR is not modified (ARM specific).
//
// TODO: MISSING/REVIEW:
// cdp
// cdp2
// chka
// cps
// enterx
// leavex
// HB, HBL, HBLP, HBP
// ldc / ldc2
// ADD 'mov' with shift spec.
// MRS/MSR <banked_reg>
// RFE
// SMC
// SRS
// STC / SRC2
// STC
// STM
// SUBS PC, LR
//
// vl?
// vmrs
// vmsr
// vpop
// vpush
// vst?
// vstm
// vstr
// TODO (Metadata):
// ARMv8-A removes UNPREDICTABLE for R13
// if ArchVersion() < 6 && d == n then UNPREDICTABLE;
(function($export, $as) {
"use strict";
$export[$as] =
// ${JSON:BEGIN}
{
"architectures": [
"T16",
"T32",
"A32",
"A64"
],
"cpuLevels": [
{ "name": "ARMv4" },
{ "name": "ARMv4T" },
{ "name": "ARMv5T" },
{ "name": "ARMv5TE" },
{ "name": "ARMv5TEJ" },
{ "name": "ARMv6" },
{ "name": "ARMv6K" },
{ "name": "ARMv6T2" },
{ "name": "ARMv7" },
{ "name": "ARMv8" },
{ "name": "ARMv8_1" },
{ "name": "ARMv8_2" }
],
"extensions": [
{ "name": "VFPv2" , "from": "ARMv8" },
{ "name": "VFPv3" , "from": "ARMv8" },
{ "name": "VFPv3_FP16" , "from": "ARMv8" },
{ "name": "VFPv4" , "from": "ARMv8" },
{ "name": "IDIVT" , "from": "ARMv7+" },
{ "name": "IDIVA" , "from": "ARMv8+" },
{ "name": "CRC32" , "from": "ARMv8_1+" },
{ "name": "ASIMD" , "from": "" },
{ "name": "AES" , "from": "" },
{ "name": "SHA1" , "from": "" },
{ "name": "SHA256" , "from": "" },
{ "name": "SECURITY" , "from": "" }
],
"attributes": [
{ "name": "ALIAS_OF" , "type": "string" , "doc": "The instruction is an alias instruction of ... ." },
{ "name": "PSEUDO_OF" , "type": "string" , "doc": "The instruction is a pseudo instruction of ... ." },
{ "name": "IT_IN" , "type": "flag" , "doc": "Instruction can be executed inside IT block." },
{ "name": "IT_OUT" , "type": "flag" , "doc": "Instruction can be executed outside IT block." },
{ "name": "IT_LAST" , "type": "flag" , "doc": "Instruction must be executed last in IT block." },
{ "name": "T16_LDM" , "type": "flag" , "doc": "Writeback is enabled if Rn is specified also in RdList." },
{ "name": "T32_LDM" , "type": "flag" , "doc": "RdList can contain one of R15|R14 and requires at least 2 registers." },
{ "name": "LSL_3_IF_SP" , "type": "flag" , "doc": "Restricts the shift operation to LSL by a maximum amount of 3 bit if the destination register is SP." },
{ "name": "ARMv6T2_IF_LOW" , "type": "flag" , "doc": "ARMv6T2+ required if both registers are low (R0..R7)." },
{ "name": "UNPRED_COMPLEX" , "type": "flag" , "doc": "Unpredictable based on complex rules." },
{ "name": "UNPRED_IF_ALL_LOW", "type": "flag" , "doc": "Unpredictable if both registers are low (R0..R7)." },
{ "name": "VEC_NARROW" , "type": "flag" , "doc": "SIMD instruction that narrows input vector(s)." },
{ "name": "VEC_WIDEN" , "type": "flag" , "doc": "SIMD instruction that widens input vector(s)." },
{ "name": "Op_CMode" , "type": "string[]" , "doc": "Array of possible OP and CMode combinations." }
],
"specialRegs": [
{ "name": "APSR.N" , "group": "APSR.N" , "doc": "Negative flag." },
{ "name": "APSR.Z" , "group": "APSR.Z" , "doc": "Zero flag." },
{ "name": "APSR.C" , "group": "APSR.C" , "doc": "Carry or unsigned overflow flag." },
{ "name": "APSR.V" , "group": "APSR.V" , "doc": "Signed overflow flag." },
{ "name": "APSR.Q" , "group": "APSR.Q" , "doc": "Sticky saturation flag." },
{ "name": "APSR.GE" , "group": "APSR.GE" , "doc": "Greater than or equal flag." },
{ "name": "CPSR.IT" , "group": "CPSR.IT" , "doc": "If-then bits." },
{ "name": "CPSR.J" , "group": "CPSR.J" , "doc": "Jazelle bit." },
{ "name": "CPSR.E" , "group": "CPSR.E" , "doc": "Endianness bit." },
{ "name": "CPSR.A" , "group": "CPSR.A" , "doc": "Imprecise abort disable bit." },
{ "name": "CPSR.I" , "group": "CPSR.I" , "doc": "IRQ disable bit." },
{ "name": "CPSR.F" , "group": "CPSR.F" , "doc": "FIQ disable bit." },
{ "name": "CPSR.T" , "group": "CPSR.T" , "doc": "Thumb mode bit." },
{ "name": "CPSR.M" , "group": "CPSR.M" , "doc": "Current processor mode." },
{ "name": "IPSR.N" , "group": "IPSR.N" , "doc": "ISR number." },
{ "name": "FPCSR.N" , "group": "FPCSR.N" , "doc": "Less than flag." },
{ "name": "FPCSR.Z" , "group": "FPCSR.Z" , "doc": "Equal flag." },
{ "name": "FPCSR.C" , "group": "FPCSR.C" , "doc": "Equal, greater than, or unordered flag." },
{ "name": "FPCSR.V" , "group": "FPCSR.V" , "doc": "Unordered flag." },
{ "name": "FPCSR.Q" , "group": "FPCSR.Q" , "doc": "Sticky saturation flag." },
{ "name": "FPCSR.AHP" , "group": "FPCSR.MODE" , "doc": "Alternative half-precision control bit." },
{ "name": "FPCSR.DN" , "group": "FPCSR.MODE" , "doc": "Default NaN mode enable bit." },
{ "name": "FPCSR.FZ" , "group": "FPCSR.MODE" , "doc": "Flush-to-zero mode enable bit." },
{ "name": "FPCSR.RMode" , "group": "FPCSR.MODE" , "doc": "Rounding mode control field." },
{ "name": "FPCSR.Stride" , "group": "FPCSR.VEC" , "doc": "Vector stride." },
{ "name": "FPCSR.Length" , "group": "FPCSR.VEC" , "doc": "Vector length." },
{ "name": "FPCSR.IDE" , "group": "FPCSR.EXC" , "doc": "Input subnormal exception enable bit." },
{ "name": "FPCSR.IXE" , "group": "FPCSR.EXC" , "doc": "Inexact exception enable bit." },
{ "name": "FPCSR.UFE" , "group": "FPCSR.EXC" , "doc": "Underflow exception enable bit." },
{ "name": "FPCSR.OFE" , "group": "FPCSR.EXC" , "doc": "Overflow exception enable bit." },
{ "name": "FPCSR.DZE" , "group": "FPCSR.EXC" , "doc": "Division by zero exception enable bit." },
{ "name": "FPCSR.IOE" , "group": "FPCSR.EXC" , "doc": "Invalid operation exception enable bit." },
{ "name": "FPCSR.IDC" , "group": "FPCSR.CUM" , "doc": "Input subnormal cumulative flag." },
{ "name": "FPCSR.IXC" , "group": "FPCSR.CUM" , "doc": "Inexact cumulative flag." },
{ "name": "FPCSR.UFC" , "group": "FPCSR.CUM" , "doc": "Underflow cumulative flag." },
{ "name": "FPCSR.OFC" , "group": "FPCSR.CUM" , "doc": "Overflow cumulative flag." },
{ "name": "FPCSR.DZC" , "group": "FPCSR.CUM" , "doc": "Division by zero cumulative flag." },
{ "name": "FPCSR.IOC" , "group": "FPCSR.CUM" , "doc": "Invalid operation cumulative flag." }
],
"shortcuts": [
{ "name": "APSR.NZ" , "expand": "APSR.N|Z" },
{ "name": "APSR.NZC" , "expand": "APSR.N|Z|C" },
{ "name": "APSR.NZCV" , "expand": "APSR.N|Z|C|V" }
],
"registers": {
"r" : { "kind": "gp" , "any": "r", "names": ["r0-31"] },
"w" : { "kind": "gp" , "any": "w", "names": ["w0-31"] },
"x" : { "kind": "gp" , "any": "x", "names": ["x0-31"] },
"s" : { "kind": "vec", "any": "s", "names": ["s0-31"] },
"d" : { "kind": "vec", "any": "d", "names": ["d0-31"] },
"v" : { "kind": "vec", "any": "v", "names": ["v0-31"] }
},
"instructions": [
["adc" , "Rd!=XX, Rn!=XX, #ImmA" , "T32", "1111|0|ImmA:1|0|1010|0|Rn|0|ImmA:3|Rd|ImmA:8" , "ARMv6T2+ IT=ANY"],
["adcS" , "Rd!=XX, Rn!=XX, #ImmA" , "T32", "1111|0|ImmA:1|0|1010|1|Rn|0|ImmA:3|Rd|ImmA:8" , "ARMv6T2+ IT=ANY APSR.NZCV=W APSR_IF_NOT_PC"],
["adc" , "Rd , Rn , #ImmA" , "A32", "Cond|001|0101|0|Rn|Rd|ImmA:12" , "ARMv4+"],
["adcS" , "Rd!=PC, Rn , #ImmA" , "A32", "Cond|001|0101|1|Rn|Rd|ImmA:12" , "ARMv4+ APSR.NZCV=W"],
["adc" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|000|101|Rm:3|Rx:3" , "ARMv4T+ IT=IN"],
["adcS" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|000|101|Rm:3|Rx:3" , "ARMv4T+ IT=OUT APSR.NZCV=W APSR_IF_NOT_PC"],
["adc" , "Rd , Rn , Rm , {Sop #Shift}" , "A32", "Cond|000|0101|0|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+"],
["adcS" , "Rd!=PC, Rn , Rm , {Sop #Shift}" , "A32", "Cond|000|0101|1|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+ APSR.NZCV=W"],
["adc" , "Rd!=XX, Rn!=XX, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|1010|0|Rn|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY"],
["adcS" , "Rd!=XX, Rn!=XX, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|1010|1|Rn|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY APSR.NZCV=W APSR_IF_NOT_PC"],
["adc" , "Rd!=PC, Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|0101|0|Rn|Rd|Rs|0|Sop:2|1|Rm" , "ARMv4+"],
["adcS" , "Rd!=PC, Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|0101|1|Rn|Rd|Rs|0|Sop:2|1|Rm" , "ARMv4+ APSR.NZCV=W"],
["add" , "Rx!=HI, Rx!=HI, #ImmZ" , "T16", "0011|0|Rx:3|ImmZ:8" , "ARMv4T+ IT=IN"],
["addS" , "Rx!=HI, Rx!=HI, #ImmZ" , "T16", "0011|0|Rx:3|ImmZ:8" , "ARMv4T+ IT=OUT APSR.NZCV=W"],
["add" , "Rd!=HI, Rn!=HI, #ImmZ" , "T16", "0001|110|ImmZ:3|Rn:3|Rd:3" , "ARMv4T+ IT=IN"],
["addS" , "Rd!=HI, Rn!=HI, #ImmZ" , "T16", "0001|110|ImmZ:3|Rn:3|Rd:3" , "ARMv4T+ IT=OUT APSR.NZCV=W"],
["add" , "Rx==SP, Rx==SP, #ImmZ*4" , "T16", "1011|00000|ImmZ:7" , "ARMv4T+ IT=ANY"],
["add" , "Rd!=SP, Rn==SP, #ImmZ*4" , "T16", "1010|1|Rd:3|ImmZ:8" , "ARMv4T+ IT=ANY"],
["add" , "Rd!=XX, Rn!=PC, #ImmZ" , "T32", "1111|0|ImmZ:1|1|0000|0|Rn|0|ImmZ:3|Rd|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["add" , "Rd!=XX, Rn!=PC, #ImmA" , "T32", "1111|0|ImmA:1|0|1000|0|Rn|0|ImmA:3|Rd|ImmA:8" , "ARMv6T2+ IT=ANY"],
["addS" , "Rd!=XX, Rn!=PC, #ImmA" , "T32", "1111|0|ImmA:1|0|1000|1|Rn|0|ImmA:3|Rd|ImmA:8" , "ARMv6T2+ IT=ANY APSR.NZCV=W"],
["add" , "Rd!=PC, Rn==SP, #ImmZ" , "T32", "1111|0|ImmZ:1|1|0000|0|1101|0|ImmZ:3|Rd|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["add" , "Rd!=PC, Rn==SP, #ImmA" , "T32", "1111|0|ImmA:1|0|1000|0|1101|0|ImmA:3|Rd|ImmA:8" , "ARMv6T2+ IT=ANY"],
["addS" , "Rd!=PC, Rn==SP, #ImmA" , "T32", "1111|0|ImmA:1|0|1000|1|1101|0|ImmA:3|Rd|ImmA:8" , "ARMv6T2+ IT=ANY APSR.NZCV=W"],
["add" , "Rd , Rn!=XX, #ImmA" , "A32", "Cond|001|0100|0|Rn|Rd|ImmA:12" , "ARMv4+"],
["addS" , "Rd!=PC, Rn!=SP, #ImmA" , "A32", "Cond|001|0100|1|Rn|Rd|ImmA:12" , "ARMv4+ APSR.NZCV=W"],
["add" , "Rd , Rn==SP, #ImmA" , "A32", "Cond|001|0100|0|1101|Rd|ImmA:12" , "ARMv4+"],
["addS" , "Rd!=PC, Rn==SP, #ImmA" , "A32", "Cond|001|0100|1|1101|Rd|ImmA:12" , "ARMv4+ APSR.NZCV=W"],
["add" , "Rd!=HI, Rn!=HI, Rm!=HI" , "T16", "0001|100|Rm:3|Rn:3|Rd:3" , "ARMv4T+ IT=IN"],
["addS" , "Rd!=HI, Rn!=HI, Rm!=HI" , "T16", "0001|100|Rm:3|Rn:3|Rd:3" , "ARMv4T+ IT=OUT APSR.NZCV=W"],
["add" , "Rx!=XX, Rx!=XX, Rm!=XX" , "T16", "0100|010|0|Rx:1|Rm:4|Rx:3" , "ARMv4T+ IT=IN ARMv6T2_IF_LOW"],
["add" , "Rx , Rx , Rm==SP" , "T16", "0100|010|0|Rx:1|1101|Rx:3" , "ARMv4T+ IT=ANY"],
["add" , "Rx==SP, Rx==SP, Rm" , "T16", "0100|010|0|1|Rm:4|101" , "ARMv4T+ IT=ANY"],
["add" , "Rd!=XX, Rn!=PC, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|1000|0|Rn|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY"],
["addS" , "Rd!=XX, Rn!=PC, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|1000|1|Rn|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY"],
["add" , "Rd!=PC, Rn==SP, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|1000|0|1101|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY LSL_3_IF_SP"],
["addS" , "Rd!=PC, Rn==SP, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|1000|1|1101|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY LSL_3_IF_SP"],
["add" , "Rd , Rn!=SP, Rm , {Sop #Shift}" , "A32", "Cond|000|0100|0|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+"],
["addS" , "Rd!=PC, Rn!=SP, Rm , {Sop #Shift}" , "A32", "Cond|000|0100|1|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+ APSR.NZCV=W"],
["add" , "Rd , Rn==SP, Rm , {Sop #Shift}" , "A32", "Cond|000|0100|0|1101|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+"],
["addS" , "Rd!=PC, Rn==SP, Rm , {Sop #Shift}" , "A32", "Cond|000|0100|1|1101|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+ APSR.NZCV=W"],
["add" , "Rd!=PC, Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|0100|0|Rn|Rd|Rs|0|Sop:2|1|Rm" , "ARMv4+"],
["addS" , "Rd!=PC, Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|0100|1|Rn|Rd|Rs|0|Sop:2|1|Rm" , "ARMv4+ APSR.NZCV=W"],
["adr" , "Rd!=HI, #RelZ*4" , "T16", "1010|0|Rd:3|RelZ:8" , "ARMv4T+ IT=ANY ADD=1"],
["adr" , "Rd!=XX, #RelZ" , "T32", "1111|0|RelZ:1|10000|0|1111|0|RelZ:3|Rd|RelZ:8" , "ARMv6T2+ IT=ANY ADD=1"],
["adr" , "Rd!=XX, #RelZ" , "T32", "1111|0|RelZ:1|10101|0|1111|0|RelZ:3|Rd|RelZ:8" , "ARMv6T2+ IT=ANY ADD=0"],
["adr" , "Rd , #RelA" , "A32", "Cond|001|0100|0|1111|Rd|RelA:12" , "ARMv4+ ADD=1"],
["adr" , "Rd , #RelA" , "A32", "Cond|001|0010|0|1111|Rd|RelA:12" , "ARMv4+ ADD=0"],
["and" , "Rd!=XX, Rn!=XX, #ImmC" , "T32", "1111|0|ImmC:1|0|1010|0|Rn|0|ImmC:3|Rd|ImmC:8" , "ARMv6T2+ IT=ANY"],
["andS" , "Rd!=XX, Rn!=XX, #ImmC" , "T32", "1111|0|ImmC:1|0|1010|1|Rn|0|ImmC:3|Rd|ImmC:8" , "ARMv6T2+ IT=ANY APSR.NZCV=W APSR_IF_NOT_PC"],
["and" , "Rd , Rn , #ImmC" , "A32", "Cond|001|0000|0|Rn|Rd|ImmC:12" , "ARMv4+"],
["andS" , "Rd!=PC, Rn , #ImmC" , "A32", "Cond|001|0000|1|Rn|Rd|ImmC:12" , "ARMv4+ APSR.NZC=W"],
["and" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|000|000|Rm:3|Rx:3" , "ARMv4T+ IT=IN"],
["andS" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|000|000|Rm:3|Rx:3" , "ARMv4T+ IT=OUT APSR.NZ=W"],
["and" , "Rd , Rn , Rm, {Sop #Shift}" , "A32", "Cond|000|0000|0|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+"],
["andS" , "Rd!=PC, Rn , Rm, {Sop #Shift}" , "A32", "Cond|000|0000|1|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+ APSR.NZC=W"],
["and" , "Rd!=XX, Rn!=XX, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|0000|0|Rn|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY"],
["andS" , "Rd!=XX, Rn!=XX, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|0000|1|Rn|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["and" , "Rd!=PC, Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|0000|0|Rn|Rd|Rs|0|Sop:2|1|Rm" , "ARMv4+"],
["andS" , "Rd!=PC, Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|0000|1|Rn|Rd|Rs|0|Sop:2|1|Rm" , "ARMv4+ APSR.NZC=W"],
["asr" , "Rd!=HI, Rn!=HI, #Shift" , "T16", "0001|0|Shift:5|Rn:3|Rd:3" , "ARMv4T+ IT=IN"],
["asrS" , "Rd!=HI, Rn!=HI, #Shift" , "T16", "0001|0|Shift:5|Rn:3|Rd:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["asr" , "Rd!=XX, Rn!=XX, #Shift" , "T32", "1110|101|0010|0|1111|0|Shift:3|Rd|Shift:2|10|Rn" , "ARMv6T2+ IT=ANY"],
["asrS" , "Rd!=XX, Rn!=XX, #Shift" , "T32", "1110|101|0010|1|1111|0|Shift:3|Rd|Shift:2|10|Rn" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["asr" , "Rd , Rn , #Shift" , "A32", "Cond|000|1101|0|0000|Rd|Shift:5|100|Rn" , "ARMv4+"],
["asrS" , "Rd , Rn , #Shift" , "A32", "Cond|000|1101|1|0000|Rd|Shift:5|100|Rn" , "ARMv4+ APSR.NZC=W"],
["asr" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|000|100|Rm:3|Rx:3" , "ARMv4T+ IT=IN"],
["asrS" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|000|100|Rm:3|Rx:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["asr" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0010|0|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY"],
["asrS" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0010|1|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["asr" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1101|0|0000|Rd|Rm|0101|Rn" , "ARMv4+"],
["asrS" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1101|1|0000|Rd|Rm|0101|Rn" , "ARMv4+ APSR.NZC=W"],
["b" , "#RelS*2" , "T16", "1101|Cond|RelS:8" , "ARMv4T+ IT=OUT"],
["b" , "#RelS*2" , "T16", "1110|0|RelS:11" , "ARMv4T+ IT=OUT|LAST"],
["b" , "#RelS*2" , "T32", "1111|0|RelS[19]|Cond|RelS[16:11]|10|J|0|K|RelS[10:0]" , "ARMv6T2+ IT=OUT"],
["b" , "#RelS*2" , "T32", "1111|0|RelS[23]| RelS[20:11]|10|J|1|K|RelS[10:0]" , "ARMv6T2+ IT=OUT|LAST"],
["b" , "#RelS*4" , "A32", "Cond|101|0|RelS:24" , "ARMv4+"],
["bfc" , "Rd!=XX, #LSB, #Width" , "T32", "1111|001|1011|0|1111|0|LSB:3|Rd|LSB:2|0|Width:5" , "ARMv6T2+ IT=ANY"],
["bfc" , "Rd!=PC, #LSB, #Width" , "A32", "Cond|011|1110|Width:5|Rd|LSB:5|001|1111" , "ARMv6T2+"],
["bfi" , "Rd!=XX, Rn!=XX, #LSB, #Width" , "T32", "1111|001|1011|0|Rn|0|LSB:3|Rd|LSB:2|0|Width:5" , "ARMv6T2+ IT=ANY"],
["bfi" , "Rd!=PC, Rn!=PC, #LSB, #Width" , "A32", "Cond|011|1110|Width:5|Rd|LSB:5|001|Rn" , "ARMv6T2+"],
["bic" , "Rd!=XX, Rn!=XX, #ImmC" , "T32", "1111|0|ImmC:1|0|0001|0|Rn|0|ImmC:3|Rd|ImmC:8" , "ARMv6T2+ IT=ANY"],
["bicS" , "Rd!=XX, Rn!=XX, #ImmC" , "T32", "1111|0|ImmC:1|0|0001|1|Rn|0|ImmC:3|Rd|ImmC:8" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["bic" , "Rd , Rn , #ImmC" , "A32", "Cond|001|1110|0|Rn|Rd|ImmC:12" , "ARMv4+"],
["bicS" , "Rd!=PC, Rn , #ImmC" , "A32", "Cond|001|1110|1|Rn|Rd|ImmC:12" , "ARMv4+ APSR.NZC=W"],
["bic" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|001|110|Rm:3|Rx:3" , "ARMv4T+ IT=IN"],
["bicS" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|001|110|Rm:3|Rx:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["bic" , "Rd , Rn , Rm , {Sop #Shift}" , "A32", "Cond|000|1110|0|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+"],
["bicS" , "Rd!=PC, Rn , Rm , {Sop #Shift}" , "A32", "Cond|000|1110|1|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+ APSR.NZC=W"],
["bic" , "Rd!=XX, Rn!=XX, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|0001|0|Rn|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY"],
["bicS" , "Rd!=XX, Rn!=XX, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|0001|1|Rn|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["bic" , "Rd!=PC, Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|1110|0|Rn|Rd|Rs|0|Sop:2|1|Rm" , "ARMv4+"],
["bicS" , "Rd!=PC, Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|1110|1|Rn|Rd|Rs|0|Sop:2|1|Rm" , "ARMv4+ APSR.NZC=W"],
["bkpt" , "#ImmZ" , "T16", "1011|111|0|ImmZ:8" , "ARMv5T+ IT=UNCOND"],
["bkpt" , "#ImmZ" , "A32", "Cond|000|1001|0|ImmZ:12|0111|ImmZ:4" , "ARMv6+ ARMv5T"],
["bl" , "#RelS*2" , "T32", "1111|0|RelS[23]|RelS[20:11]|11|Ja|1|Jb|RelS[10:0]" , "ARMv4T+ IT=OUT|LAST"],
["bl" , "#RelS*4" , "A32", "Cond|101|1|RelS:24" , "ARMv4+"],
["blx" , "#RelS*4" , "T32", "1111|0|RelS[22]|RelS[19:10]|11|Ja|0|Jb|RelS[9:0]|0" , "ARMv4T+ IT=OUT|LAST"],
["blx" , "#RelS*2" , "A32", "1111|101|RelS[0]|RelS[24:1]" , "ARMv4+"],
["blx" , "Rm!=PC" , "T16", "0100|011|11|Rm:4|000" , "ARMv5T+ IT=OUT|LAST"],
["blx" , "Rm!=PC" , "A32", "Cond|000|1001|0|1111|1111|1111|0011|Rm" , "ARMv5T+"],
["bx" , "Rm" , "T16", "0100|011|10|Rm:4|000" , "ARMv4T+ IT=OUT|LAST"],
["bx" , "Rm" , "A32", "Cond|000|1001|0|1111|1111|1111|0001|Rm" , "ARMv4T+"],
["bxj" , "Rm!=XX" , "T32", "1111|001|1110|0|Rm|1000|1111|00000000" , "ARMv6T2+ IT=OUT|LAST"],
["bxj" , "Rm!=PC" , "A32", "Cond|000|1001|0|1111|1111|1111|0010|Rm" , "ARMv5TEJ+"],
["cbz" , "Rn!=HI, #RelZ*2" , "T16", "1011|00|RelZ:1|1|RelZ:5|Rn:3" , "ARMv6T2+ IT=OUT"],
["cbnz" , "Rn!=HI, #RelZ*2" , "T16", "1011|10|RelZ:1|1|RelZ:5|Rn:3" , "ARMv6T2+ IT=OUT"],
["clrex" , "" , "T32", "1111|001|1101|1|1111|1000|1111|0010|1111" , "ARMv7+ IT=ANY"],
["clrex" , "" , "A32", "1111|010|1011|1|1111|1111|0000|0001|1111" , "ARMv7+ ARMv6K"],
["clz" , "Rd!=XX, Rn!=XX" , "T32", "1111|101|0101|1|Rm|1111|Rd|1000|Rn" , "ARMv6T2+ IT=ANY"],
["clz" , "Rd!=PC, Rn!=PC" , "A32", "Cond|000|1011|0|1111|Rd|1111|0001|Rn" , "ARMv6+ ARMv5T"],
["cmn" , "Rn!=PC, #ImmA" , "T32", "1111|0|ImmA:1|0|1000|1|Rn|0|ImmA:3|1111|ImmA:8" , "ARMv6T2+ IT=ANY APSR.NZCV=W"],
["cmn" , "Rn , #ImmA" , "A32", "Cond|001|1011|1|Rn|0000|ImmA:12" , "ARMv4+ APSR.NZCV=W"],
["cmn" , "Rn!=HI, Rm!=HI" , "T16", "0100|001|011|Rm:3|Rn:3" , "ARMv4T+ IT=ANY APSR.NZCV=W"],
["cmn" , "Rn!=PC, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|1000|1|Rn|0|Shift:3|1111|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY APSR.NZCV=W"],
["cmn" , "Rn , Rm , {Sop #Shift}" , "A32", "Cond|000|1011|1|Rn|0000|Shift:5|Sop:2|0|Rm" , "ARMv4+ APSR.NZCV=W"],
["cmn" , "Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|1011|1|Rn|0000|Rs|0|Sop:2|1|Rm" , "ARMv4+ APSR.NZCV=W"],
["cmp" , "Rn!=HI, #ImmZ" , "T16", "0010|1|Rn:3|ImmZ:8" , "ARMv4T+ IT=ANY APSR.NZCV=W"],
["cmp" , "Rn!=PC, #ImmA" , "T32", "1111|0|ImmA:1|0|1101|1|Rn|0|ImmA:3|1111|ImmA:8" , "ARMv6T2+ IT=ANY APSR.NZCV=W"],
["cmp" , "Rn , #ImmA" , "A32", "Cond|001|1010|1|Rn|0000|ImmA:12" , "ARMv4+ APSR.NZCV=W"],
["cmp" , "Rn!=HI, Rm!=HI" , "T16", "0100|001|010|Rm:3|Rn:3" , "ARMv4T+ IT=ANY APSR.NZCV=W"],
["cmp" , "Rn!=PC, Rm!=PC" , "T16", "0100|010|1|Rn:1|Rm:4|Rn:3" , "ARMv4T+ IT=ANY APSR.NZCV=W UNPRED_IF_ALL_LOW"],
["cmp" , "Rn!=PC, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|1101|1|Rn|0|Shift:3|1111|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY APSR.NZCV=W"],
["cmp" , "Rn , Rm , {Sop #Shift}" , "A32", "Cond|000|1010|1|Rn|0000|Shift:5|Sop:2|0|Rm" , "ARMv4+ APSR.NZCV=W"],
["cmp" , "Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|1010|1|Rn|0000|Rs|0|Sop:2|1|Rm" , "ARMv4+ APSR.NZCV=W"],
["cps" , "#ImmZ" , "A32", "1111|000|1000|0|0010|0000|000|000|0|ImmZ:5" , "?"],
["cpsid" , "#AIF" , "A32", "1111|000|1000|0|1100|0000|000|AIF:3|0|00000" , "?"],
["cpsid" , "#AIF, #ImmZ" , "A32", "1111|000|1000|0|1110|0000|000|AIF:3|0|ImmZ:5" , "?"],
["cpsie" , "#AIF" , "A32", "1111|000|1000|0|1000|0000|000|AIF:3|0|00000" , "?"],
["cpsie" , "#AIF, #ImmZ" , "A32", "1111|000|1000|0|1010|0000|000|AIF:3|0|ImmZ:5" , "?"],
["crc32b" , "Rd!=PC, Rn!=PC, Rm!=PC" , "T32", "1111|101|0110|0|Rn|1111|Rd|10|00|Rm" , "CRC32 IT=OUT"],
["crc32b" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1000|0|Rn|Rd|0000|0100|Rm" , "CRC32"],
["crc32h" , "Rd!=PC, Rn!=PC, Rm!=PC" , "T32", "1111|101|0110|0|Rn|1111|Rd|10|01|Rm" , "CRC32 IT=OUT"],
["crc32h" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1001|0|Rn|Rd|0000|0100|Rm" , "CRC32"],
["crc32w" , "Rd!=PC, Rn!=PC, Rm!=PC" , "T32", "1111|101|0110|0|Rn|1111|Rd|10|10|Rm" , "CRC32 IT=OUT"],
["crc32w" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1010|0|Rn|Rd|0000|0100|Rm" , "CRC32"],
["crc32cb" , "Rd!=PC, Rn!=PC, Rm!=PC" , "T32", "1111|101|0110|1|Rn|1111|Rd|10|00|Rm" , "CRC32 IT=OUT"],
["crc32cb" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1000|0|Rn|Rd|0010|0100|Rm" , "CRC32"],
["crc32ch" , "Rd!=PC, Rn!=PC, Rm!=PC" , "T32", "1111|101|0110|1|Rn|1111|Rd|10|01|Rm" , "CRC32 IT=OUT"],
["crc32ch" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1001|0|Rn|Rd|0010|0100|Rm" , "CRC32"],
["crc32cw" , "Rd!=PC, Rn!=PC, Rm!=PC" , "T32", "1111|101|0110|1|Rn|1111|Rd|10|10|Rm" , "CRC32 IT=OUT"],
["crc32cw" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1010|0|Rn|Rd|0010|0100|Rm" , "CRC32"],
["dbg" , "#ImmZ" , "T32", "1111|001|1101|0|1111|1000|0000|1111|ImmZ:4" , "ARMv6T2+ IT=ANY"],
["dbg" , "#ImmZ" , "A32", "Cond|001|1001|0|0000|1111|0000|1111|ImmZ:4" , "ARMv7+ ARMv8-"],
["dmb" , "#ImmZ" , "T32", "1111|001|1101|1|1111|1000|1111|0101|ImmZ:4" , "ARMv7+ IT=ANY"],
["dmb" , "#ImmZ" , "A32", "1111|010|1011|1|1111|1111|0000|0101|ImmZ:4" , "ARMv7+"],
["dsb" , "#ImmZ" , "T32", "1111|001|1101|1|1111|1000|1111|0100|ImmZ:4" , "ARMv7+ IT=ANY"],
["dsb" , "#ImmZ" , "A32", "1111|010|1011|1|1111|1111|0000|0100|ImmZ:4" , "ARMv7+"],
["eor" , "Rd!=XX, Rn!=XX, #ImmC" , "T32", "1111|0|ImmC:1|0|0100|0|Rn|0|ImmC:3|Rd|ImmC:8" , "ARMv6T2+ IT=ANY"],
["eorS" , "Rd!=XX, Rn!=XX, #ImmC" , "T32", "1111|0|ImmC:1|0|0100|1|Rn|0|ImmC:3|Rd|ImmC:8" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["eor" , "Rd , Rn , #ImmC" , "A32", "Cond|001|0001|0|Rn|Rd|ImmC:12" , "ARMv4+"],
["eorS" , "Rd!=PC, Rn , #ImmC" , "A32", "Cond|001|0001|1|Rn|Rd|ImmC:12" , "ARMv4+ APSR.NZC=W"],
["eor" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|000|001|Rm:3|Rx:3" , "ARMv4T+ IT=IN"],
["eorS" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|000|001|Rm:3|Rx:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["eor" , "Rd , Rn , Rm , {Sop #Shift}" , "A32", "Cond|000|0001|0|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+"],
["eorS" , "Rd!=PC, Rn , Rm , {Sop #Shift}" , "A32", "Cond|000|0001|1|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+ APSR.NZC=W"],
["eor" , "Rd!=XX, Rn!=XX, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|0100|0|Rn|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY"],
["eorS" , "Rd!=XX, Rn!=XX, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|0100|1|Rn|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["eor" , "Rd!=PC, Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|0001|0|Rn|Rd|Rs|0|Sop:2|1|Rm" , "ARMv4+"],
["eorS" , "Rd!=PC, Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|0001|1|Rn|Rd|Rs|0|Sop:2|1|Rm" , "ARMv4+ APSR.NZC=W"],
["eret" , "" , "A32", "Cond|000|1011|0|0000|0000|0000|0110|1110" , "?"],
["hlt" , "#ImmZ" , "A32", "Cond|000|1000|0|ImmZ:12|0111|ImmZ:4" , "?"],
["hvc" , "#ImmZ" , "A32", "Cond|000|1010|0|ImmZ:12|0111|ImmZ:4" , "?"],
["isb" , "#ImmZ" , "A32", "1111|010|1011|1|1111|1111|0000|0110|ImmZ:4" , "ARMv7+"],
["it" , "#FirstCond!=15" , "T16", "1011|111|1|FirstCond[3:0]|1000" , "ARMv6T2+ IT=OUT|DEF"],
["ite" , "#FirstCond!=15" , "T16", "1011|111|1|FirstCond[3:0]|X100" , "ARMv6T2+ IT=OUT|DEF"],
["itee" , "#FirstCond!=15" , "T16", "1011|111|1|FirstCond[3:0]|XY10" , "ARMv6T2+ IT=OUT|DEF"],
["iteee" , "#FirstCond!=15" , "T16", "1011|111|1|FirstCond[3:0]|XYZ1" , "ARMv6T2+ IT=OUT|DEF"],
["iteet" , "#FirstCond!=15" , "T16", "1011|111|1|FirstCond[3:0]|XYZ1" , "ARMv6T2+ IT=OUT|DEF"],
["itet" , "#FirstCond!=15" , "T16", "1011|111|1|FirstCond[3:0]|XY10" , "ARMv6T2+ IT=OUT|DEF"],
["itete" , "#FirstCond!=15" , "T16", "1011|111|1|FirstCond[3:0]|XYZ1" , "ARMv6T2+ IT=OUT|DEF"],
["itett" , "#FirstCond!=15" , "T16", "1011|111|1|FirstCond[3:0]|XYZ1" , "ARMv6T2+ IT=OUT|DEF"],
["itt" , "#FirstCond!=15" , "T16", "1011|111|1|FirstCond[3:0]|X100" , "ARMv6T2+ IT=OUT|DEF"],
["itte" , "#FirstCond!=15" , "T16", "1011|111|1|FirstCond[3:0]|XY10" , "ARMv6T2+ IT=OUT|DEF"],
["ittee" , "#FirstCond!=15" , "T16", "1011|111|1|FirstCond[3:0]|XYZ1" , "ARMv6T2+ IT=OUT|DEF"],
["ittet" , "#FirstCond!=15" , "T16", "1011|111|1|FirstCond[3:0]|XYZ1" , "ARMv6T2+ IT=OUT|DEF"],
["ittt" , "#FirstCond!=15" , "T16", "1011|111|1|FirstCond[3:0]|XY10" , "ARMv6T2+ IT=OUT|DEF"],
["ittte" , "#FirstCond!=15" , "T16", "1011|111|1|FirstCond[3:0]|XYZ1" , "ARMv6T2+ IT=OUT|DEF"],
["itttt" , "#FirstCond!=15" , "T16", "1011|111|1|FirstCond[3:0]|XYZ1" , "ARMv6T2+ IT=OUT|DEF"],
["lda" , "Rd!=PC, [Rn!=PC]" , "T32", "1110|100|0110|1|Rn|Rd|1111|1010|1111" , "ARMv8+ IT=ANY"],
["lda" , "Rd!=PC, [Rn!=PC]" , "A32", "Cond|000|1100|1|Rn|Rd|1100|1001|1111" , "ARMv8+"],
["ldab" , "Rd!=PC, [Rn!=PC]" , "T32", "1110|100|0110|1|Rn|Rd|1111|1000|1111" , "ARMv8+ IT=ANY"],
["ldab" , "Rd!=PC, [Rn!=PC]" , "A32", "Cond|000|1110|1|Rn|Rd|1100|1001|1111" , "ARMv8+"],
["ldaex" , "Rd!=PC, [Rn!=PC]" , "T32", "1110|100|0110|1|Rn|Rd|1111|1110|1111" , "ARMv8+ IT=ANY"],
["ldaex" , "Rd!=PC, [Rn!=PC]" , "A32", "Cond|000|1100|1|Rn|Rd|1110|1001|1111" , "ARMv8+"],
["ldaexb" , "Rd!=PC, [Rn!=PC]" , "T32", "1110|100|0110|1|Rn|Rd|1111|1100|1111" , "ARMv8+ IT=ANY"],
["ldaexb" , "Rd!=PC, [Rn!=PC]" , "A32", "Cond|000|1110|1|Rn|Rd|1110|1001|1111" , "ARMv8+"],
["ldaexd" , "Rd!=PC, Rd2!=PC , [Rn!=PC]" , "T32", "1110|100|0110|1|Rn|Rd|Rd2|1111|1111" , "ARMv8+ IT=ANY"],
["ldaexd" , "Rd<=13, Rd2==Rd+1, [Rn!=PC]" , "A32", "Cond|000|1101|1|Rn|Rd|1110|1001|1111" , "ARMv8+"],
["ldaexh" , "Rd!=PC, [Rn!=PC]" , "T32", "1110|100|0110|1|Rn|Rd|1111|1101|1111" , "ARMv8+ IT=ANY"],
["ldaexh" , "Rd!=PC, [Rn!=PC]" , "A32", "Cond|000|1111|1|Rn|Rd|1110|1001|1111" , "ARMv8+"],
["ldah" , "Rd!=PC, [Rn!=PC]" , "T32", "1110|100|0110|1|Rn|Rd|1111|1001|1111" , "ARMv8+ IT=ANY"],
["ldah" , "Rd!=PC, [Rn!=PC]" , "A32", "Cond|000|1111|1|Rn|Rd|1100|1001|1111" , "ARMv8+"],
["ldm" , "[Rn!=HI]{!}, RdList" , "T16", "1100|1|Rn:3|RdList:8" , "ARMv4T+ IT=ANY T16_LDM"],
["ldm" , "[Rn!=PC]{!}, RdList" , "T32", "1110|100|010W|1|Rn|RdList[15:14]|0|RdList[12:0]" , "ARMv6T2+ IT=ANY T32_LDM"],
["ldm" , "[Rn!=PC]{!}, RdList" , "A32", "Cond|100|010W|1|Rn|RdList:16" , "ARMv4+"],
["ldm" , "[Rn!=PC]{!}, RdList" , "A32", "Cond|100|011W|1|Rn|RdList:16" , "ARMv4+"],
["ldmda" , "[Rn!=PC]{!}, RdList" , "A32", "Cond|100|000W|1|Rn|RdList:16" , "ARMv4+"],
["ldmda" , "[Rn!=PC]{!}, RdList" , "A32", "Cond|100|001W|1|Rn|RdList:16" , "ARMv4+"],
["ldmdb" , "[Rn!=PC]{!}, RdList" , "T32", "1110|100|100W|1|Rn|RdList[15:14]|0|RdList[12:0]" , "ARMv6T2+ IT=ANY T32_LDM"],
["ldmdb" , "[Rn!=PC]{!}, RdList" , "A32", "Cond|100|100W|1|Rn|RdList:16" , "ARMv4+"],
["ldmdb" , "[Rn!=PC]{!}, RdList" , "A32", "Cond|100|101W|1|Rn|RdList:16" , "ARMv4+"],
["ldmib" , "[Rn!=PC]{!}, RdList" , "A32", "Cond|100|110W|1|Rn|RdList:16" , "ARMv4+"],
["ldmib" , "[Rn!=PC]{!}, RdList" , "A32", "Cond|100|111W|1|Rn|RdList:16" , "ARMv4+"],
["ldr" , "Rd!=HI, [Rn!=HI, #ImmZ*4]" , "T16", "0110|1|ImmZ:5|Rn:3|Rd:3" , "ARMv4T+ IT=ANY"],
["ldr" , "Rd!=HI, [Rn==SP, #ImmZ*4]" , "T16", "1001|1|Rd:3|ImmZ:8" , "ARMv4T+ IT=ANY"],
["ldr" , "Rd!=HI, [Rn==PC, #ImmZ*4]" , "T16", "0100|1|Rd:3|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["ldr" , "Rd , [Rn!=PC, #ImmZ]" , "T32", "1111|100|0110|1|Rn|Rd|ImmZ:12" , "ARMv6T2+ IT=ANY"],
["ldr" , "Rd , [Rn!=PC, #+/-ImmZ]{!}" , "T32", "1111|100|0010|1|Rn|Rd|1PUW|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["ldr" , "Rd , [Rn==PC, #+/-ImmZ]" , "T32", "1111|100|0U10|1|Rn|Rd|ImmZ:12" , "ARMv6T2+ IT=ANY"],
["ldr" , "Rd , [Rn , #+/-ImmZ]{!}" , "A32", "Cond|010|PU0W|1|Rn|Rd|ImmZ:12" , "ARMv4+"],
["ldr" , "Rd!=HI, [Rn!=HI, Rm!=HI]" , "T16", "0101|100|Rm:3|Rn:3|Rd:3" , "ARMv4T+ IT=ANY"],
["ldr" , "Rd , [Rn!=PC, Rm!=XX, {LSL #Shift}]" , "T32", "1111|100|0010|1|Rn|Rd|0|00000|Shift:2|Rm" , "ARMv6T2+ IT=ANY"],
["ldr" , "Rd , [Rn , +/-Rm!=PC, {Sop #Shift}]{!}", "A32", "Cond|011|PU0W|1|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+"],
["ldrb" , "Rd!=HI, [Rn!=HI, #ImmZ*4]" , "T16", "0111|1|ImmZ:5|Rn:3|Rd:3" , "ARMv4T+ IT=ANY"],
["ldrb" , "Rd!=XX, [Rn!=PC, #ImmZ]" , "T32", "1111|100|0100|1|Rn|Rd|ImmZ:12" , "ARMv6T2+ IT=ANY"],
["ldrb" , "Rd!=XX, [Rn!=PC, #+/-ImmZ]{!}" , "T32", "1111|100|0000|1|Rn|Rd|1PUW|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["ldrb" , "Rd!=XX, [Rn==PC, #+/-ImmZ]" , "T32", "1111|100|0U00|1|Rn|Rd|ImmZ:12" , "ARMv6T2+ IT=ANY"],
["ldrb" , "Rd!=PC, [Rn , #+/-ImmZ]{!}" , "A32", "Cond|010|PU1W|1|Rn|Rd|ImmZ:12" , "ARMv4+"],
["ldrb" , "Rd!=HI, [Rn!=HI, Rm!=HI]" , "T16", "0101|110|Rm:3|Rn:3|Rd:3" , "ARMv4T+ IT=ANY"],
["ldrb" , "Rd!=XX, [Rn!=PC, Rm!=XX, {LSL #Shift}]" , "T32", "1111|100|0000|1|Rn|Rd|0|00000|Shift:2|Rm" , "ARMv6T2+ IT=ANY"],
["ldrb" , "Rd!=PC, [Rn , +/-Rm!=PC, {Sop #Shift}]{!}", "A32", "Cond|011|PU1W|1|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+"],
["ldrbt" , "Rd!=XX, [Rn!=PC, #ImmZ]" , "T32", "1111|100|0000|1|Rn|Rd|1110|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["ldrbt" , "Rd!=PC, [Rn!=PC, #+/-ImmZ]!" , "A32", "Cond|010|0U11|1|Rn|Rd|ImmZ:12" , "ARMv4+"],
["ldrbt" , "Rd!=PC, [Rn!=PC, +/-Rm!=PC, {Sop #Shift}]!" , "A32", "Cond|011|0U11|1|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+"],
["ldrd" , "Rd!=XX, Rd2!=XX , [Rn!=PC, #+/-ImmZ*4]{!}" , "T32", "1110|100|PU1W|1|Rn|Rd|Rd2|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["ldrd" , "Rd!=XX, Rd2!=XX , [Rn==PC, #+/-ImmZ*4]" , "T32", "1110|100|PU10|1|Rn|Rd|Rd2|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["ldrd" , "Rd<=13, Rd2==Rd+1, [Rn , #+/-ImmZ]{!}" , "A32", "Cond|000|PU1W|0|Rn|Rd|ImmZ:4|1101|ImmZ:4" , "ARMv5TE+"],
["ldrd" , "Rd<=13, Rd2==Rd+1, [Rn , +/-Rm]{!}" , "A32", "Cond|000|PU0W|0|Rn|Rd|0000|1101|Rm" , "ARMv5TE+"],
["ldrex" , "Rd!=XX, [Rn!=PC, #ImmZ*4]" , "T32", "1110|100|0010|1|Rn|Rd|1111|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["ldrex" , "Rd!=PC, [Rn!=PC]" , "A32", "Cond|000|1100|1|Rn|Rd|1111|1001|1111" , "ARMv6+"],
["ldrexb" , "Rd!=XX, [Rn!=PC]" , "T32", "1110|100|0110|1|Rn|Rd|1111|0100|1111" , "ARMv7+ IT=ANY"],
["ldrexb" , "Rd!=PC, [Rn!=PC]" , "A32", "Cond|000|1110|1|Rn|Rd|1111|1001|1111" , "ARMv6K+"],
["ldrexd" , "Rd!=XX, Rd2!=XX , [Rn!=PC]" , "T32", "1110|100|0110|1|Rn|Rd|Rd2 |0111|1111" , "ARMv7+ IT=ANY"],
["ldrexd" , "Rd<=13, Rd2==Rd+1, [Rn!=PC]" , "A32", "Cond|000|1101|1|Rn|Rd|1111|1001|1111" , "ARMv6K+"],
["ldrexh" , "Rd!=XX, [Rn!=PC]" , "T32", "1110|100|0110|1|Rn|Rd|1111|0101|1111" , "ARMv7+ IT=ANY"],
["ldrexh" , "Rd!=PC, [Rn!=PC]" , "A32", "Cond|000|1111|1|Rn|Rd|1111|1001|1111" , "ARMv6K+"],
["ldrh" , "Rd!=HI, [Rn!=HI, #ImmZ*4]" , "T16", "1000|1|ImmZ:5|Rn:3|Rd:3" , "ARMv4T+ IT=ANY"],
["ldrh" , "Rd!=XX, [Rn!=PC, #ImmZ]" , "T32", "1111|100|0101|1|Rn|Rd|ImmZ:12" , "ARMv6T2+ IT=ANY"],
["ldrh" , "Rd!=XX, [Rn!=PC, #+/-ImmZ]{!}" , "T32", "1111|100|0001|1|Rn|Rd|1PUW|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["ldrh" , "Rd!=XX, [Rn==PC, #+/-ImmZ]" , "T32", "1111|100|0U01|1|Rn|Rd|ImmZ:12" , "ARMv6T2+ IT=ANY"],
["ldrh" , "Rd!=PC, [Rn , #+/-ImmZ]{!}" , "A32", "Cond|000|PU1W|1|Rn|Rd|ImmZ:4|1011|ImmZ:4" , "ARMv4+"],
["ldrh" , "Rd!=HI, [Rn!=HI, Rm!=HI]" , "T16", "0101|101|Rm:3|Rn:3|Rd:3" , "ARMv4T+ IT=ANY"],
["ldrh" , "Rd!=PC, [Rn , +/-Rm!=PC]{!}" , "A32", "Cond|000|PU0W|1|Rn|Rd|0000|1011|Rm" , "ARMv4+"],
["ldrh" , "Rd!=XX, [Rn!=PC, Rm!=XX, {LSL #Shift}]" , "T32", "1111|100|0001|1|Rn|Rd|0|00000|Shift:2|Rm" , "ARMv6T2+ IT=ANY"],
["ldrht" , "Rd!=XX, [Rn!=PC, #ImmZ]" , "T32", "1111|100|0001|1|Rn|Rd|1110|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["ldrht" , "Rd!=PC, [Rn!=PC, #+/-ImmZ]!" , "A32", "Cond|000|0U11|1|Rn|Rd|ImmZ:4|1011|ImmZ:4" , "ARMv6T2+"],
["ldrht" , "Rd!=PC, [Rn!=PC, +/-Rm!=PC]!" , "A32", "Cond|000|0U01|1|Rn|Rd|0000|1011|Rm" , "ARMv6T2+"],
["ldrsb" , "Rd!=XX, [Rn!=PC, #ImmZ]" , "T32", "1111|100|1100|1|Rn|Rd|ImmZ:12" , "ARMv6T2+ IT=ANY"],
["ldrsb" , "Rd!=XX, [Rn!=PC, #+/-ImmZ]{!}" , "T32", "1111|100|1000|1|Rn|Rd|1PUW|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["ldrsb" , "Rd!=XX, [Rn==PC, #+/-ImmZ]" , "T32", "1111|100|1U00|1|Rn|Rd|ImmZ:12" , "ARMv6T2+ IT=ANY"],
["ldrsb" , "Rd!=PC, [Rn , #+/-ImmZ]{!}" , "A32", "Cond|000|PU1W|1|Rn|Rd|ImmZ:4|1101|ImmZ:4" , "ARMv4+"],
["ldrsb" , "Rd!=HI, [Rn!=HI, Rm!=HI]" , "T16", "0101|011|Rm:3|Rn:3|Rd:3" , "ARMv4T+ IT=ANY"],
["ldrsb" , "Rd!=XX, [Rn!=PC, Rm!=XX, {LSL #Shift}]" , "T32", "1111|100|1000|1|Rn|Rd|0|00000|Shift:2|Rm" , "ARMv6T2+ IT=ANY"],
["ldrsb" , "Rd!=PC, [Rn!=PC, +/-Rm!=PC]{!}" , "A32", "Cond|000|PU0W|1|Rn|Rd|0000|1101|Rm" , "ARMv4+"],
["ldrsbt" , "Rd!=XX, [Rn!=PC, #ImmZ]" , "T32", "1111|100|1000|1|Rn|Rd|1110|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["ldrsbt" , "Rd!=PC, [Rn!=PC, #+/-ImmZ]!" , "A32", "Cond|000|0U11|1|Rn|Rd|ImmZ:4|1011|ImmZ:4" , "ARMv6T2+"],
["ldrsbt" , "Rd!=PC, [Rn!=PC, +/-Rm]!" , "A32", "Cond|000|0U01|1|Rn|Rd|0000|1011|Rm" , "ARMv6T2+"],
["ldrsh" , "Rd!=XX, [Rn!=PC, #ImmZ]" , "T32", "1111|100|1101|1|Rn|Rd|ImmZ:12" , "ARMv6T2+ IT=ANY"],
["ldrsh" , "Rd!=XX, [Rn!=PC, #+/-ImmZ]{!}" , "T32", "1111|100|1001|1|Rn|Rd|1PUW|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["ldrsh" , "Rd!=XX, [Rn==PC, #+/-ImmZ]" , "T32", "1111|100|1U01|1|Rn|Rd|ImmZ:12" , "ARMv6T2+ IT=ANY"],
["ldrsh" , "Rd!=PC, [Rn , #+/-ImmZ]{!}" , "A32", "Cond|000|PU1W|1|Rn|Rd|ImmZ:4|1111|ImmZ:4" , "ARMv4+"],
["ldrsh" , "Rd!=HI, [Rn!=HI, Rm!=HI]" , "T16", "0101|111|Rm:3|Rn:3|Rd:3" , "ARMv4T+ IT=ANY"],
["ldrsh" , "Rd!=XX, [Rn!=PC, Rm!=XX, {LSL #Shift}]" , "T32", "1111|100|1001|1|Rn|Rd|0|00000|Shift:2|Rm" , "ARMv6T2+ IT=ANY"],
["ldrsh" , "Rd!=PC, [Rn , +/-Rm!=PC]{!}" , "A32", "Cond|000|PU0W|1|Rn|Rd|0000|1111|Rm" , "ARMv4+"],
["ldrsht" , "Rd!=XX, [Rn!=PC, #ImmZ]" , "T32", "1111|100|1001|1|Rn|Rd|1110|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["ldrsht" , "Rd!=PC, [Rn!=PC, #+/-ImmZ]!" , "A32", "Cond|000|0U11|1|Rn|Rd|ImmZ:4|1111|ImmZ:4" , "ARMv6T2+"],
["ldrsht" , "Rd!=PC, [Rn!=PC, +/-Rm!=PC]!" , "A32", "Cond|000|0U01|1|Rn|Rd|0000|1111|Rm" , "ARMv6T2+"],
["ldrt" , "Rd!=XX, [Rn!=PC, #ImmZ]" , "T32", "1111|100|0010|1|Rn|Rd|1110|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["ldrt" , "Rd!=PC, [Rn!=PC, #+/-ImmZ]!" , "A32", "Cond|010|0U01|1|Rn|Rd|ImmZ:12" , "ARMv4+"],
["ldrt" , "Rd!=PC, [Rn!=PC, +/-Rm!=PC, {Sop #Shift}]!" , "A32", "Cond|011|0U01|1|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+"],
["lsl" , "Rd!=HI, Rn!=HI, #Shift" , "T16", "0000|0|Shift:5|Rn:3|Rd:3" , "ARMv4T+ IT=IN"],
["lslS" , "Rd!=HI, Rn!=HI, #Shift" , "T16", "0000|0|Shift:5|Rn:3|Rd:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["lsl" , "Rd!=XX, Rn!=XX, #Shift" , "T32", "1110|101|0010|0|1111|0|Shift:3|Rd|Shift:2|00|Rn" , "ARMv6T2+ IT=ANY"],
["lslS" , "Rd!=XX, Rn!=XX, #Shift" , "T32", "1110|101|0010|1|1111|0|Shift:3|Rd|Shift:2|00|Rn" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["lsl" , "Rd , Rn , #Shift" , "A32", "Cond|000|1101|0|0000|Rd|Shift:5|000|Rn" , "ARMv4+"],
["lslS" , "Rd , Rn , #Shift" , "A32", "Cond|000|1101|1|0000|Rd|Shift:5|000|Rn" , "ARMv4+ APSR.NZC=W"],
["lsl" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|000|010|Rm:3|Rx:3" , "ARMv4T+ IT=IN"],
["lslS" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|000|010|Rm:3|Rx:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["lsl" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0000|0|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY"],
["lslS" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1110|101|0000|1|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY"],
["lsl" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1101|0|0000|Rd|Rm|0001|Rn" , "ARMv4+"],
["lslS" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1101|1|0000|Rd|Rm|0001|Rn" , "ARMv4+ APSR.NZC=W"],
["lsr" , "Rd!=HI, Rn!=HI, #Shift" , "T16", "0000|1|Shift:5|Rn:3|Rd:3" , "ARMv4T+ IT=IN"],
["lsrS" , "Rd!=HI, Rn!=HI, #Shift" , "T16", "0000|1|Shift:5|Rn:3|Rd:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["lsr" , "Rd!=XX, Rn!=XX, #Shift" , "T32", "1110|101|0010|0|1111|0|Shift:3|Rd|Shift:2|01|Rn" , "ARMv6T2+ IT=ANY"],
["lsrS" , "Rd!=XX, Rn!=XX, #Shift" , "T32", "1110|101|0010|1|1111|0|Shift:3|Rd|Shift:2|01|Rn" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["lsr" , "Rd , Rn , #Shift" , "A32", "Cond|000|1101|0|0000|Rd|Shift:5|010|Rn" , "ARMv4+"],
["lsrS" , "Rd , Rn , #Shift" , "A32", "Cond|000|1101|1|0000|Rd|Shift:5|010|Rn" , "ARMv4+ APSR.NZC=W"],
["lsr" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|000|011|Rm:3|Rx:3" , "ARMv4T+ IT=IN"],
["lsrS" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|000|011|Rm:3|Rx:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["lsr" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0001|0|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY"],
["lsrS" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1110|101|0001|1|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY"],
["lsr" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1101|0|0000|Rd|Rm|0011|Rn" , "ARMv4+"],
["lsrS" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1101|1|0000|Rd|Rm|0011|Rn" , "ARMv4+ APSR.NZC=W"],
["isb" , "#ImmZ" , "T32", "1111|001|1101|1|1111|1000|1111|0110|ImmZ:4" , "ARMv7+ IT=ANY"],
["mcr" , "#CP, #Op1, Rs!=XX, Cn, Cm, {#Op2}" , "T32", "1110|111|0|Op1:3|0|Cn:4|Rs|CP:4|Op2:3|1|Cm:4" , "ARMv6T2+"],
["mcr" , "#CP, #Op1, Rs!=PC, Cn, Cm, {#Op2}" , "A32", "Cond|111|0|Op1:3|0|Cn:4|Rs|CP:4|Op2:3|1|Cm:4" , "ARMv4+"],
["mcr2" , "#CP, #Op1, Rs!=XX, Cn, Cm, {#Op2}" , "T32", "1111|111|0|Op1:3|0|Cn:4|Rs|CP:4|Op2:3|1|Cm:4" , "ARMv6T2+"],
["mcr2" , "#CP, #Op1, Rs!=PC, Cn, Cm, {#Op2}" , "A32", "1111|111|0|Op1:3|0|Cn:4|Rs|CP:4|Op2:3|1|Cm:4" , "ARMv4+"],
["mcrr" , "#CP, #Op1, Rs!=XX, Rs2!=XX, Cm" , "T32", "1110|110|0010|0|Rs2|Rs|CP:4|Op1:4|Cm:4" , "ARMv6T2+"],
["mcrr" , "#CP, #Op1, Rs!=PC, Rs2!=PC, Cm" , "A32", "Cond|110|0010|0|Rs2|Rs|CP:4|Op1:4|Cm:4" , "ARMv5TE+"],
["mcrr2" , "#CP, #Op1, Rs!=XX, Rs2!=XX, Cm" , "T32", "1111|110|0010|0|Rs2|Rs|CP:4|Op1:4|Cm:4" , "ARMv6T2+"],
["mcrr2" , "#CP, #Op1, Rs!=PC, Rs2!=PC, Cm" , "A32", "1111|110|0010|0|Rs2|Rs|CP:4|Op1:4|Cm:4" , "ARMv5TE+"],
["mla" , "Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "T32", "1111|101|1000|0|Rn|Ra|Rd|0000|Rm" , "ARMv6T2+ IT=ANY"],
["mla" , "Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "A32", "Cond|000|0001|0|Rd|Ra|Rm|1001|Rn" , "ARMv4+"],
["mlaS" , "Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "A32", "Cond|000|0001|1|Rd|Ra|Rm|1001|Rn" , "ARMv4+ APSR.NZ=W"],
["mls" , "Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "T32", "1111|101|1000|0|Rn|Ra|Rd|0001|Rm" , "ARMv6T2+ IT=ANY"],
["mls" , "Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "A32", "Cond|000|0011|0|Rd|Ra|Rm|1001|Rn" , "ARMv6T2+"],
["mov" , "Rd!=HI, #ImmZ" , "T16", "0010|0|Rd:3|ImmZ:8" , "ARMv4T+ IT=IN"],
["movS" , "Rd!=HI, #ImmZ" , "T16", "0010|0|Rd:3|ImmZ:8" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["mov" , "Rd!=XX, #ImmC" , "T32", "1111|0|ImmC:1|0|0010|0|1111|0|ImmC:3|Rd|ImmC:8" , "ARMv6T2+ IT=ANY"],
["movS" , "Rd!=XX, #ImmC" , "T32", "1111|0|ImmC:1|0|0010|1|1111|0|ImmC:3|Rd|ImmC:8" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["mov" , "Rd , #ImmC" , "A32", "Cond|001|1101|0|0000|Rd|ImmC:12" , "ARMv4+"],
["movS" , "Rd!=PC, #ImmC" , "A32", "Cond|001|1101|1|0000|Rd|ImmC:12" , "ARMv4+ APSR.NZC=W"],
["mov" , "Rd , Rn" , "T16", "0100|0110|Rd:1|Rn:4|Rd:3" , "ARMv4T+ IT=IN ARMv6T2_IF_LOW"],
["movS" , "Rd!=HI, Rn!=HI" , "T16", "0000|000000|Rn:3|Rd:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["mov" , "Rd!=PC, Rn" , "T32", "1110|101|0010|0|1111|0000|Rd|0000|Rn" , "ARMv6T2+ IT=ANY UNPRED_COMPLEX"],
["movS" , "Rd!=XX, Rn" , "T32", "1110|101|0010|1|1111|0000|Rd|0000|Rn" , "ARMv6T2+ IT=ANY UNPRED_COMPLEX"],
["mov" , "Rd!=HI, Rn!=HI, LSL #Shift" , "T16", "0000|0|Shift:5|Rn:3|Rd:3" , "ARMv4T+ IT=IN"],
["movS" , "Rd!=HI, Rn!=HI, LSL #Shift" , "T16", "0000|0|Shift:5|Rn:3|Rd:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["mov" , "Rd!=HI, Rn!=HI, LSR #Shift" , "T16", "0000|1|Shift:5|Rn:3|Rd:3" , "ARMv4T+ IT=IN"],
["movS" , "Rd!=HI, Rn!=HI, LSR #Shift" , "T16", "0000|1|Shift:5|Rn:3|Rd:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["mov" , "Rd!=HI, Rn!=HI, ASR #Shift" , "T16", "0001|0|Shift:5|Rn:3|Rd:3" , "ARMv4T+ IT=IN"],
["movS" , "Rd!=HI, Rn!=HI, ASR #Shift" , "T16", "0001|0|Shift:5|Rn:3|Rd:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["mov" , "Rd!=XX, Rn!=XX, Sop #Shift" , "T32", "1110|101|0010|0|1111|0|Shift:3|Rd|Shift:2|Sop:2|Rn" , "ARMv6T2+ IT=ANY"],
["movS" , "Rd!=XX, Rn!=XX, Sop #Shift" , "T32", "1110|101|0010|1|1111|0|Shift:3|Rd|Shift:2|Sop:2|Rn" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["mov" , "Rx!=HI, Rx!=HI, LSL Rm!=HI" , "T16", "0100|000|010|Rm:3|Rx:3" , "ARMv4T+ IT=IN"],
["movS" , "Rx!=HI, Rx!=HI, LSL Rm!=HI" , "T16", "0100|000|010|Rm:3|Rx:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["mov" , "Rx!=HI, Rx!=HI, LSR Rm!=HI" , "T16", "0100|000|011|Rm:3|Rx:3" , "ARMv4T+ IT=IN"],
["movS" , "Rx!=HI, Rx!=HI, LSR Rm!=HI" , "T16", "0100|000|011|Rm:3|Rx:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["mov" , "Rx!=HI, Rx!=HI, ASR Rm!=HI" , "T16", "0100|000|100|Rm:3|Rx:3" , "ARMv4T+ IT=IN"],
["movS" , "Rx!=HI, Rx!=HI, ASR Rm!=HI" , "T16", "0100|000|100|Rm:3|Rx:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["mov" , "Rx!=HI, Rx!=HI, ROR Rm!=HI" , "T16", "0100|000|111|Rm:3|Rx:3" , "ARMv4T+ IT=IN"],
["movS" , "Rx!=HI, Rx!=HI, ROR Rm!=HI" , "T16", "0100|000|111|Rm:3|Rx:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["mov" , "Rd!=XX, Rn!=XX, Sop Rm!=XX" , "T32", "1111|101|00|Sop:2|0|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY"],
["movS" , "Rd!=XX, Rn!=XX, Sop Rm!=XX" , "T32", "1110|101|00|Sop:2|1|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["mov" , "Rd , Rn , {Sop #Shift}" , "A32", "Cond|000|1101|0|0000|Rd|Shift:5|Sop:2|0|Rn" , "ARMv4+"],
["movS" , "Rd!=PC, Rn , {Sop #Shift}" , "A32", "Cond|000|1101|1|0000|Rd|Shift:5|Sop:2|0|Rn" , "ARMv4+ APSR.NZC=W"],
["mov" , "Rd , Rn , Sop Rs" , "A32", "Cond|000|1101|0|0000|Rd|Rs|0|Sop:2|1|Rn" , "ARMv4+"],
["movS" , "Rd!=PC, Rn , Sop Rs" , "A32", "Cond|000|1101|1|0000|Rd|Rs|0|Sop:2|1|Rn" , "ARMv4+ APSR.NZC=W"],
["movt" , "Rx!=XX, #ImmZ" , "T32", "1111|0|ImmZ:1|1|0110|0|ImmZ:4|0|ImmZ:3|Rx|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["movt" , "Rx!=PC, #ImmZ" , "A32", "Cond|001|1010|0|ImmZ:4|Rx|ImmZ:12" , "ARMv6T2+"],
["movw" , "Rd!=XX, #ImmZ" , "T32", "1111|0|ImmZ:1|1|0010|0|ImmZ:4|0|ImmZ:3|Rd|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["movw" , "Rd!=PC, #ImmZ" , "A32", "Cond|001|1000|0|ImmZ:4|Rd|ImmZ:12" , "ARMv6T2+"],
["mrc" , "#CP, #Op1, Rd!=XX, Cn, Cm, {#Op2}" , "T32", "1110|111|0|Op1:3|1|Cn:4|Rd|CP:4|Op2:3|1|Cm:4" , "ARMv4+"],
["mrc" , "#CP, #Op1, Rd!=PC, Cn, Cm, {#Op2}" , "A32", "Cond|111|0|Op1:3|1|Cn:4|Rd|CP:4|Op2:3|1|Cm:4" , "ARMv4+"],
["mrc2" , "#CP, #Op1, Rd!=XX, Cn, Cm, {#Op2}" , "T32", "1111|111|0|Op1:3|1|Cn:4|Rd|CP:4|Op2:3|1|Cm:4" , "ARMv4+"],
["mrc2" , "#CP, #Op1, Rd!=PC, Cn, Cm, {#Op2}" , "A32", "1111|111|0|Op1:3|1|Cn:4|Rd|CP:4|Op2:3|1|Cm:4" , "ARMv4+"],
["mrrc" , "#CP, #Op1, Rd!=XX, Rd2!=Rd, Cm" , "T32", "1110|110|0010|1|Rd2|Rd|CP:4|Op1:4|Cm:4" , "ARMv5TE+"],
["mrrc" , "#CP, #Op1, Rd!=PC, Rd2!=Rd, Cm" , "A32", "Cond|110|0010|1|Rd2|Rd|CP:4|Op1:4|Cm:4" , "ARMv5TE+"],
["mrrc2" , "#CP, #Op1, Rd!=XX, Rd2!=Rd, Cm" , "T32", "1111|110|0010|1|Rd2|Rd|CP:4|Op1:4|Cm:4" , "ARMv5TE+"],
["mrrc2" , "#CP, #Op1, Rd!=PC, Rd2!=Rd, Cm" , "A32", "1111|110|0010|1|Rd2|Rd|CP:4|Op1:4|Cm:4" , "ARMv5TE+"],
["mrs" , "Rd!=XX, #APSR" , "T32", "1111|001|1111|0|1111|1000|Rd|0000|0000" , "ARMv6T2+ IT=ANY"],
["mrs" , "Rd!=PC, #APSR" , "A32", "Cond|000|1000|0|1111|Rd|0000|0000|0000" , "ARMv4+"],
["msr" , "#APSR, #ImmA" , "A32", "Cond|001|1001|0|APSR:2|00|1111|ImmA:12" , "ARMv4+"],
["msr" , "#APSR, Rn!=PC" , "T32", "1111|001|1100|0|Rn|1100|APSR:2|00|0000|0000" , "ARMv6T2+ IT=ANY"],
["msr" , "#APSR, Rn!=PC" , "A32", "Cond|000|1001|0|APSR:2|00|1111|0000|0000|Rn" , "ARMv4+"],
["mul" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|001|101|Rm:3|Rx:3" , "ARMv4T+ IT=IN"],
["mulS" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|001|101|Rm:3|Rx:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["mul" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1000|0|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY"],
["mul" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|0000|0|Rd|0000|Rm|1001|Rn" , "ARMv4+"],
["mulS" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|0000|1|Rd|0000|Rm|1001|Rn" , "ARMv4+"],
["mvn" , "Rd!=XX, #ImmC" , "T32", "1111|0|ImmC:1|0|0011|0|1111|0|ImmC:3|Rd|ImmC:8" , "ARMv6T2+ IT=ANY"],
["mvnS" , "Rd!=XX, #ImmC" , "T32", "1111|0|ImmC:1|0|0011|1|1111|0|ImmC:3|Rd|ImmC:8" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["mvn" , "Rd , #ImmC" , "A32", "Cond|001|1111|0|0000|Rd|ImmC:12" , "ARMv4+"],
["mvnS" , "Rd!=PC, #ImmC" , "A32", "Cond|001|1111|1|0000|Rd|ImmC:12" , "ARMv4+ APSR.NZC=W"],
["mvn" , "Rd!=HI, Rn!=HI" , "T16", "0100|001|111|Rn:3|Rd:3" , "ARMv4T+ IT=IN"],
["mvnS" , "Rd!=HI, Rn!=HI" , "T16", "0100|001|111|Rn:3|Rd:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["mvn" , "Rd!=XX, Rn!=XX, {Sop #Shift}" , "T32", "1110|101|0011|0|1111|0|Shift:3|Rd|Shift:2|Sop:2|Rn" , "ARMv6T2+ IT=ANY"],
["mvnS" , "Rd!=XX, Rn!=XX, {Sop #Shift}" , "T32", "1110|101|0011|1|1111|0|Shift:3|Rd|Shift:2|Sop:2|Rn" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["mvn" , "Rd , Rn , {Sop #Shift}" , "A32", "Cond|000|1111|0|0000|Rd|Shift:5|Sop:2|0|Rn" , "ARMv4+"],
["mvnS" , "Rd!=PC, Rn , {Sop #Shift}" , "A32", "Cond|000|1111|1|0000|Rd|Shift:5|Sop:2|0|Rn" , "ARMv4+ APSR.NZC=W"],
["mvn" , "Rd!=PC, Rn!=PC, Sop Rs!=PC" , "A32", "Cond|000|1111|0|0000|Rd|Rs|0|Sop:2|1|Rn" , "ARMv4+"],
["mvnS" , "Rd!=PC, Rn!=PC, Sop Rs!=PC" , "A32", "Cond|000|1111|1|0000|Rd|Rs|0|Sop:2|1|Rn" , "ARMv4+ APSR.NZC=W"],
["nop" , "" , "T16", "1011|111|1000|0|0000" , "ARMv6T2+ IT=ANY"],
["nop" , "" , "T32", "1111|001|1101|0|1111|1000|0000|0000|0000" , "ARMv6T2+ IT=ANY"],
["nop" , "" , "A32", "Cond|001|1001|0|0000|1111|0000|0000|0000" , "ARMv6K+"],
["orn" , "Rd!=XX, Rn!=XX, #ImmC" , "T32", "1111|0|ImmC:1|0|0011|0|Rn|0|ImmC:3|Rd|ImmC:8" , "ARMv6T2+ IT=ANY"],
["ornS" , "Rd!=XX, Rn!=XX, #ImmC" , "T32", "1111|0|ImmC:1|0|0011|1|Rn|0|ImmC:3|Rd|ImmC:8" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["orn" , "Rd!=XX, Rn!=XX, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|0011|0|Rn|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY"],
["ornS" , "Rd!=XX, Rn!=XX, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|0011|1|Rn|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["orr" , "Rd!=XX, Rn!=XX, #ImmC" , "T32", "1111|0|ImmC:1|0|0010|0|Rn|0|ImmC:3|Rd|ImmC:8" , "ARMv6T2+ IT=ANY"],
["orrS" , "Rd!=XX, Rn!=XX, #ImmC" , "T32", "1111|0|ImmC:1|0|0010|1|Rn|0|ImmC:3|Rd|ImmC:8" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["orr" , "Rd , Rn , #ImmC" , "A32", "Cond|001|1100|0|Rn|Rd|ImmC:12" , "ARMv4+"],
["orrS" , "Rd!=PC, Rn , #ImmC" , "A32", "Cond|001|1100|1|Rn|Rd|ImmC:12" , "ARMv4+ APSR.NZC=W"],
["orr" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|001|100|Rm:3|Rx:3" , "ARMv4T+ IT=IN"],
["orrS" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|001|100|Rm:3|Rx:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["orr" , "Rd , Rn , Rm , {Sop #Shift}" , "A32", "Cond|000|1100|0|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+"],
["orrS" , "Rd!=PC, Rn , Rm , {Sop #Shift}" , "A32", "Cond|000|1100|1|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+ APSR.NZC=W"],
["orr" , "Rd!=XX, Rn!=XX, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|0010|0|Rn|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY"],
["orrS" , "Rd!=XX, Rn!=XX, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|0010|1|Rn|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["orr" , "Rd!=PC, Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|1100|0|Rn|Rd|Rs|0|Sop:2|1|Rm" , "ARMv4+"],
["orrS" , "Rd!=PC, Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|1100|1|Rn|Rd|Rs|0|Sop:2|1|Rm" , "ARMv4+ APSR.NZC=W"],
["pkhbt" , "Rd!=XX, Rn!=XX, Rm!=XX, {LSL #Shift}" , "T32", "1110|101|0110|0|Rn|0|Shift:3|Rd|Shift:2|00|Rm" , "ARMv6T2+ IT=ANY"],
["pkhbt" , "Rd!=PC, Rn!=PC, Rm!=PC, {LSL #Shift}" , "A32", "Cond|011|0100|0|Rn|Rd|Shift:5|0|01|Rm" , "ARMv6+"],
["pkhtb" , "Rd!=XX, Rn!=XX, Rm!=XX, {ASR #Shift}" , "T32", "1110|101|0110|0|Rn|0|Shift:3|Rd|Shift:2|10|Rm" , "ARMv6T2+ IT=ANY"],
["pkhtb" , "Rd!=PC, Rn!=PC, Rm!=PC, {ASR #Shift}" , "A32", "Cond|011|0100|0|Rn|Rd|Shift:5|1|01|Rm" , "ARMv6+"],
["pld" , "[Rn!=PC, #ImmZ]" , "T32", "1111|100|0100|1|Rn|1111|ImmZ:12" , "ARMv6T2+ IT=ANY"],
["pld" , "[Rn!=PC, #-ImmZ]" , "T32", "1111|100|0000|1|Rn|1111|1100|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["pld" , "[Rn==PC, #+/-ImmZ]" , "T32", "1111|100|0U00|1|1111|1111|ImmZ:12" , "ARMv6T2+ IT=ANY"],
["pld" , "[Rn , #+/-ImmZ]" , "A32", "1111|010|1U10|1|Rn|1111|ImmZ:12" , "ARMv5TE+"],
["pld" , "[Rn!=PC, Rm!=XX, {LSL #Shift}]" , "T32", "1111|100|0000|1|Rn|1111|0000|00|Shift:2|Rm" , "ARMv6T2+ IT=ANY"],
["pld" , "[Rn , +/-Rm!=PC, {Sop #Shift}]" , "A32", "1111|011|1U10|1|Rn|1111|Shift:5|Sop:2|0|Rm" , "ARMv5TE+"],
["pldw" , "[Rn!=PC, #ImmZ]" , "T32", "1111|100|0101|1|Rn|1111|ImmZ:12" , "ARMv6T2+ IT=ANY"],
["pldw" , "[Rn!=PC, #-ImmZ]" , "T32", "1111|100|0001|1|Rn|1111|1100|ImmZ:8" , "ARMv6T2+ IT=ANY"],
["pldw" , "[Rn , #+/-ImmZ]" , "A32", "1111|010|1U00|1|Rn|1111|ImmZ:12" , "ARMv7+ MP"],
["pldw" , "[Rn!=PC, Rm!=XX, {LSL #Shift}]" , "T32", "1111|100|0001|1|Rn|1111|0000|00|Shift:2|Rm" , "ARMv6T2+ IT=ANY"],
["pldw" , "[Rn , +/-Rm!=PC, {Sop #Shift}]" , "A32", "1111|011|1U00|1|Rn|1111|Shift:5|Sop:2|0|Rm" , "ARMv7+ MP"],
["pli" , "[Rn!=PC, #ImmZ]" , "T32", "1111|100|1100|1|Rn|1111|ImmZ:12" , "ARMv7+ IT=ANY"],
["pli" , "[Rn!=PC, #-ImmZ]" , "T32", "1111|100|1000|1|Rn|1111|1100|ImmZ:8" , "ARMv7+ IT=ANY"],
["pli" , "[Rn==PC, #+/-ImmZ]" , "T32", "1111|100|1U00|1|1111|1111|ImmZ:12" , "ARMv7+ IT=ANY"],
["pli" , "[Rn , #+/-ImmZ]" , "A32", "1111|010|0U10|1|Rn|1111|ImmZ:12" , "ARMv7+"],
["pli" , "[Rn!=PC, Rm!=XX, {LSL #Shift}]" , "T32", "1111|100|1000|1|Rn|1111|0000|00|Shift:2|Rm" , "ARMv7+ IT=ANY"],
["pli" , "[Rn , +/-Rm!=PC, {Sop #Shift}]" , "A32", "1111|011|0U10|1|Rn|1111|Shift:5|Sop:2|0|Rm" , "ARMv7+"],
["pop" , "Rd!=SP" , "T32", "1111|100|0010|1|1101|Rd|1011|00000100" , "ARMv6T2+ IT=ANY"],
["pop" , "Rd!=SP" , "A32", "Cond|010|0100|1|1101|Rd|0000|0000|0100" , "ARMv4+"],
["pop" , "RdList" , "T16", "1011|110|RdList[15]|RdList[7:0]" , "ARMv4T+ IT=ANY"],
["pop" , "RdList" , "T32", "1110|100|0101|1|1101|RdList[15:14]|0|RdList[12:0]" , "ARMv6T2+ IT=ANY"],
["pop" , "RdList" , "A32", "Cond|100|0101|1|1101|RdList:16" , "ARMv4+"],
["push" , "Rs!=XX" , "T32", "1111|100|0010|0|1101|Rs|1101|0000|0100" , "ARMv6T2+ IT=ANY"],
["push" , "Rs!=SP" , "A32", "Cond|010|1001|0|1101|Rs|0000|0000|0100" , "ARMv4+"],
["push" , "RsList" , "T16", "1011|010|RsList[14]|RsList[7:0]" , "ARMv4T+ IT=ANY"],
["push" , "RsList" , "T32", "1110|100|0101|0|1101|0|RsList[14]|0|RsList[12:0]" , "ARMv6T2+ IT=ANY"],
["push" , "RsList" , "A32", "Cond|100|1001|0|1101|RsList:16" , "ARMv4+"],
["qadd" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0100|0|Rm|1111|Rd|1000|Rn" , "ARMv6T2+ IT=ANY APSR.Q=X"],
["qadd" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1000|0|Rm|Rd|0000|0101|Rn" , "ARMv5TE+ APSR.Q=X"],
["qadd16" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0100|1|Rm|1111|Rd|0001|Rn" , "ARMv6T2+ IT=ANY"],
["qadd16" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|0001|0|Rn|Rd|1111|0001|Rm" , "ARMv6+"],
["qadd8" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0100|0|Rm|1111|Rd|0001|Rn" , "ARMv6T2+ IT=ANY"],
["qadd8" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|0001|0|Rn|Rd|1111|1001|Rm" , "ARMv6+"],
["qasx" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0101|0|Rm|1111|Rd|0001|Rn" , "ARMv6T2+ IT=ANY"],
["qasx" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|0001|0|Rn|Rd|1111|0011|Rm" , "ARMv6+"],
["qdadd" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0100|0|Rm|1111|Rd|1001|Rn" , "ARMv6T2+ IT=ANY APSR.Q=X"],
["qdadd" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1010|0|Rm|Rd|0000|0101|Rn" , "ARMv5TE+ APSR.Q=X"],
["qdsub" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0100|0|Rm|1111|Rd|1011|Rn" , "ARMv6T2+ IT=ANY APSR.Q=X"],
["qdsub" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1011|0|Rm|Rd|0000|0101|Rn" , "ARMv5TE+ APSR.Q=X"],
["qsax" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0111|0|Rm|1111|Rd|0001|Rn" , "ARMv6T2+ IT=ANY"],
["qsax" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|0001|0|Rn|Rd|1111|0101|Rm" , "ARMv6+"],
["qsub" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0100|0|Rm|1111|Rd|1010|Rn" , "ARMv6T2+ IT=ANY APSR.Q=X"],
["qsub" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1001|0|Rm|Rd|0000|0101|Rn" , "ARMv5TE+ APSR.Q=X"],
["qsub16" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0110|1|Rm|1111|Rd|0001|Rn" , "ARMv6T2+ IT=ANY"],
["qsub16" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|0001|0|Rn|Rd|1111|0111|Rm" , "ARMv6+"],
["qsub8" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0110|0|Rm|1111|Rd|0001|Rn" , "ARMv6T2+ IT=ANY"],
["qsub8" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|0001|0|Rn|Rd|1111|1111|Rm" , "ARMv6+"],
["rbit" , "Rd!=XX, Rn!=XX" , "T32", "1111|101|0100|1|Rm|1111|Rd|1010|Rn" , "ARMv6T2+ IT=ANY"],
["rbit" , "Rd!=PC, Rn!=PC" , "A32", "Cond|011|0111|1|1111|Rd|1111|0011|Rn" , "ARMv6T2+"],
["rev" , "Rd!=HI, Rn!=HI" , "T16", "1011|101|000|Rn:3|Rd:3" , "ARMv6T+ IT=ANY"],
["rev" , "Rd!=XX, Rn!=XX" , "T32", "1111|101|0100|1|Rm|1111|Rd|1000|Rn" , "ARMv6T2+ IT=ANY"],
["rev" , "Rd!=PC, Rn!=PC" , "A32", "Cond|011|0101|1|1111|Rd|1111|0011|Rn" , "ARMv6+"],
["rev16" , "Rd!=HI, Rn!=HI" , "T16", "1011|101|001|Rn:3|Rd:3" , "ARMv6T+ IT=ANY"],
["rev16" , "Rd!=XX, Rn!=XX" , "T32", "1111|101|0100|1|Rm|1111|Rd|1001|Rn" , "ARMv6T2+ IT=ANY"],
["rev16" , "Rd!=PC, Rn!=PC" , "A32", "Cond|011|0101|1|1111|Rd|1111|1011|Rn" , "ARMv6+"],
["revsh" , "Rd!=HI, Rn!=HI" , "T16", "1011|101|011|Rn:3|Rd:3" , "ARMv6T+ IT=ANY"],
["revsh" , "Rd!=XX, Rn!=XX" , "T32", "1111|101|0100|1|Rm|1111|Rd|1011|Rn" , "ARMv6T2+ IT=ANY"],
["revsh" , "Rd!=PC, Rn!=PC" , "A32", "Cond|011|0111|1|1111|Rd|1111|1011|Rn" , "ARMv6+"],
["rfe" , "[Rn!=PC]{!}" , "A32", "1111|100|010|W|1|Rn|0000|1010|0000|0000" , "ARMv6+ CSPR=W"],
["rfeda" , "[Rn!=PC]{!}" , "A32", "1111|100|000|W|1|Rn|0000|1010|0000|0000" , "ARMv6+ CSPR=W"],
["rfedb" , "[Rn!=PC]{!}" , "A32", "1111|100|100|W|1|Rn|0000|1010|0000|0000" , "ARMv6+ CSPR=W"],
["rfeib" , "[Rn!=PC]{!}" , "A32", "1111|100|110|W|1|Rn|0000|1010|0000|0000" , "ARMv6+ CSPR=W"],
["ror" , "Rd!=XX, Rn!=XX, #Shift" , "T32", "1110|101|0010|0|1111|0|Shift:3|Rd|Shift:2|11|Rn" , "ARMv6T2+ IT=ANY"],
["rorS" , "Rd!=XX, Rn!=XX, #Shift" , "T32", "1110|101|0010|1|1111|0|Shift:3|Rd|Shift:2|11|Rn" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["ror" , "Rd , Rn , #Shift" , "A32", "Cond|000|1101|0|0000|Rd|Shift:5|110|Rn" , "ARMv4+"],
["rorS" , "Rd , Rn , #Shift" , "A32", "Cond|000|1101|1|0000|Rd|Shift:5|110|Rn" , "ARMv4+ APSR.NZC=W"],
["ror" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|000|111|Rm:3|Rx:3" , "ARMv4T+ IT=IN"],
["rorS" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|000|111|Rm:3|Rx:3" , "ARMv4T+ IT=OUT APSR.NZC=W"],
["ror" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0011|0|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY"],
["rorS" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0011|1|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["ror" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1101|0|0000|Rd|Rm|0111|Rn" , "ARMv4+"],
["rorS" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1101|1|0000|Rd|Rm|0111|Rn" , "ARMv4+ APSR.NZC=W"],
["rsb" , "Rd!=HI, Rn!=HI, #0" , "T16", "0100|001001|Rn:3|Rd:3" , "ARMv4T+ IT=IN"],
["rsbS" , "Rd!=HI, Rn!=HI, #0" , "T16", "0100|001001|Rn:3|Rd:3" , "ARMv4T+ IT=OUT APSR.NZCV=W"],
["rsb" , "Rd!=XX, Rn!=XX, #ImmA" , "T32", "1111|0|ImmA:1|0|1110|0|Rn|0|ImmA:3|Rd|ImmA:8" , "ARMv6T2+ IT=ANY"],
["rsbS" , "Rd!=XX, Rn!=XX, #ImmA" , "T32", "1111|0|ImmA:1|0|1110|1|Rn|0|ImmA:3|Rd|ImmA:8" , "ARMv6T2+ IT=ANY APSR.NZCV=W"],
["rsb" , "Rd , Rn , #ImmA" , "A32", "Cond|001|0011|0|Rn|Rd|ImmA:12" , "ARMv4+"],
["rsbS" , "Rd!=PC, Rn , #ImmA" , "A32", "Cond|001|0011|1|Rn|Rd|ImmA:12" , "ARMv4+ APSR.NZCV=W"],
["rsb" , "Rd!=XX, Rn!=XX, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|1110|0|Rn|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY"],
["rsbS" , "Rd!=XX, Rn!=XX, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|1110|1|Rn|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY APSR.NZCV=W"],
["rsb" , "Rd , Rn , Rm , {Sop #Shift}" , "A32", "Cond|000|0011|0|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+"],
["rsbS" , "Rd!=PC, Rn , Rm , {Sop #Shift}" , "A32", "Cond|000|0011|1|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+ APSR.NZCV=W"],
["rsb" , "Rd!=PC, Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|0011|0|Rn|Rd|Rs|0|Sop:2|1|Rm" , "ARMv4+"],
["rsbS" , "Rd!=PC, Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|0011|1|Rn|Rd|Rs|0|Sop:2|1|Rm" , "ARMv4+ APSR.NZCV=W"],
["rsc" , "Rd , Rn, #ImmA" , "A32", "Cond|001|0111|0|Rn|Rd|ImmA:12" , "ARMv4+"],
["rscS" , "Rd!=PC, Rn, #ImmA" , "A32", "Cond|001|0111|1|Rn|Rd|ImmA:12" , "ARMv4+ APSR.NZCV=W"],
["rsc" , "Rd , Rn, Rm, {Sop #Shift}" , "A32", "Cond|000|0111|0|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+"],
["rscS" , "Rd!=PC, Rn, Rm, {Sop #Shift}" , "A32", "Cond|000|0111|1|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+ APSR.NZCV=W"],
["rsc" , "Rd!=PC, Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|0111|0|Rn|Rd|Rs|0|Sop:2|1|Rm" , "ARMv4+"],
["rscS" , "Rd!=PC, Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|0111|1|Rn|Rd|Rs|0|Sop:2|1|Rm" , "ARMv4+ APSR.NZCV=W"],
["rrx" , "Rd!=XX, Rn!=XX" , "T32", "1110|101|0010|0|1111|0000|Rd|0011|Rn" , "ARMv6T2+ IT=ANY"],
["rrxS" , "Rd!=XX, Rn!=XX" , "T32", "1110|101|0010|1|1111|0000|Rd|0011|Rn" , "ARMv6T2+ IT=ANY APSR.NZC=W"],
["rrx" , "Rd , Rn" , "A32", "Cond|000|1101|0|0000|Rd|00000|110|Rn" , "ARMv4+"],
["rrxS" , "Rd , Rn" , "A32", "Cond|000|1101|1|0000|Rd|00000|110|Rn" , "ARMv4+ APSR.NZ=W APSR.C=X"],
["sadd16" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0100|1|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY APSR.GE=W"],
["sadd16" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|0000|1|Rn|Rd|1111|0001|Rm" , "ARMv6+ APSR.GE=W"],
["sadd8" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0100|0|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY APSR.GE=W"],
["sadd8" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|0000|1|Rn|Rd|1111|1001|Rm" , "ARMv6+ APSR.GE=W"],
["sasx" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0101|0|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY APSR.GE=W"],
["sasx" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|0000|1|Rn|Rd|1111|0011|Rm" , "ARMv6+ APSR.GE=W"],
["sbc" , "Rd!=XX, Rn!=XX, #ImmA" , "T32", "1111|0|ImmA:1|0|1011|0|Rn|0|ImmA:3|Rd|ImmA:8" , "ARMv6T2+ IT=ANY"],
["sbcS" , "Rd!=XX, Rn!=XX, #ImmA" , "T32", "1111|0|ImmA:1|0|1011|1|Rn|0|ImmA:3|Rd|ImmA:8" , "ARMv6T2+ IT=ANY APSR.NZCV=W"],
["sbc" , "Rd , Rn , #ImmA" , "A32", "Cond|001|0110|0|Rn|Rd|ImmA:12" , "ARMv4+"],
["sbcS" , "Rd!=PC, Rn , #ImmA" , "A32", "Cond|001|0110|1|Rn|Rd|ImmA:12" , "ARMv4+ APSR.NZCV=W"],
["sbc" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|000|110|Rm:3|Rx:3" , "ARMv4T+ IT=IN"],
["sbcS" , "Rx!=HI, Rx!=HI, Rm!=HI" , "T16", "0100|000|110|Rm:3|Rx:3" , "ARMv4T+ IT=OUT APSR.NZCV=W"],
["sbc" , "Rd!=XX, Rn!=XX, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|1011|0|Rn|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY"],
["sbcS" , "Rd!=XX, Rn!=XX, Rm!=XX, {Sop #Shift}" , "T32", "1110|101|1011|1|Rn|0|Shift:3|Rd|Shift:2|Sop:2|Rm" , "ARMv6T2+ IT=ANY"],
["sbc" , "Rd , Rn , Rm , {Sop #Shift}" , "A32", "Cond|000|0110|0|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+"],
["sbcS" , "Rd!=PC, Rn , Rm , {Sop #Shift}" , "A32", "Cond|000|0110|1|Rn|Rd|Shift:5|Sop:2|0|Rm" , "ARMv4+ APSR.NZCV=W"],
["sbc" , "Rd!=PC, Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|0110|0|Rn|Rd|Rs|0|Sop:2|1|Rm" , "ARMv4+"],
["sbcS" , "Rd!=PC, Rn!=PC, Rm!=PC, Sop Rs!=PC" , "A32", "Cond|000|0110|1|Rn|Rd|Rs|0|Sop:2|1|Rm" , "ARMv4+ APSR.NZCV=W"],
["sbfx" , "Rd!=XX, Rn!=XX, #LSB, #Width!=0" , "T32", "1111|001|1010|0|Rn|0|LSB:3|Rd|LSB:2|0|Width-1:5" , "ARMv6T2+ IT=ANY"],
["sbfx" , "Rd!=PC, Rn!=PC, #LSB, #Width" , "A32", "Cond|011|1101|Width-1:5|Rd|LSB:5|101|Rn" , "ARMv6T2+"],
["sdiv" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1100|1|Rn|1111|Rd|1111|Rm" , "IDIVT IT=ANY"],
["sdiv" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|1000|1|Rd|1111|Rm|0001|Rn" , "IDIVA"],
["sel" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0101|0|Rn|1111|Rd|1000|Rm" , "ARMv6T2+ IT=ANY"],
["sel" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|0100|0|Rn|Rd|1111|1011|Rm" , "ARMv6+ APSR.GE=R"],
["setend" , "#ImmZ" , "T16", "1011|0110|010|1|ImmZ:1|000" , "ARMv6+ IT=OUT"],
["setend" , "#ImmZ" , "A32", "1111|000|1000|0|0001|0000|00|ImmZ:1|0|0000|0000" , "ARMv6+ ARMv8-"],
["sev" , "" , "T16", "1011|1111|0100|0000" , "ARMv6T2+ IT=ANY"],
["sev" , "" , "T32", "1111|001|1101|0|1111|1000|0000|00000000" , "ARMv6T2+ IT=ANY"],
["sev" , "" , "A32", "Cond|001|1001|0|0000|1111|0000|0000|0100" , "ARMv7+ ARMv6K"],
["sevl" , "" , "A32", "Cond|001|1001|0|0000|1111|0000|0000|0101" , "?"],
["shadd16" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0100|1|Rn|1111|Rd|0010|Rm" , "ARMv6T2+ IT=ANY"],
["shadd16" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|0001|1|Rn|Rd|1111|0001|Rm" , "ARMv6+"],
["shadd8" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0100|0|Rn|1111|Rd|0010|Rm" , "ARMv6T2+ IT=ANY"],
["shadd8" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|0001|1|Rn|Rd|1111|1001|Rm" , "ARMv6+"],
["shasx" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0101|0|Rn|1111|Rd|0010|Rm" , "ARMv6T2+ IT=ANY"],
["shasx" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|0001|1|Rn|Rd|1111|0011|Rm" , "ARMv6+"],
["shsax" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0111|0|Rn|1111|Rd|0010|Rm" , "ARMv6T2+ IT=ANY"],
["shsax" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|0001|1|Rn|Rd|1111|0101|Rm" , "ARMv6+"],
["shsub16" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0110|1|Rn|1111|Rd|0010|Rm" , "ARMv6T2+ IT=ANY"],
["shsub16" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|0001|1|Rn|Rd|1111|0111|Rm" , "ARMv6+"],
["shsub8" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|0110|0|Rn|1111|Rd|0010|Rm" , "ARMv6T2+ IT=ANY"],
["shsub8" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|0001|1|Rn|Rd|1111|1111|Rm" , "ARMv6+"],
["smc" , "#ImmZ" , "A32", "Cond|000|1|0|0|1|0|0000|0000|0000|0111|ImmZ:4" , "SECURITY"],
["smlabb" , "Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "T32", "1111|101|1001|1|Rn|Ra|Rd|0000|Rm" , "ARMv6T2+ IT=ANY APSR.Q=X"],
["smlabb" , "Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "A32", "Cond|000|1000|0|Rd|Ra|Rm|1000|Rn" , "ARMv5TE+ APSR.Q=X"],
["smlabt" , "Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "T32", "1111|101|1001|1|Rn|Ra|Rd|0001|Rm" , "ARMv6T2+ IT=ANY APSR.Q=X"],
["smlabt" , "Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "A32", "Cond|000|1000|0|Rd|Ra|Rm|1100|Rn" , "ARMv5TE+ APSR.Q=X"],
["smlatb" , "Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "T32", "1111|101|1001|1|Rn|Ra|Rd|0010|Rm" , "ARMv6T2+ IT=ANY APSR.Q=X"],
["smlatb" , "Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "A32", "Cond|000|1000|0|Rd|Ra|Rm|1010|Rn" , "ARMv5TE+ APSR.Q=X"],
["smlatt" , "Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "T32", "1111|101|1001|1|Rn|Ra|Rd|0011|Rm" , "ARMv6T2+ IT=ANY APSR.Q=X"],
["smlatt" , "Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "A32", "Cond|000|1000|0|Rd|Ra|Rm|1110|Rn" , "ARMv5TE+ APSR.Q=X"],
["smlad" , "Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "T32", "1111|101|1001|0|Rn|Ra|Rd|0000|Rm" , "ARMv6T2+ IT=ANY APSR.Q=X"],
["smlad" , "Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "A32", "Cond|011|1000|0|Rd|Ra|Rm|0001|Rn" , "ARMv6+ APSR.Q=X"],
["smladx" , "Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "T32", "1111|101|1001|0|Rn|Ra|Rd|0001|Rm" , "ARMv6T2+ IT=ANY APSR.Q=X"],
["smladx" , "Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "A32", "Cond|011|1000|0|Rd|Ra|Rm|0011|Rn" , "ARMv6+ APSR.Q=X"],
["smlal" , "RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1110|0|Rn|RxLo|RxHi|0000|Rm" , "ARMv6T2+ IT=ANY"],
["smlal" , "RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|0111|0|RxHi|RxLo|Rm|1001|Rn" , "ARMv4+"],
["smlalS" , "RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|0111|1|RxHi|RxLo|Rm|1001|Rn" , "ARMv4+ APSR.NZ=W"],
["smlalbb" , "RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1110|0|Rn|RxLo|RxHi|1000|Rm" , "ARMv6T2+ IT=ANY"],
["smlalbb" , "RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1010|0|RxHi|RxLo|Rm|1000|Rn" , "ARMv5TE+"],
["smlalbt" , "RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1110|0|Rn|RxLo|RxHi|1001|Rm" , "ARMv6T2+ IT=ANY"],
["smlalbt" , "RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1010|0|RxHi|RxLo|Rm|1100|Rn" , "ARMv5TE+"],
["smlaltb" , "RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1110|0|Rn|RxLo|RxHi|1010|Rm" , "ARMv6T2+ IT=ANY"],
["smlaltb" , "RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1010|0|RxHi|RxLo|Rm|1010|Rn" , "ARMv5TE+"],
["smlaltt" , "RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1110|0|Rn|RxLo|RxHi|1011|Rm" , "ARMv6T2+ IT=ANY"],
["smlaltt" , "RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1010|0|RxHi|RxLo|Rm|1110|Rn" , "ARMv5TE+"],
["smlald" , "RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1110|0|Rn|RxLo|RxHi|1100|Rm" , "ARMv6T2+ IT=ANY"],
["smlald" , "RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|1010|0|RxHi|RxLo|Rm|0001|Rn" , "ARMv6+"],
["smlaldx" , "RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1110|0|Rn|RxLo|RxHi|1101|Rm" , "ARMv6T2+ IT=ANY"],
["smlaldx" , "RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|1010|0|RxHi|RxLo|Rm|0011|Rn" , "ARMv6+"],
["smlawb" , "Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "T32", "1111|101|1001|1|Rn|Ra|Rd|0000|Rm" , "ARMv6T2+ IT=ANY APSR.Q=X"],
["smlawb" , "Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "A32", "Cond|000|1001|0|Rd|Ra|Rm|1000|Rn" , "ARMv5TE+ APSR.Q=X"],
["smlawt" , "Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "T32", "1111|101|1001|1|Rn|Ra|Rd|0001|Rm" , "ARMv6T2+ IT=ANY APSR.Q=X"],
["smlawt" , "Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "A32", "Cond|000|1001|0|Rd|Ra|Rm|1100|Rn" , "ARMv5TE+ APSR.Q=X"],
["smlsd" , "Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "T32", "1111|101|1010|1|Rn|Ra|Rd|0000|Rm" , "ARMv6T2+ IT=ANY APSR.Q=X"],
["smlsd" , "Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "A32", "Cond|011|1000|0|Rd|Ra|Rm|0101|Rn" , "ARMv6+ APSR.Q=X"],
["smlsdx" , "Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "T32", "1111|101|1010|1|Rn|Ra|Rd|0001|Rm" , "ARMv6T2+ IT=ANY APSR.Q=X"],
["smlsdx" , "Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "A32", "Cond|011|1000|0|Rd|Ra|Rm|0111|Rn" , "ARMv6+ APSR.Q=X"],
["smlsld" , "RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1110|1|Rn|RxLo|RxHi|1100|Rm" , "ARMv6T2+ IT=ANY APSR.Q=X"],
["smlsld" , "RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|1010|0|RxHi|RxLo|Rm|0101|Rn" , "ARMv6+"],
["smlsldx" , "RxLo!=XX, RxHi!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1110|1|Rn|RxLo|RxHi|1101|Rm" , "ARMv6T2+ IT=ANY APSR.Q=X"],
["smlsldx" , "RxLo!=PC, RxHi!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|1010|0|RxHi|RxLo|Rm|0111|Rn" , "ARMv6+"],
["smmla" , "Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "T32", "1111|101|1010|1|Rn|Ra|Rd|0000|Rm" , "ARMv6T2+ IT=ANY"],
["smmla" , "Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "A32", "Cond|011|1010|1|Rd|Ra|Rm|0001|Rn" , "ARMv6+"],
["smmlar" , "Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "T32", "1111|101|1010|1|Rn|Ra|Rd|0001|Rm" , "ARMv6T2+ IT=ANY"],
["smmlar" , "Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "A32", "Cond|011|1010|1|Rd|Ra|Rm|0011|Rn" , "ARMv6+"],
["smmls" , "Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "T32", "1111|101|1011|0|Rn|Ra|Rd|0000|Rm" , "ARMv6T2+ IT=ANY"],
["smmls" , "Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "A32", "Cond|011|1010|1|Rd|Ra|Rm|1101|Rn" , "ARMv6+"],
["smmlsr" , "Rd!=XX, Rn!=XX, Rm!=XX, Ra!=XX" , "T32", "1111|101|1011|0|Rn|Ra|Rd|0001|Rm" , "ARMv6T2+ IT=ANY"],
["smmlsr" , "Rd!=PC, Rn!=PC, Rm!=PC, Ra!=PC" , "A32", "Cond|011|1010|1|Rd|Ra|Rm|1111|Rn" , "ARMv6+"],
["smmul" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1010|1|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY"],
["smmul" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|1010|1|Rd|1111|Rm|0001|Rn" , "ARMv6+"],
["smmulr" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1010|1|Rn|1111|Rd|0001|Rm" , "ARMv6T2+ IT=ANY"],
["smmulr" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|1010|1|Rd|1111|Rm|0011|Rn" , "ARMv6+"],
["smuad" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1001|0|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY APSR.Q=X"],
["smuad" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|1000|0|Rd|1111|Rm|0001|Rn" , "ARMv6+ APSR.Q=X"],
["smuadx" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1001|0|Rn|1111|Rd|0001|Rm" , "ARMv6T2+ IT=ANY APSR.Q=X"],
["smuadx" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|1000|0|Rd|1111|Rm|0011|Rn" , "ARMv6+ APSR.Q=X"],
["smulbb" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1000|1|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY"],
["smulbb" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1011|0|Rd|SBZ:4|Rm|1000|Rn" , "ARMv5TE+"],
["smulbt" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1000|1|Rn|1111|Rd|0001|Rm" , "ARMv6T2+ IT=ANY"],
["smulbt" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1011|0|Rd|SBZ:4|Rm|1100|Rn" , "ARMv5TE+"],
["smultb" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1000|1|Rn|1111|Rd|0010|Rm" , "ARMv6T2+ IT=ANY"],
["smultb" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1011|0|Rd|SBZ:4|Rm|1010|Rn" , "ARMv5TE+"],
["smultt" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1000|1|Rn|1111|Rd|0011|Rm" , "ARMv6T2+ IT=ANY"],
["smultt" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1011|0|Rd|SBZ:4|Rm|1110|Rn" , "ARMv5TE+"],
["smull" , "RdLo!=XX, RdHi!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1100|0|Rn|RdLo|RdHi|0000|Rm" , "ARMv6T2+ IT=ANY"],
["smull" , "RdLo!=PC, RdHi!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|0110|0|RdHi|RdLo|Rm|1001|Rn" , "ARMv4+ APSR.NZ=W"],
["smullS" , "RdLo!=PC, RdHi!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|0110|1|RdHi|RdLo|Rm|1001|Rn" , "ARMv4+ APSR.NZ=W"],
["smulwb" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1001|1|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY"],
["smulwb" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1001|0|Rd|SBZ:4|Rm|1010|Rn" , "ARMv5TE+"],
["smulwt" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1001|1|Rn|1111|Rd|0001|Rm" , "ARMv6T2+ IT=ANY"],
["smulwt" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|000|1001|0|Rd|SBZ:4|Rm|1110|Rn" , "ARMv5TE+"],
["smusd" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1010|0|Rn|1111|Rd|0000|Rm" , "ARMv6T2+ IT=ANY"],
["smusd" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|1000|0|Rd|1111|Rm|0101|Rn" , "ARMv6+"],
["smusdx" , "Rd!=XX, Rn!=XX, Rm!=XX" , "T32", "1111|101|1010|0|Rn|1111|Rd|0001|Rm" , "ARMv6T2+ IT=ANY"],
["smusdx" , "Rd!=PC, Rn!=PC, Rm!=PC" , "A32", "Cond|011|1000|0|Rd|1111|Rm|0111|Rn" , "ARMv6+"],
["srs" , "[Rn==SP]{!}, #Mode" , "A32", "1111|100|011|W|0|1101|0000|0101|000|Mode:5" , "ARMv6+"],