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out.vcd
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$date
Tue Jun 21 18:41:55 2022
$end
$version
GHDL v0
$end
$timescale
1 fs
$end
$var reg 1 ! clk_ext $end
$var reg 1 " reset_ext $end
$var reg 3 # wave_sel[2:0] $end
$var reg 8 $ fw_ext[7:0] $end
$var reg 8 % yq_out[7:0] $end
$var reg 1 & testing $end
$scope module i_dut1 $end
$var reg 1 ' clk $end
$var reg 1 ( reset $end
$var reg 3 ) wave[2:0] $end
$var reg 8 * fw[7:0] $end
$var reg 8 + yq[7:0] $end
$var reg 8 , pa_to_lut[7:0] $end
$var reg 8 - lut_output[7:0] $end
$scope module i_pa $end
$var reg 1 . clk $end
$var reg 1 / rst $end
$var reg 8 0 pa_in[7:0] $end
$var reg 8 1 pa_out[7:0] $end
$var reg 8 2 kfw_s[7:0] $end
$var reg 8 3 kfw_next[7:0] $end
$scope module i_adder $end
$var reg 8 4 x[7:0] $end
$var reg 8 5 y[7:0] $end
$var reg 1 6 c0 $end
$var reg 8 7 s[7:0] $end
$var reg 1 8 cn $end
$var reg 9 9 c[8:0] $end
$scope module gen_rca(0) $end
$scope module i_fa $end
$var reg 1 : x $end
$var reg 1 ; y $end
$var reg 1 < cin $end
$var reg 1 = s $end
$var reg 1 > cout $end
$upscope $end
$upscope $end
$scope module gen_rca(1) $end
$scope module i_fa $end
$var reg 1 ? x $end
$var reg 1 @ y $end
$var reg 1 A cin $end
$var reg 1 B s $end
$var reg 1 C cout $end
$upscope $end
$upscope $end
$scope module gen_rca(2) $end
$scope module i_fa $end
$var reg 1 D x $end
$var reg 1 E y $end
$var reg 1 F cin $end
$var reg 1 G s $end
$var reg 1 H cout $end
$upscope $end
$upscope $end
$scope module gen_rca(3) $end
$scope module i_fa $end
$var reg 1 I x $end
$var reg 1 J y $end
$var reg 1 K cin $end
$var reg 1 L s $end
$var reg 1 M cout $end
$upscope $end
$upscope $end
$scope module gen_rca(4) $end
$scope module i_fa $end
$var reg 1 N x $end
$var reg 1 O y $end
$var reg 1 P cin $end
$var reg 1 Q s $end
$var reg 1 R cout $end
$upscope $end
$upscope $end
$scope module gen_rca(5) $end
$scope module i_fa $end
$var reg 1 S x $end
$var reg 1 T y $end
$var reg 1 U cin $end
$var reg 1 V s $end
$var reg 1 W cout $end
$upscope $end
$upscope $end
$scope module gen_rca(6) $end
$scope module i_fa $end
$var reg 1 X x $end
$var reg 1 Y y $end
$var reg 1 Z cin $end
$var reg 1 [ s $end
$var reg 1 \ cout $end
$upscope $end
$upscope $end
$scope module gen_rca(7) $end
$scope module i_fa $end
$var reg 1 ] x $end
$var reg 1 ^ y $end
$var reg 1 _ cin $end
$var reg 1 ` s $end
$var reg 1 a cout $end
$upscope $end
$upscope $end
$upscope $end
$scope module i_reg $end
$var reg 1 b clk $end
$var reg 1 c rst $end
$var reg 8 d d[7:0] $end
$var reg 8 e q[7:0] $end
$scope module reg_gen(0) $end
$scope module i_dff $end
$var reg 1 f clk_dff $end
$var reg 1 g rst_dff $end
$var reg 1 h d_dff $end
$var reg 1 i q_dff $end
$upscope $end
$upscope $end
$scope module reg_gen(1) $end
$scope module i_dff $end
$var reg 1 j clk_dff $end
$var reg 1 k rst_dff $end
$var reg 1 l d_dff $end
$var reg 1 m q_dff $end
$upscope $end
$upscope $end
$scope module reg_gen(2) $end
$scope module i_dff $end
$var reg 1 n clk_dff $end
$var reg 1 o rst_dff $end
$var reg 1 p d_dff $end
$var reg 1 q q_dff $end
$upscope $end
$upscope $end
$scope module reg_gen(3) $end
$scope module i_dff $end
$var reg 1 r clk_dff $end
$var reg 1 s rst_dff $end
$var reg 1 t d_dff $end
$var reg 1 u q_dff $end
$upscope $end
$upscope $end
$scope module reg_gen(4) $end
$scope module i_dff $end
$var reg 1 v clk_dff $end
$var reg 1 w rst_dff $end
$var reg 1 x d_dff $end
$var reg 1 y q_dff $end
$upscope $end
$upscope $end
$scope module reg_gen(5) $end
$scope module i_dff $end
$var reg 1 z clk_dff $end
$var reg 1 { rst_dff $end
$var reg 1 | d_dff $end
$var reg 1 } q_dff $end
$upscope $end
$upscope $end
$scope module reg_gen(6) $end
$scope module i_dff $end
$var reg 1 !" clk_dff $end
$var reg 1 "" rst_dff $end
$var reg 1 #" d_dff $end
$var reg 1 $" q_dff $end
$upscope $end
$upscope $end
$scope module reg_gen(7) $end
$scope module i_dff $end
$var reg 1 %" clk_dff $end
$var reg 1 &" rst_dff $end
$var reg 1 '" d_dff $end
$var reg 1 (" q_dff $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module i_lut $end
$var reg 8 )" lut_line[7:0] $end
$var reg 8 *" lut_data[7:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
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