-
Notifications
You must be signed in to change notification settings - Fork 0
/
tb_avm_cache.gtkw
78 lines (78 loc) · 4.35 KB
/
tb_avm_cache.gtkw
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
[*]
[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
[*] Fri Oct 14 12:51:29 2022
[*]
[dumpfile] "/home/mfj/git/PRIVATE/MJoergen/Avalon/tb_avm_cache.ghw"
[dumpfile_mtime] "Fri Oct 14 12:51:19 2022"
[dumpfile_size] 1110241
[savefile] "/home/mfj/git/PRIVATE/MJoergen/Avalon/tb_avm_cache.gtkw"
[timestart] 0
[size] 1853 1138
[pos] 0 33
*-32.986801 18134600000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.tb_avm_cache.
[treeopen] top.tb_avm_cache.i_avm_cache.
[sst_width] 371
[signals_width] 321
[sst_expanded] 1
[sst_vpaned_height] 248
@28
top.tb_avm_cache.clk
top.tb_avm_cache.rst
top.tb_avm_cache.stop_test
top.tb_avm_cache.s_avm_has_started
top.tb_avm_cache.s_avm_start
top.tb_avm_cache.s_avm_wait
[color] 6
top.tb_avm_cache.s_avm_waitrequest
[color] 2
top.tb_avm_cache.s_avm_write
[color] 2
top.tb_avm_cache.s_avm_read
@22
#{top.tb_avm_cache.s_avm_address[5:0]} top.tb_avm_cache.s_avm_address[4] top.tb_avm_cache.s_avm_address[3] top.tb_avm_cache.s_avm_address[2] top.tb_avm_cache.s_avm_address[1] top.tb_avm_cache.s_avm_address[0]
#{top.tb_avm_cache.s_avm_writedata[7:0]} top.tb_avm_cache.s_avm_writedata[7] top.tb_avm_cache.s_avm_writedata[6] top.tb_avm_cache.s_avm_writedata[5] top.tb_avm_cache.s_avm_writedata[4] top.tb_avm_cache.s_avm_writedata[3] top.tb_avm_cache.s_avm_writedata[2] top.tb_avm_cache.s_avm_writedata[1] top.tb_avm_cache.s_avm_writedata[0]
@28
top.tb_avm_cache.s_avm_byteenable[0]
@22
#{top.tb_avm_cache.s_avm_burstcount[7:0]} top.tb_avm_cache.s_avm_burstcount[7] top.tb_avm_cache.s_avm_burstcount[6] top.tb_avm_cache.s_avm_burstcount[5] top.tb_avm_cache.s_avm_burstcount[4] top.tb_avm_cache.s_avm_burstcount[3] top.tb_avm_cache.s_avm_burstcount[2] top.tb_avm_cache.s_avm_burstcount[1] top.tb_avm_cache.s_avm_burstcount[0]
@28
[color] 3
top.tb_avm_cache.s_avm_readdatavalid
@22
#{top.tb_avm_cache.s_avm_readdata[7:0]} top.tb_avm_cache.s_avm_readdata[7] top.tb_avm_cache.s_avm_readdata[6] top.tb_avm_cache.s_avm_readdata[5] top.tb_avm_cache.s_avm_readdata[4] top.tb_avm_cache.s_avm_readdata[3] top.tb_avm_cache.s_avm_readdata[2] top.tb_avm_cache.s_avm_readdata[1] top.tb_avm_cache.s_avm_readdata[0]
@28
[color] 6
top.tb_avm_cache.m_avm_waitrequest
[color] 2
top.tb_avm_cache.m_avm_write
[color] 2
top.tb_avm_cache.m_avm_read
@22
#{top.tb_avm_cache.m_avm_address[5:0]} top.tb_avm_cache.m_avm_address[4] top.tb_avm_cache.m_avm_address[3] top.tb_avm_cache.m_avm_address[2] top.tb_avm_cache.m_avm_address[1] top.tb_avm_cache.m_avm_address[0]
#{top.tb_avm_cache.m_avm_writedata[7:0]} top.tb_avm_cache.m_avm_writedata[7] top.tb_avm_cache.m_avm_writedata[6] top.tb_avm_cache.m_avm_writedata[5] top.tb_avm_cache.m_avm_writedata[4] top.tb_avm_cache.m_avm_writedata[3] top.tb_avm_cache.m_avm_writedata[2] top.tb_avm_cache.m_avm_writedata[1] top.tb_avm_cache.m_avm_writedata[0]
@28
top.tb_avm_cache.m_avm_byteenable[0]
@22
#{top.tb_avm_cache.m_avm_burstcount[7:0]} top.tb_avm_cache.m_avm_burstcount[7] top.tb_avm_cache.m_avm_burstcount[6] top.tb_avm_cache.m_avm_burstcount[5] top.tb_avm_cache.m_avm_burstcount[4] top.tb_avm_cache.m_avm_burstcount[3] top.tb_avm_cache.m_avm_burstcount[2] top.tb_avm_cache.m_avm_burstcount[1] top.tb_avm_cache.m_avm_burstcount[0]
@28
[color] 3
top.tb_avm_cache.m_avm_readdatavalid
@22
#{top.tb_avm_cache.m_avm_readdata[7:0]} top.tb_avm_cache.m_avm_readdata[7] top.tb_avm_cache.m_avm_readdata[6] top.tb_avm_cache.m_avm_readdata[5] top.tb_avm_cache.m_avm_readdata[4] top.tb_avm_cache.m_avm_readdata[3] top.tb_avm_cache.m_avm_readdata[2] top.tb_avm_cache.m_avm_readdata[1] top.tb_avm_cache.m_avm_readdata[0]
#{top.tb_avm_cache.i_avm_cache.cache_addr[4:0]} top.tb_avm_cache.i_avm_cache.cache_addr[4] top.tb_avm_cache.i_avm_cache.cache_addr[3] top.tb_avm_cache.i_avm_cache.cache_addr[2] top.tb_avm_cache.i_avm_cache.cache_addr[1] top.tb_avm_cache.i_avm_cache.cache_addr[0]
@420
top.tb_avm_cache.i_avm_cache.cache_count
@22
#{top.tb_avm_cache.i_avm_cache.cache_offset_s[4:0]} top.tb_avm_cache.i_avm_cache.cache_offset_s[4] top.tb_avm_cache.i_avm_cache.cache_offset_s[3] top.tb_avm_cache.i_avm_cache.cache_offset_s[2] top.tb_avm_cache.i_avm_cache.cache_offset_s[1] top.tb_avm_cache.i_avm_cache.cache_offset_s[0]
@28
top.tb_avm_cache.i_avm_cache.cache_rd_hit_s
top.tb_avm_cache.i_avm_cache.cache_wr_hit_s
top.tb_avm_cache.i_avm_cache.cache_filled_s
@420
top.tb_avm_cache.i_avm_cache.state
@29
top.tb_avm_cache.m_error
[pattern_trace] 1
[pattern_trace] 0