How to generate disasm for tests?

[otakubeam]

In risc-v unit tests there is a section with disasm listings. They seem somewhat random to me.
For example:

    TEST_RV32_DISASM  ( 0x30200073, "mret");
    TEST_RV32_DISASM  ( 0x30202373, "csrrs $medeleg, $t1, $zero");
    TEST_RV32_DISASM  ( 0x30205073, "csrrwi $medeleg, $zero, 0x0");
    TEST_RV32_DISASM  ( 0x4082,     "c_lwsp $ra, 0x0($sp)");
    TEST_RV32_DISASM  ( 0xdf86,     "c_swsp $ra, 0xfc($sp)");
    TEST_RV64_DISASM  ( 0x6082,     "c_ldsp $ra, 0x0($sp)");
    TEST_RV64_DISASM  ( 0xff86,     "c_sdsp $ra, 0x1f8($sp)");
    TEST_RV128_DISASM ( 0x30fe,     "c_lqsp $ra, 0x3f0($sp)");
    TEST_RV128_DISASM ( 0xb686,     "c_sqsp $ra, 0x360($sp)");
    TEST_RV32_DISASM  ( 0x4110,     "c_lw $a2, 0x0($a0)");
    TEST_RV64_DISASM  ( 0x6298,     "c_ld $a4, 0x0($a3)");
    TEST_RV64_DISASM  ( 0xfefc,     "c_sd $a5, 0xf8($a3)");
    TEST_RV32_DISASM  ( 0xdefc,     "c_sw $a5, 0x7c($a3)");
    TEST_RV128_DISASM ( 0x36d8,     "c_lq $a4, 0x1a0($a3)");
    TEST_RV128_DISASM ( 0xaebc,     "c_sq $a5, 0x150($a3)");
    TEST_RV32_DISASM  ( 0xb001,     "c_j -2048");

How do I write one to test my function? Specifically, sbset

[pavelkryukov]

Sorry, I don't get the question.
To write a test for an instruction, you need to check its specification on RISC-V Manual: https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf

[otakubeam]

On a quick glance I don't see what part of the manual you are referring to. Is it the part about opcode encodings?

I have written the second part of the tests, like this:

TEST_RV32_RR_OP( 1, sbset, 0x2, 0x0, 1)
TEST_RV32_RR_OP( 2, sbset, 0xf, 0xf, 1)
TEST_RV32_RR_OP( 3, sbset, 0x1f, 0x0f, 4)

It's more or less obvious.

What I don't understand is how to write the first part, so something along the lines

TEST_RV32_DISASM  ( 0x<some-hex-value>,     "sbset $<some register>, $<some register, or maybe a literal?>");

Could you help me out with this?

I am not sure if this is some common knowledge. If that's the case I'm sorry

[otakubeam]

So, sbset's funct7 is 0010100. Then there are two source registers, five bits each. For example $a2 is 00011. Then there is f3, so 001. A destination register and, finally, the opcode which is 0110011.
The resulting binary number constitutes the full instruction. Is that correct?

[pavelkryukov]

Right. I think it is explained in L7: https://github.com/MIPT-ILab/ca-lectures/blob/master/mipt-mips/2020/Lecture%207%20-%20RISC-V%20ISA.pptx?raw=true