An unidentifiable mechanism that helps you bypass GFW.

Verilator open-source SystemVerilog simulator and lint system

Learning FPGA, yosys, nextpnr, and RISC-V

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

船长关于机器学习、计算机视觉和工程技术的总结和分享

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

Run Time for AIE and FPGA based platforms

A robotic arm controller design based on AMD/Xilinx KR260 FPGA dev-kit.

Vitis Model Composer Examples and Tutorials

Verilator open-source SystemVerilog simulator and lint system

Module for the ns-3 discrete-event simulator. Enables the community to test networking solutions for THz communications.

Code for M. Polese, J. Jornet, T. Melodia, M. Zorzi, “Toward End-to-End, Full-Stack 6G Terahertz Networks”, https://arxiv.org/abs/2005.07989, 2020.