example added

Author: Kurus

example/cookbook/dff/dff.py

@@ -1,31 +1,29 @@
 from myhdl import *
 from myhdl.conversion import analyze
 
-def dff(q, d, clk):
-
+def dff(t,q, d, clk):
     @always(clk.posedge)
-    def logic():
-        q.next = d
-
-    return logic
+    def toggle():
+        q.next =not q
+    def store():
+        q.next= d
+    if t==1 :
+        return logic
+    else return store
 
 
 from random import randrange
 
-def test_dff():
-    
-    q, d, clk = [Signal(bool(0)) for i in range(3)]
-    
-    dff_inst = dff(q, d, clk)
-
+def test_dff():    
+    q, d= [[Signal(bool(0)) for i in range(3)] for i in range(2)]
+    clk = [Signal(bool(0)) for i in range(3)]  
+    counter = [dff(q, d, clk) for i in range(2)]
     @always(delay(10))
     def clkgen():
         clk.next = not clk
-
     @always(clk.negedge)
     def stimulus():
         d.next = randrange(2)
-
     return dff_inst, clkgen, stimulus
 
 def simulate(timesteps):
@@ -34,8 +32,8 @@ def simulate(timesteps):
     sim = Simulation(tb)
     sim.run(timesteps)
 
-simulate(2000)
-
+s=Simulation(test_dff())
+s.run(2000)
 def convert():
     q, d, clk = [Signal(bool(0)) for i in range(3)]
     toVerilog(dff, q, d, clk)

myhdl_examples/example.py

@@ -0,0 +1,13 @@
+from myhdl import *
+
+
+def tff(t,q, d, clk):
+    @always(clk.posedge)
+    def toggle():
+        q.next =not q
+    def store():
+        q.next= d
+    if t==1 :
+        return logic
+    else:
+        return store

myhdl_examples/example_1.py

@@ -0,0 +1,13 @@
+from myhdl import *
+
+
+def tff(t,q, d, clk):
+    @always(clk.posedge)
+    def toggle():
+        q.next =not q
+    def store():
+        q.next= d
+    if t==1 :
+        return logic
+    else:
+        return store