replace backqote with repr everywhere excpt conversion test

Author: jck

myhdl/conversion/_toVHDL.py

@@ -937,7 +937,7 @@ def visit_Call(self, node):
         elif f is len:
             val = self.getVal(node)
             self.require(node, val is not None, "cannot calculate len")
-            self.write(`val`)
+            self.write(repr(val))
             return
         elif f is now:
             pre, suf = self.inferCast(node.vhd, node.vhdOri)

myhdl/conversion/_toVerilog.py

@@ -720,7 +720,7 @@ def visit_Call(self, node):
         elif f is len:
             val = self.getVal(node)
             self.require(node, val is not None, "cannot calculate len")
-            self.write(`val`)
+            self.write(repr(val))
             return
         elif f is now:
             self.write("$time")

myhdl/test/core/test_Signal.py

@@ -164,7 +164,7 @@ def testModify(self):
                 s.next[3] = 5
             else:
                 s.next # plain read access
-            self.assertTrue(s.val is not s.next, `s.val`)
+            self.assertTrue(s.val is not s.next, repr(s.val))
 
     def testUpdatePosedge(self):
         """ update on posedge should return event and posedge waiters """