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[SYCL][FPGA] Update ArbitraryFloatCastTo/FromInt processing
Add processing of a new parameter To/FromSign that specifies if integer value to cast to/from is signed or not for ArbitraryFloatCastTo/FromInt functions. See spec update (intel/llvm#1934): https://github.com/intel/llvm/blob/ea96f3ccee007e04074af6e275dbfce4fce13717/sycl/doc/extensions/SPIRV/SPV_INTEL_arbitrary_precision_floating_point.asciidoc Signed-off-by: Mikhail Lychkov <mikhail.lychkov@intel.com>
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‎lib/SPIRV/SPIRVReader.cpp‎

Lines changed: 21 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -2772,21 +2772,23 @@ CallInst *SPIRVToLLVM::transArbFloatInst(SPIRVInstruction *BI, BasicBlock *BB,
27722772

27732773
// Format of instruction CastFromInt:
27742774
// LLVM arbitrary floating point functions return value: iN
2775-
// Arguments: A(iN), Mout(i32), EnableSubnormals(i32),
2775+
// Arguments: A(iN), Mout(i32), FromSign(bool), EnableSubnormals(i32),
27762776
// RoundingMode(i32), RoundingAccuracy(i32)
27772777
// where A and return values are of arbitrary precision integer type.
27782778
// SPIR-V arbitrary floating point instruction layout:
2779-
// <id>ResTy Res<id> A<id> Literal Mout Literal EnableSubnormals
2780-
// Literal RoundingMode Literal RoundingAccuracy
2779+
// <id>ResTy Res<id> A<id> Literal Mout Literal FromSign
2780+
// Literal EnableSubnormals Literal RoundingMode
2781+
// Literal RoundingAccuracy
27812782

27822783
// Format of instruction CastToInt:
27832784
// LLVM arbitrary floating point functions return value: iN
2784-
// Arguments: A(iN), MA(i32), EnableSubnormals(i32), RoundingMode(i32),
2785-
// RoundingAccuracy(i32)
2785+
// Arguments: A(iN), MA(i32), ToSign(bool), EnableSubnormals(i32),
2786+
// RoundingMode(i32), RoundingAccuracy(i32)
27862787
// where A and return values are of arbitrary precision integer type.
27872788
// SPIR-V arbitrary floating point instruction layout:
2788-
// <id>ResTy Res<id> A<id> Literal MA Literal EnableSubnormals
2789-
// Literal RoundingMode Literal RoundingAccuracy
2789+
// <id>ResTy Res<id> A<id> Literal MA Literal ToSign
2790+
// Literal EnableSubnormals Literal RoundingMode
2791+
// Literal RoundingAccuracy
27902792

27912793
// Format of other instructions:
27922794
// LLVM arbitrary floating point functions return value: iN
@@ -2798,15 +2800,15 @@ CallInst *SPIRVToLLVM::transArbFloatInst(SPIRVInstruction *BI, BasicBlock *BB,
27982800
// Literal RoundingMode Literal RoundingAccuracy
27992801

28002802
Type *RetTy = transType(BI->getType());
2801-
IntegerType *Int32Ty = IntegerType::get(*Context, 32);
2803+
IntegerType *Int32Ty = Type::getInt32Ty(*Context);
28022804

28032805
auto Inst = static_cast<SPIRVArbFloatIntelInst *>(BI);
28042806

28052807
Type *ATy = transType(Inst->getOperand(0)->getType());
28062808
Type *BTy = nullptr;
28072809

28082810
// Words contain:
2809-
// A<id> [Literal MA] [B<id>] [Literal MB] [Literal Mout]
2811+
// A<id> [Literal MA] [B<id>] [Literal MB] [Literal Mout] [Literal Sign]
28102812
// [Literal EnableSubnormals Literal RoundingMode Literal RoundingAccuracy]
28112813
const std::vector<SPIRVWord> Words = Inst->getOpWords();
28122814
auto WordsItr = Words.begin() + 1; /* Skip word for A input id */
@@ -2816,6 +2818,14 @@ CallInst *SPIRVToLLVM::transArbFloatInst(SPIRVInstruction *BI, BasicBlock *BB,
28162818
transValue(Inst->getOperand(0), BB->getParent(), BB) /* A - input */,
28172819
ConstantInt::get(Int32Ty, *WordsItr++) /* MA/Mout - width of mantissa */};
28182820

2821+
Op OC = Inst->getOpCode();
2822+
if (OC == OpArbitraryFloatCastFromIntINTEL ||
2823+
OC == OpArbitraryFloatCastToIntINTEL) {
2824+
IntegerType *Int1Ty = Type::getInt1Ty(*Context);
2825+
ArgTys.push_back(Int1Ty);
2826+
Args.push_back(ConstantInt::get(Int1Ty, *WordsItr++)); /* ToSign/FromSign */
2827+
}
2828+
28192829
if (IsBinaryInst) {
28202830
/* B - input */
28212831
BTy = transType(Inst->getOperand(2)->getType());
@@ -2831,8 +2841,8 @@ CallInst *SPIRVToLLVM::transArbFloatInst(SPIRVInstruction *BI, BasicBlock *BB,
28312841
});
28322842

28332843
FunctionType *FT = FunctionType::get(RetTy, ArgTys, false);
2834-
std::string FuncName = SPIRVArbFloatIntelMap::rmap(Inst->getOpCode()) +
2835-
getFuncAPIntSuffix(RetTy, ATy, BTy);
2844+
std::string FuncName =
2845+
SPIRVArbFloatIntelMap::rmap(OC) + getFuncAPIntSuffix(RetTy, ATy, BTy);
28362846
FunctionCallee FCallee = M->getOrInsertFunction(FuncName, FT);
28372847

28382848
auto *Func = cast<Function>(FCallee.getCallee());

‎lib/SPIRV/SPIRVWriter.cpp‎

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3668,21 +3668,23 @@ LLVMToSPIRV::transBuiltinToInstWithoutDecoration(Op OC, CallInst *CI,
36683668
// Format of instruction CastFromInt:
36693669
// LLVM arbitrary floating point functions return value type:
36703670
// iN (arbitrary precision integer of N bits length)
3671-
// Arguments: A(iN), Mout(i32), EnableSubnormals(i32), RoundingMode(i32),
3672-
// RoundingAccuracy(i32)
3671+
// Arguments: A(iN), Mout(i32), FromSign(bool), EnableSubnormals(i32),
3672+
// RoundingMode(i32), RoundingAccuracy(i32)
36733673
// where A and return values are of arbitrary precision integer type.
36743674
// SPIR-V arbitrary floating point instruction layout:
3675-
// <id>ResTy Res<id> A<id> Literal Mout Literal EnableSubnormals
3676-
// Literal RoundingMode Literal RoundingAccuracy
3675+
// <id>ResTy Res<id> A<id> Literal Mout Literal FromSign
3676+
// Literal EnableSubnormals Literal RoundingMode
3677+
// Literal RoundingAccuracy
36773678

36783679
// Format of instruction CastToInt:
36793680
// LLVM arbitrary floating point functions return value: iN
3680-
// Arguments: A(iN), MA(i32), EnableSubnormals(i32), RoundingMode(i32),
3681-
// RoundingAccuracy(i32)
3681+
// Arguments: A(iN), MA(i32), ToSign(bool), EnableSubnormals(i32),
3682+
// RoundingMode(i32), RoundingAccuracy(i32)
36823683
// where A and return values are of arbitrary precision integer type.
36833684
// SPIR-V arbitrary floating point instruction layout:
3684-
// <id>ResTy Res<id> A<id> Literal MA Literal EnableSubnormals
3685-
// Literal RoundingMode Literal RoundingAccuracy
3685+
// <id>ResTy Res<id> A<id> Literal MA Literal ToSign
3686+
// Literal EnableSubnormals Literal RoundingMode
3687+
// Literal RoundingAccuracy
36863688

36873689
// Format of other instructions:
36883690
// LLVM arbitrary floating point functions return value: iN

‎lib/SPIRV/libSPIRV/SPIRVInstruction.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2677,8 +2677,8 @@ class SPIRVArbFloatIntelInst : public SPIRVInstTemplateBase {
26772677
OpArbitraryFloat##x##INTEL, __VA_ARGS__> \
26782678
SPIRVArbitraryFloat##x##INTEL;
26792679
_SPIRV_OP(Cast, true, 9)
2680-
_SPIRV_OP(CastFromInt, true, 8)
2681-
_SPIRV_OP(CastToInt, true, 8)
2680+
_SPIRV_OP(CastFromInt, true, 9)
2681+
_SPIRV_OP(CastToInt, true, 9)
26822682
_SPIRV_OP(Add, true, 11)
26832683
_SPIRV_OP(Sub, true, 11)
26842684
_SPIRV_OP(Mul, true, 11)

‎lib/SPIRV/libSPIRV/SPIRVModule.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1489,7 +1489,7 @@ SPIRVInstruction *SPIRVModuleImpl::addArbFloatPointIntelInst(
14891489
Op OC, SPIRVType *ResTy, SPIRVValue *InA, SPIRVValue *InB,
14901490
const std::vector<SPIRVWord> &Ops, SPIRVBasicBlock *BB) {
14911491
// SPIR-V format:
1492-
// A<id> [Literal MA] [B<id>] [Literal MB] [Literal Mout]
1492+
// A<id> [Literal MA] [B<id>] [Literal MB] [Literal Mout] [Literal Sign]
14931493
// [Literal EnableSubnormals Literal RoundingMode Literal RoundingAccuracy]
14941494
auto OpsItr = Ops.begin();
14951495
std::vector<SPIRVWord> TheOps = getVec(InA->getId(), *OpsItr++);

‎test/transcoding/capability-arbitrary-precision-floating-point.ll‎

Lines changed: 16 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,11 @@
33
; SYCL source code for this test:
44
; #include "CL/__spirv/spirv_ops.hpp"
55
;
6-
; constexpr int32_t Subnorm = 0, RndMode = 2, RndAcc = 1;
6+
; constexpr int32_t Subnorm = 0;
7+
; constexpr int32_t RndMode = 2;
8+
; constexpr int32_t RndAcc = 1;
9+
; constexpr bool FromSign = false;
10+
; constexpr bool ToSign = true;
711
;
812
; template <int EA, int MA, int Eout, int Mout>
913
; void ap_float_cast() {
@@ -18,15 +22,15 @@
1822
; ap_int<WA> A;
1923
; ap_int<1+Eout+Mout> cast_from_int_res =
2024
; __spirv_ArbitraryFloatCastFromIntINTEL<WA, 1+Eout+Mout>(
21-
; A, Mout, Subnorm, RndMode, RndAcc);
25+
; A, Mout, FromSign, Subnorm, RndMode, RndAcc);
2226
; }
2327
;
2428
; template <int EA, int MA, int Wout>
2529
; void ap_float_cast_to_int() {
2630
; ap_int<1+EA+MA> A;
2731
; ap_int<Wout> cast_to_int_res =
2832
; __spirv_ArbitraryFloatCastToIntINTEL<1+EA+MA, Wout>(
29-
; A, MA, Subnorm, RndMode, RndAcc);
33+
; A, MA, ToSign, Subnorm, RndMode, RndAcc);
3034
; }
3135
;
3236
; Test also that the same arbitrary precision floating point intrinsic with
@@ -397,7 +401,7 @@
397401
; }
398402

399403
; LLVM IR compilation command:
400-
; clang -I llvm/include/sycl -S -emit-llvm -fsycl-device-only capability-arbitrary-precision-floating-point.cpp
404+
; clang -I llvm/include/sycl -S -emit-llvm -fno-sycl-early-optimizations -fsycl-device-only capability-arbitrary-precision-floating-point.cpp
401405

402406
; RUN: llvm-as %s -o %t.bc
403407
; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_arbitrary_precision_integers,+SPV_INTEL_arbitrary_precision_floating_point -o %t.spv
@@ -566,10 +570,10 @@ define linkonce_odr dso_local spir_func void @_Z22ap_float_cast_from_intILi43ELi
566570
%4 = bitcast i25* %2 to i8*
567571
call void @llvm.lifetime.start.p0i8(i64 4, i8* %4) #5
568572
%5 = load i43, i43* %1, align 8, !tbaa !11
569-
%6 = call spir_func signext i25 @_Z38__spirv_ArbitraryFloatCastFromIntINTELILi43ELi25EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiii(i43 %5, i32 16, i32 0, i32 2, i32 1) #5
573+
%6 = call spir_func signext i25 @_Z38__spirv_ArbitraryFloatCastFromIntINTELILi43ELi25EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiibiii(i43 %5, i32 16, i1 zeroext false, i32 0, i32 2, i32 1) #5
570574
; CHECK-SPIRV: 6 Load [[Ty_43]] [[CastFromInt_AId:[0-9]+]]
571-
; CHECK-SPIRV-NEXT: 8 ArbitraryFloatCastFromIntINTEL [[Ty_25]] [[#]] [[CastFromInt_AId]] 16 0 2 1
572-
; CHECK-LLVM: call i25 @intel_arbitrary_float_cast_from_int.i25.i43(i43 %[[#]], i32 16, i32 0, i32 2, i32 1)
575+
; CHECK-SPIRV-NEXT: 9 ArbitraryFloatCastFromIntINTEL [[Ty_25]] [[#]] [[CastFromInt_AId]] 16 0 0 2 1
576+
; CHECK-LLVM: call i25 @intel_arbitrary_float_cast_from_int.i25.i43(i43 %[[#]], i32 16, i1 false, i32 0, i32 2, i32 1)
573577
store i25 %6, i25* %2, align 4, !tbaa !13
574578
%7 = bitcast i25* %2 to i8*
575579
call void @llvm.lifetime.end.p0i8(i64 4, i8* %7) #5
@@ -587,10 +591,10 @@ define linkonce_odr dso_local spir_func void @_Z20ap_float_cast_to_intILi7ELi15E
587591
%4 = bitcast i30* %2 to i8*
588592
call void @llvm.lifetime.start.p0i8(i64 4, i8* %4) #5
589593
%5 = load i23, i23* %1, align 4, !tbaa !15
590-
%6 = call spir_func signext i30 @_Z36__spirv_ArbitraryFloatCastToIntINTELILi23ELi30EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiii(i23 signext %5, i32 15, i32 0, i32 2, i32 1) #5
594+
%6 = call spir_func signext i30 @_Z36__spirv_ArbitraryFloatCastToIntINTELILi23ELi30EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiibiii(i23 signext %5, i32 15, i1 zeroext true, i32 0, i32 2, i32 1) #5
591595
; CHECK-SPIRV: 6 Load [[Ty_23]] [[CastToInt_AId:[0-9]+]]
592-
; CHECK-SPIRV-NEXT: 8 ArbitraryFloatCastToIntINTEL [[Ty_30]] [[#]] [[CastToInt_AId]] 15 0 2 1
593-
; CHECK-LLVM: call i30 @intel_arbitrary_float_cast_to_int.i30.i23(i23 %[[#]], i32 15, i32 0, i32 2, i32 1)
596+
; CHECK-SPIRV-NEXT: 9 ArbitraryFloatCastToIntINTEL [[Ty_30]] [[#]] [[CastToInt_AId]] 15 1 0 2 1
597+
; CHECK-LLVM: call i30 @intel_arbitrary_float_cast_to_int.i30.i23(i23 %[[#]], i32 15, i1 true, i32 0, i32 2, i32 1)
594598
store i30 %6, i30* %2, align 4, !tbaa !17
595599
%7 = bitcast i30* %2 to i8*
596600
call void @llvm.lifetime.end.p0i8(i64 4, i8* %7) #5
@@ -1562,10 +1566,10 @@ define linkonce_odr dso_local spir_func void @_Z13ap_float_pownILi4ELi7ELi10ELi5
15621566
declare dso_local spir_func i40 @_Z31__spirv_ArbitraryFloatCastINTELILi40ELi40EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i40, i32, i32, i32, i32, i32) #4
15631567

15641568
; Function Attrs: nounwind
1565-
declare dso_local spir_func signext i25 @_Z38__spirv_ArbitraryFloatCastFromIntINTELILi43ELi25EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiii(i43, i32, i32, i32, i32) #4
1569+
declare dso_local spir_func signext i25 @_Z38__spirv_ArbitraryFloatCastFromIntINTELILi43ELi25EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiibiii(i43, i32, i1 zeroext, i32, i32, i32) #4
15661570

15671571
; Function Attrs: nounwind
1568-
declare dso_local spir_func signext i30 @_Z36__spirv_ArbitraryFloatCastToIntINTELILi23ELi30EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiii(i23 signext, i32, i32, i32, i32) #4
1572+
declare dso_local spir_func signext i30 @_Z36__spirv_ArbitraryFloatCastToIntINTELILi23ELi30EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiibiii(i23 signext, i32, i1 zeroext, i32, i32, i32) #4
15691573

15701574
; Function Attrs: nounwind
15711575
declare dso_local spir_func signext i14 @_Z30__spirv_ArbitraryFloatAddINTELILi13ELi15ELi14EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i13 signext, i32, i15 signext, i32, i32, i32, i32, i32) #4

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