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[NFC] Remove Intel Op codes that are being upstreamed (#1657)
Unstreamed in KhronosGroup/SPIRV-Headers#298 Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
1 parent cad5182 commit 1d56946

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7 files changed

+54
-93
lines changed

7 files changed

+54
-93
lines changed

‎lib/SPIRV/SPIRVReader.cpp

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -863,7 +863,7 @@ void SPIRVToLLVM::setLLVMLoopMetadata(const LoopInstType *LM,
863863
}
864864
if (LC & LoopControlNoFusionINTELMask)
865865
Metadata.push_back(getMetadataFromName("llvm.loop.fusion.disable"));
866-
if (LC & spv::internal::LoopControlLoopCountINTELMask) {
866+
if (LC & spv::LoopControlLoopCountINTELMask) {
867867
// LoopCountINTELMask parameters are int64 and each parameter is stored
868868
// as 2 SPIRVWords (int32)
869869
assert(NumParam + 6 <= LoopControlParameters.size() &&
@@ -896,7 +896,7 @@ void SPIRVToLLVM::setLLVMLoopMetadata(const LoopInstType *LM,
896896
"llvm.loop.intel.loopcount_avg", static_cast<int64_t>(LoopCountAvg)));
897897
}
898898
}
899-
if (LC & spv::internal::LoopControlMaxReinvocationDelayINTELMask) {
899+
if (LC & spv::LoopControlMaxReinvocationDelayINTELMask) {
900900
Metadata.push_back(llvm::MDNode::get(
901901
*Context, getMetadataFromNameAndParameter(
902902
"llvm.loop.intel.max_reinvocation_delay.count",
@@ -4259,9 +4259,9 @@ bool SPIRVToLLVM::transFPGAFunctionMetadata(SPIRVFunction *BF, Function *F) {
42594259
MetadataVec.push_back(ConstantAsMetadata::get(getUInt32(M, Literals[1])));
42604260
F->setMetadata(kSPIR2MD::LoopFuse, MDNode::get(*Context, MetadataVec));
42614261
}
4262-
if (BF->hasDecorate(internal::DecorationMathOpDSPModeINTEL)) {
4262+
if (BF->hasDecorate(DecorationMathOpDSPModeINTEL)) {
42634263
std::vector<SPIRVWord> Literals =
4264-
BF->getDecorationLiterals(internal::DecorationMathOpDSPModeINTEL);
4264+
BF->getDecorationLiterals(DecorationMathOpDSPModeINTEL);
42654265
assert(Literals.size() == 2 &&
42664266
"MathOpDSPModeINTEL decoration shall have 2 literals");
42674267
F->setMetadata(kSPIR2MD::PreferDSP,
@@ -4273,25 +4273,23 @@ bool SPIRVToLLVM::transFPGAFunctionMetadata(SPIRVFunction *BF, Function *F) {
42734273
getUInt32(M, Literals[1]))));
42744274
}
42754275
}
4276-
if (BF->hasDecorate(internal::DecorationInitiationIntervalINTEL)) {
4276+
if (BF->hasDecorate(DecorationInitiationIntervalINTEL)) {
42774277
std::vector<Metadata *> MetadataVec;
42784278
auto Literals =
4279-
BF->getDecorationLiterals(internal::DecorationInitiationIntervalINTEL);
4279+
BF->getDecorationLiterals(DecorationInitiationIntervalINTEL);
42804280
MetadataVec.push_back(ConstantAsMetadata::get(getUInt32(M, Literals[0])));
42814281
F->setMetadata(kSPIR2MD::InitiationInterval,
42824282
MDNode::get(*Context, MetadataVec));
42834283
}
4284-
if (BF->hasDecorate(internal::DecorationMaxConcurrencyINTEL)) {
4284+
if (BF->hasDecorate(DecorationMaxConcurrencyINTEL)) {
42854285
std::vector<Metadata *> MetadataVec;
4286-
auto Literals =
4287-
BF->getDecorationLiterals(internal::DecorationMaxConcurrencyINTEL);
4286+
auto Literals = BF->getDecorationLiterals(DecorationMaxConcurrencyINTEL);
42884287
MetadataVec.push_back(ConstantAsMetadata::get(getUInt32(M, Literals[0])));
42894288
F->setMetadata(kSPIR2MD::MaxConcurrency,
42904289
MDNode::get(*Context, MetadataVec));
42914290
}
4292-
if (BF->hasDecorate(internal::DecorationPipelineEnableINTEL)) {
4293-
auto Literals =
4294-
BF->getDecorationLiterals(internal::DecorationPipelineEnableINTEL);
4291+
if (BF->hasDecorate(DecorationPipelineEnableINTEL)) {
4292+
auto Literals = BF->getDecorationLiterals(DecorationPipelineEnableINTEL);
42954293
std::vector<Metadata *> MetadataVec;
42964294
MetadataVec.push_back(ConstantAsMetadata::get(getInt32(M, !Literals[0])));
42974295
F->setMetadata(kSPIR2MD::DisableLoopPipelining,

‎lib/SPIRV/SPIRVWriter.cpp

Lines changed: 16 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1516,43 +1516,42 @@ LLVMToSPIRVBase::getLoopControl(const BranchInst *Branch,
15161516
BM->addExtension(ExtensionID::SPV_INTEL_fpga_loop_controls);
15171517
BM->addCapability(CapabilityFPGALoopControlsINTEL);
15181518
LoopCount.Min = getMDOperandAsInt(Node, 1);
1519-
LoopControl |= spv::internal::LoopControlLoopCountINTELMask;
1519+
LoopControl |= spv::LoopControlLoopCountINTELMask;
15201520
} else if (S == "llvm.loop.intel.loopcount_max") {
15211521
BM->addExtension(ExtensionID::SPV_INTEL_fpga_loop_controls);
15221522
BM->addCapability(CapabilityFPGALoopControlsINTEL);
15231523
LoopCount.Max = getMDOperandAsInt(Node, 1);
1524-
LoopControl |= spv::internal::LoopControlLoopCountINTELMask;
1524+
LoopControl |= spv::LoopControlLoopCountINTELMask;
15251525
} else if (S == "llvm.loop.intel.loopcount_avg") {
15261526
BM->addExtension(ExtensionID::SPV_INTEL_fpga_loop_controls);
15271527
BM->addCapability(CapabilityFPGALoopControlsINTEL);
15281528
LoopCount.Avg = getMDOperandAsInt(Node, 1);
1529-
LoopControl |= spv::internal::LoopControlLoopCountINTELMask;
1529+
LoopControl |= spv::LoopControlLoopCountINTELMask;
15301530
} else if (S == "llvm.loop.intel.max_reinvocation_delay.count") {
15311531
BM->addExtension(ExtensionID::SPV_INTEL_fpga_loop_controls);
15321532
BM->addCapability(CapabilityFPGALoopControlsINTEL);
15331533
size_t I = getMDOperandAsInt(Node, 1);
15341534
ParametersToSort.emplace_back(
1535-
spv::internal::LoopControlMaxReinvocationDelayINTELMask, I);
1536-
LoopControl |=
1537-
spv::internal::LoopControlMaxReinvocationDelayINTELMask;
1535+
spv::LoopControlMaxReinvocationDelayINTELMask, I);
1536+
LoopControl |= spv::LoopControlMaxReinvocationDelayINTELMask;
15381537
}
15391538
}
15401539
}
15411540
}
1542-
if (LoopControl & spv::internal::LoopControlLoopCountINTELMask) {
1541+
if (LoopControl & spv::LoopControlLoopCountINTELMask) {
15431542
// LoopCountINTELMask have int64 literal parameters and we need to store
15441543
// int64 into 2 SPIRVWords
1545-
ParametersToSort.emplace_back(spv::internal::LoopControlLoopCountINTELMask,
1544+
ParametersToSort.emplace_back(spv::LoopControlLoopCountINTELMask,
15461545
static_cast<SPIRVWord>(LoopCount.Min));
1547-
ParametersToSort.emplace_back(spv::internal::LoopControlLoopCountINTELMask,
1546+
ParametersToSort.emplace_back(spv::LoopControlLoopCountINTELMask,
15481547
static_cast<SPIRVWord>(LoopCount.Min >> 32));
1549-
ParametersToSort.emplace_back(spv::internal::LoopControlLoopCountINTELMask,
1548+
ParametersToSort.emplace_back(spv::LoopControlLoopCountINTELMask,
15501549
static_cast<SPIRVWord>(LoopCount.Max));
1551-
ParametersToSort.emplace_back(spv::internal::LoopControlLoopCountINTELMask,
1550+
ParametersToSort.emplace_back(spv::LoopControlLoopCountINTELMask,
15521551
static_cast<SPIRVWord>(LoopCount.Max >> 32));
1553-
ParametersToSort.emplace_back(spv::internal::LoopControlLoopCountINTELMask,
1552+
ParametersToSort.emplace_back(spv::LoopControlLoopCountINTELMask,
15541553
static_cast<SPIRVWord>(LoopCount.Avg));
1555-
ParametersToSort.emplace_back(spv::internal::LoopControlLoopCountINTELMask,
1554+
ParametersToSort.emplace_back(spv::LoopControlLoopCountINTELMask,
15561555
static_cast<SPIRVWord>(LoopCount.Avg >> 32));
15571556
}
15581557
// If any loop control parameters were held back until fully collected,
@@ -2378,9 +2377,9 @@ static void transMetadataDecorations(Metadata *MD, SPIRVEntry *Target) {
23782377
ONE_STRING_DECORATION_CASE(UserSemantic, spv)
23792378
ONE_INT_DECORATION_CASE(AliasScopeINTEL, spv, SPIRVId)
23802379
ONE_INT_DECORATION_CASE(NoAliasINTEL, spv, SPIRVId)
2381-
ONE_INT_DECORATION_CASE(InitiationIntervalINTEL, spv::internal, SPIRVWord)
2382-
ONE_INT_DECORATION_CASE(MaxConcurrencyINTEL, spv::internal, SPIRVWord)
2383-
ONE_INT_DECORATION_CASE(PipelineEnableINTEL, spv::internal, SPIRVWord)
2380+
ONE_INT_DECORATION_CASE(InitiationIntervalINTEL, spv, SPIRVWord)
2381+
ONE_INT_DECORATION_CASE(MaxConcurrencyINTEL, spv, SPIRVWord)
2382+
ONE_INT_DECORATION_CASE(PipelineEnableINTEL, spv, SPIRVWord)
23842383
TWO_INT_DECORATION_CASE(FunctionRoundingModeINTEL, spv, SPIRVWord,
23852384
FPRoundingMode);
23862385
TWO_INT_DECORATION_CASE(FunctionDenormModeINTEL, spv, SPIRVWord,
@@ -2389,8 +2388,7 @@ static void transMetadataDecorations(Metadata *MD, SPIRVEntry *Target) {
23892388
FPOperationMode);
23902389
TWO_INT_DECORATION_CASE(FuseLoopsInFunctionINTEL, spv, SPIRVWord,
23912390
SPIRVWord);
2392-
TWO_INT_DECORATION_CASE(MathOpDSPModeINTEL, spv::internal, SPIRVWord,
2393-
SPIRVWord);
2391+
TWO_INT_DECORATION_CASE(MathOpDSPModeINTEL, spv, SPIRVWord, SPIRVWord);
23942392
case DecorationStallEnableINTEL: {
23952393
Target->addDecorate(new SPIRVDecorateStallEnableINTEL(Target));
23962394
break;

‎lib/SPIRV/libSPIRV/SPIRVDecorate.h

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -164,13 +164,13 @@ class SPIRVDecorate : public SPIRVDecorateGeneric {
164164
return ExtensionID::SPV_INTEL_loop_fuse;
165165
case internal::DecorationCallableFunctionINTEL:
166166
return ExtensionID::SPV_INTEL_fast_composite;
167-
case internal::DecorationMathOpDSPModeINTEL:
167+
case DecorationMathOpDSPModeINTEL:
168168
return ExtensionID::SPV_INTEL_fpga_dsp_control;
169-
case internal::DecorationInitiationIntervalINTEL:
169+
case DecorationInitiationIntervalINTEL:
170170
return ExtensionID::SPV_INTEL_fpga_invocation_pipelining_attributes;
171-
case internal::DecorationMaxConcurrencyINTEL:
171+
case DecorationMaxConcurrencyINTEL:
172172
return ExtensionID::SPV_INTEL_fpga_invocation_pipelining_attributes;
173-
case internal::DecorationPipelineEnableINTEL:
173+
case DecorationPipelineEnableINTEL:
174174
return ExtensionID::SPV_INTEL_fpga_invocation_pipelining_attributes;
175175
case internal::DecorationRuntimeAlignedINTEL:
176176
return ExtensionID::SPV_INTEL_runtime_aligned;
@@ -658,8 +658,8 @@ class SPIRVDecorateMathOpDSPModeINTEL : public SPIRVDecorate {
658658
// Complete constructor for SPIRVDecorateMathOpDSPModeINTEL
659659
SPIRVDecorateMathOpDSPModeINTEL(SPIRVEntry *TheTarget, SPIRVWord Mode,
660660
SPIRVWord Propagate)
661-
: SPIRVDecorate(spv::internal::DecorationMathOpDSPModeINTEL, TheTarget,
662-
Mode, Propagate){};
661+
: SPIRVDecorate(spv::DecorationMathOpDSPModeINTEL, TheTarget, Mode,
662+
Propagate){};
663663
};
664664

665665
class SPIRVDecorateAliasScopeINTEL : public SPIRVDecorateId {
@@ -680,24 +680,23 @@ class SPIRVDecorateInitiationIntervalINTEL : public SPIRVDecorate {
680680
public:
681681
// Complete constructor for SPIRVDecorateInitiationIntervalINTEL
682682
SPIRVDecorateInitiationIntervalINTEL(SPIRVEntry *TheTarget, SPIRVWord Cycles)
683-
: SPIRVDecorate(spv::internal::DecorationInitiationIntervalINTEL,
684-
TheTarget, Cycles){};
683+
: SPIRVDecorate(spv::DecorationInitiationIntervalINTEL, TheTarget,
684+
Cycles){};
685685
};
686686

687687
class SPIRVDecorateMaxConcurrencyINTEL : public SPIRVDecorate {
688688
public:
689689
// Complete constructor for SPIRVDecorateMaxConcurrencyINTEL
690690
SPIRVDecorateMaxConcurrencyINTEL(SPIRVEntry *TheTarget, SPIRVWord Invocations)
691-
: SPIRVDecorate(spv::internal::DecorationMaxConcurrencyINTEL, TheTarget,
691+
: SPIRVDecorate(spv::DecorationMaxConcurrencyINTEL, TheTarget,
692692
Invocations){};
693693
};
694694

695695
class SPIRVDecoratePipelineEnableINTEL : public SPIRVDecorate {
696696
public:
697697
// Complete constructor for SPIRVDecoratePipelineEnableINTEL
698698
SPIRVDecoratePipelineEnableINTEL(SPIRVEntry *TheTarget, SPIRVWord Enable)
699-
: SPIRVDecorate(spv::internal::DecorationPipelineEnableINTEL, TheTarget,
700-
Enable){};
699+
: SPIRVDecorate(spv::DecorationPipelineEnableINTEL, TheTarget, Enable){};
701700
};
702701

703702
class SPIRVDecorateHostAccessINTEL : public SPIRVDecorate {

‎lib/SPIRV/libSPIRV/SPIRVEnum.h

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -434,16 +434,15 @@ template <> inline void SPIRVMap<Decoration, SPIRVCapVec>::init() {
434434
ADD_VEC_INIT(DecorationStallEnableINTEL,
435435
{CapabilityFPGAClusterAttributesINTEL});
436436
ADD_VEC_INIT(DecorationFuseLoopsInFunctionINTEL, {CapabilityLoopFuseINTEL});
437-
ADD_VEC_INIT(internal::DecorationMathOpDSPModeINTEL,
438-
{internal::CapabilityFPGADSPControlINTEL});
439-
ADD_VEC_INIT(internal::DecorationInitiationIntervalINTEL,
440-
{internal::CapabilityFPGAInvocationPipeliningAttributesINTEL});
441-
ADD_VEC_INIT(internal::DecorationMaxConcurrencyINTEL,
442-
{internal::CapabilityFPGAInvocationPipeliningAttributesINTEL});
443-
ADD_VEC_INIT(internal::DecorationPipelineEnableINTEL,
444-
{internal::CapabilityFPGAInvocationPipeliningAttributesINTEL});
437+
ADD_VEC_INIT(DecorationMathOpDSPModeINTEL, {CapabilityFPGADSPControlINTEL});
438+
ADD_VEC_INIT(DecorationInitiationIntervalINTEL,
439+
{CapabilityFPGAInvocationPipeliningAttributesINTEL});
440+
ADD_VEC_INIT(DecorationMaxConcurrencyINTEL,
441+
{CapabilityFPGAInvocationPipeliningAttributesINTEL});
442+
ADD_VEC_INIT(DecorationPipelineEnableINTEL,
443+
{CapabilityFPGAInvocationPipeliningAttributesINTEL});
445444
ADD_VEC_INIT(internal::DecorationRuntimeAlignedINTEL,
446-
{internal::CapabilityRuntimeAlignedAttributeINTEL});
445+
{CapabilityRuntimeAlignedAttributeINTEL});
447446
ADD_VEC_INIT(internal::DecorationHostAccessINTEL,
448447
{internal::CapabilityGlobalVariableDecorationsINTEL});
449448
ADD_VEC_INIT(internal::DecorationInitModeINTEL,

‎lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -179,13 +179,13 @@ template <> inline void SPIRVMap<Decoration, std::string>::init() {
179179
add(DecorationMediaBlockIOINTEL, "MediaBlockIOINTEL");
180180
add(DecorationAliasScopeINTEL, "AliasScopeINTEL");
181181
add(DecorationNoAliasINTEL, "NoAliasINTEL");
182+
add(DecorationMathOpDSPModeINTEL, "MathOpDSPModeINTEL");
183+
add(DecorationInitiationIntervalINTEL, "InitiationIntervalINTEL");
184+
add(DecorationMaxConcurrencyINTEL, "MaxConcurrencyINTEL");
185+
add(DecorationPipelineEnableINTEL, "PipelineEnableINTEL");
182186

183187
// From spirv_internal.hpp
184188
add(internal::DecorationCallableFunctionINTEL, "CallableFunctionINTEL");
185-
add(internal::DecorationMathOpDSPModeINTEL, "MathOpDSPModeINTEL");
186-
add(internal::DecorationInitiationIntervalINTEL, "InitiationIntervalINTEL");
187-
add(internal::DecorationMaxConcurrencyINTEL, "MaxConcurrencyINTEL");
188-
add(internal::DecorationPipelineEnableINTEL, "PipelineEnableINTEL");
189189
add(internal::DecorationRuntimeAlignedINTEL, "RuntimeAlignedINTEL");
190190
add(internal::DecorationHostAccessINTEL, "HostAccessINTEL");
191191
add(internal::DecorationInitModeINTEL, "InitModeINTEL");
@@ -597,17 +597,16 @@ template <> inline void SPIRVMap<Capability, std::string>::init() {
597597
add(CapabilityDebugInfoModuleINTEL, "DebugInfoModuleINTEL");
598598
add(CapabilitySplitBarrierINTEL, "SplitBarrierINTEL");
599599
add(CapabilityGroupUniformArithmeticKHR, "GroupUniformArithmeticKHR");
600+
add(CapabilityFPGADSPControlINTEL, "FPGADSPControlINTEL");
601+
add(CapabilityFPGAInvocationPipeliningAttributesINTEL,
602+
"FPGAInvocationPipeliningAttributesINTEL");
603+
add(CapabilityRuntimeAlignedAttributeINTEL, "RuntimeAlignedAttributeINTEL");
604+
add(CapabilityMax, "Max");
600605

601606
// From spirv_internal.hpp
602-
add(internal::CapabilityFPGADSPControlINTEL, "FPGADSPControlINTEL");
603607
add(internal::CapabilityFastCompositeINTEL, "FastCompositeINTEL");
604608
add(internal::CapabilityOptNoneINTEL, "OptNoneINTEL");
605-
add(internal::CapabilityFPGAInvocationPipeliningAttributesINTEL,
606-
"FPGAInvocationPipeliningAttributesINTEL");
607609
add(internal::CapabilityTokenTypeINTEL, "TokenTypeINTEL");
608-
add(internal::CapabilityRuntimeAlignedAttributeINTEL,
609-
"RuntimeAlignedAttributeINTEL");
610-
add(CapabilityMax, "Max");
611610
add(internal::CapabilityFPArithmeticFenceINTEL, "FPArithmeticFenceINTEL");
612611
add(internal::CapabilityBfloat16ConversionINTEL, "Bfloat16ConversionINTEL");
613612
add(internal::CapabilityJointMatrixINTEL, "JointMatrixINTEL");

‎lib/SPIRV/libSPIRV/spirv_internal.hpp

Lines changed: 0 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -54,10 +54,6 @@ enum InternalOp {
5454
};
5555

5656
enum InternalDecoration {
57-
IDecMathOpDSPModeINTEL = 5909,
58-
IDecInitiationIntervalINTEL = 5917,
59-
IDecMaxConcurrencyINTEL = 5918,
60-
IDecPipelineEnableINTEL = 5919,
6157
IDecRuntimeAlignedINTEL = 5940,
6258
IDecCallableFunctionINTEL = 6087,
6359
IDecHostAccessINTEL = 6147,
@@ -67,9 +63,6 @@ enum InternalDecoration {
6763
};
6864

6965
enum InternalCapability {
70-
ICapFPGADSPControlINTEL = 5908,
71-
ICapFPGAInvocationPipeliningAttributesINTEL = 5916,
72-
ICapRuntimeAlignedAttributeINTEL = 5939,
7366
ICapFastCompositeINTEL = 6093,
7467
ICapOptNoneINTEL = 6094,
7568
ICapTokenTypeINTEL = 6112,
@@ -91,11 +84,6 @@ enum InternalExecutionMode {
9184
IExecModeStreamingInterfaceINTEL = 6154
9285
};
9386

94-
enum InternalLoopControlMask {
95-
ILoopControlLoopCountINTELMask = 0x1000000,
96-
ILoopControlMaxReinvocationDelayINTELMask = 0x2000000
97-
};
98-
9987
constexpr LinkageType LinkageTypeInternal =
10088
static_cast<LinkageType>(ILTInternal);
10189

@@ -144,12 +132,6 @@ constexpr Op OpArithmeticFenceINTEL = static_cast<Op>(IOpArithmeticFenceINTEL);
144132
constexpr Op OpConvertFToBF16INTEL = static_cast<Op>(IOpConvertFToBF16INTEL);
145133
constexpr Op OpConvertBF16ToFINTEL = static_cast<Op>(IOpConvertBF16ToFINTEL);
146134

147-
constexpr Decoration DecorationInitiationIntervalINTEL =
148-
static_cast<Decoration>(IDecInitiationIntervalINTEL);
149-
constexpr Decoration DecorationMaxConcurrencyINTEL =
150-
static_cast<Decoration>(IDecMaxConcurrencyINTEL);
151-
constexpr Decoration DecorationPipelineEnableINTEL =
152-
static_cast<Decoration>(IDecPipelineEnableINTEL);
153135
constexpr Decoration DecorationCallableFunctionINTEL =
154136
static_cast<Decoration>(IDecCallableFunctionINTEL);
155137
constexpr Decoration DecorationRuntimeAlignedINTEL =
@@ -167,14 +149,8 @@ constexpr Capability CapabilityFastCompositeINTEL =
167149
static_cast<Capability>(ICapFastCompositeINTEL);
168150
constexpr Capability CapabilityOptNoneINTEL =
169151
static_cast<Capability>(ICapOptNoneINTEL);
170-
constexpr Capability CapabilityFPGADSPControlINTEL =
171-
static_cast<Capability>(ICapFPGADSPControlINTEL);
172-
constexpr Capability CapabilityFPGAInvocationPipeliningAttributesINTEL =
173-
static_cast<Capability>(ICapFPGAInvocationPipeliningAttributesINTEL);
174152
constexpr Capability CapabilityTokenTypeINTEL =
175153
static_cast<Capability>(ICapTokenTypeINTEL);
176-
constexpr Capability CapabilityRuntimeAlignedAttributeINTEL =
177-
static_cast<Capability>(ICapRuntimeAlignedAttributeINTEL);
178154
constexpr Capability CapabilityFPArithmeticFenceINTEL =
179155
static_cast<Capability>(ICapFPArithmeticFenceINTEL);
180156
constexpr Capability CapabilityBfloat16ConversionINTEL =
@@ -185,19 +161,11 @@ constexpr Capability CapabilityGlobalVariableDecorationsINTEL =
185161
constexpr FunctionControlMask FunctionControlOptNoneINTELMask =
186162
static_cast<FunctionControlMask>(IFunctionControlOptNoneINTELMask);
187163

188-
constexpr Decoration DecorationMathOpDSPModeINTEL =
189-
static_cast<Decoration>(IDecMathOpDSPModeINTEL);
190-
191164
constexpr ExecutionMode ExecutionModeFastCompositeKernelINTEL =
192165
static_cast<ExecutionMode>(IExecModeFastCompositeKernelINTEL);
193166
constexpr ExecutionMode ExecutionModeStreamingInterfaceINTEL =
194167
static_cast<ExecutionMode>(IExecModeStreamingInterfaceINTEL);
195168

196-
static const LoopControlMask LoopControlLoopCountINTELMask =
197-
static_cast<LoopControlMask>(ILoopControlLoopCountINTELMask);
198-
static const LoopControlMask LoopControlMaxReinvocationDelayINTELMask =
199-
static_cast<LoopControlMask>(ILoopControlMaxReinvocationDelayINTELMask);
200-
201169
} // namespace internal
202170
} // namespace spv
203171

‎spirv-headers-tag.conf

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
5a121866927a16ab9d49bed4788b532c7fcea766
1+
c214f6f2d1a7253bb0e9f195c2dc5b0659dc99ef

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