16
16
17
17
#include <stdlib.h>
18
18
#include <string.h>
19
- #include <stdio.h>
19
+ // #include <stdio.h>
20
+ #include <stdint.h>
20
21
21
- #include "address_space.h"
22
- #include "timeline.h"
23
22
#include "processor.h"
24
23
25
24
26
25
#define UNDEFINED (0xCCCCCCCCCCCCCCCC)
27
26
28
27
29
28
static void
30
- trap (Processor * p , Uint64_t cause ) {
29
+ trap (Processor * p , uint64_t cause ) {
31
30
/* KCP53000 only supports M-mode, so we can hardwire the
32
31
* MPP bits of mstatus.
33
32
*/
34
- Uint64_t newstat = p -> mstatus & 0xFFFFFFFFFFFFE777 ;
33
+ uint64_t newstat = p -> mstatus & 0xFFFFFFFFFFFFE777 ;
35
34
newstat |= (p -> mstatus & 0x8 ) << 4 ;
36
35
37
36
p -> mcause = cause ;
@@ -130,7 +129,7 @@ ecall(Processor *p) {
130
129
131
130
static void
132
131
mret (Processor * p ) {
133
- Uint64_t new_mie = (p -> mstatus & 0x80 ) >> 4 ;
132
+ uint64_t new_mie = (p -> mstatus & 0x80 ) >> 4 ;
134
133
p -> mstatus = (p -> mstatus & 0xFFFFFFFFFFFE0F77 ) | new_mie | 0x1880 ;
135
134
p -> pc = p -> mepc ;
136
135
}
@@ -161,11 +160,13 @@ new_processor(AddressSpace *as) {
161
160
162
161
163
162
void
164
- step (Processor * p , Timeline * t ) {
163
+ step (Processor * p ) {
165
164
int32_t ir ;
166
165
int opc , rd , fn3 , rs1 , rs2 , imm12 , imm12s , disp12 ;
167
166
int64_t imm20 , disp20 , ia ;
168
- Uint64_t mask , v ;
167
+ uint64_t mask , v ;
168
+ AddressSpace * as = p -> as ;
169
+ IAddressSpace * asi = as -> i ;
169
170
170
171
/* If service from the virtual machine monitor is required,
171
172
* return to the VMM until it has been properly serviced.
@@ -186,18 +187,17 @@ step(Processor *p, Timeline *t) {
186
187
mask = (p -> mstatus & MSTATUSF_MIE ) ?
187
188
p -> mip & p -> mie : 0 ;
188
189
if (mask & MIEF_MEIE ) {
189
- trap (p , MCAUSEF_IRQ | MEIB_MEIE );
190
+ trap (p , MCAUSEF_IRQ | MIEB_MEIE );
190
191
}
191
192
else if (mask & MIEF_MSIE ) {
192
- trap (p , MCAUSEF_IRQ | MEIB_MSIE );
193
+ trap (p , MCAUSEF_IRQ | MIEB_MSIE );
193
194
}
194
195
else if (mask & MIEF_MTIE ) {
195
- trap (p , MCAUSEF_IRQ | MEIB_MTIE );
196
+ trap (p , MCAUSEF_IRQ | MIEB_MTIE );
196
197
}
197
198
198
- ir = as -> fetch_word (p -> as , ia );
199
+ ir = asi -> fetch_word (p -> as , ia );
199
200
p -> pc = ia + 4 ;
200
- tt -> step (t , 2 ); /* 32-bit fetches take 2 cycles over 16-bit bus. */
201
201
202
202
/* This takes a bunch of time. */
203
203
opc = ir & 0x7F ;
@@ -280,16 +280,16 @@ step(Processor *p, Timeline *t) {
280
280
281
281
case 6 : /* BLTU */
282
282
if (
283
- (Uint64_t )(p -> x [rs1 ]) <
284
- (Uint64_t )(p -> x [rs2 ])
283
+ (uint64_t )(p -> x [rs1 ]) <
284
+ (uint64_t )(p -> x [rs2 ])
285
285
)
286
286
p -> pc = ia + disp12 ;
287
287
break ;
288
288
289
289
case 7 : /* BGEU */
290
290
if (
291
- (Uint64_t )(p -> x [rs1 ]) >=
292
- (Uint64_t )(p -> x [rs2 ])
291
+ (uint64_t )(p -> x [rs1 ]) >=
292
+ (uint64_t )(p -> x [rs2 ])
293
293
)
294
294
p -> pc = ia + disp12 ;
295
295
break ;
@@ -300,102 +300,90 @@ step(Processor *p, Timeline *t) {
300
300
case 0x03 :
301
301
switch (fn3 ) {
302
302
case 0 : /* LB */
303
- p -> x [rd ] = as -> fetch_byte (
303
+ p -> x [rd ] = asi -> fetch_byte (
304
304
p -> as , p -> x [rs1 ] + imm12
305
305
);
306
306
p -> x [rd ] |= - (p -> x [rd ] & 0x80 );
307
- tt -> step (t , 1 );
308
307
break ;
309
308
310
309
case 1 : /* LH */
311
- p -> x [rd ] = as -> fetch_hword (
310
+ p -> x [rd ] = asi -> fetch_hword (
312
311
p -> as , p -> x [rs1 ] + imm12
313
312
);
314
313
p -> x [rd ] |= - (p -> x [rd ] & 0x8000 );
315
- tt -> step (t , 1 );
316
314
break ;
317
315
318
316
case 2 : /* LW */
319
- p -> x [rd ] = as -> fetch_word (
317
+ p -> x [rd ] = asi -> fetch_word (
320
318
p -> as , p -> x [rs1 ] + imm12
321
319
);
322
320
p -> x [rd ] |= - (p -> x [rd ] & 0x80000000 );
323
- tt -> step (t , 2 );
324
321
break ;
325
322
326
323
case 3 : /* LD */
327
- p -> x [rd ] = as -> fetch_dword (
324
+ p -> x [rd ] = asi -> fetch_dword (
328
325
p -> as , p -> x [rs1 ] + imm12
329
326
);
330
- tt -> step (t , 4 );
331
327
break ;
332
328
333
329
case 4 : /* LBU */
334
- p -> x [rd ] = as -> fetch_byte (
330
+ p -> x [rd ] = asi -> fetch_byte (
335
331
p -> as , p -> x [rs1 ] + imm12
336
332
);
337
- tt -> step (t , 1 );
338
333
break ;
339
334
340
335
case 5 : /* LHU */
341
- p -> x [rd ] = as -> fetch_hword (
336
+ p -> x [rd ] = asi -> fetch_hword (
342
337
p -> as , p -> x [rs1 ] + imm12
343
338
);
344
- tt -> step (t , 1 );
345
339
break ;
346
340
347
341
case 6 : /* LWU */
348
- p -> x [rd ] = as -> fetch_word (
342
+ p -> x [rd ] = asi -> fetch_word (
349
343
p -> as , p -> x [rs1 ] + imm12
350
344
);
351
- tt -> step (t , 2 );
352
345
break ;
353
346
354
347
case 7 : /* LDU */
355
- p -> x [rd ] = as -> fetch_dword (
356
- p -> as , p -> x [rs1 ] + imm12 '
348
+ p -> x [rd ] = asi -> fetch_dword (
349
+ p -> as , p -> x [rs1 ] + imm12
357
350
);
358
- tt -> step (t , 4 );
359
351
break ;
360
352
}
361
353
break ;
362
354
/* Sx */
363
355
case 0x23 :
364
356
switch (fn3 ) {
365
357
case 0 : /* SB */
366
- as -> store_byte (
358
+ asi -> store_byte (
367
359
p -> as ,
368
360
p -> x [rs1 ]+ imm12s ,
369
361
p -> x [rs2 ]
370
362
);
371
- tt -> step (t , 1 );
372
363
break ;
373
364
374
365
case 1 : /* SH */
375
- as -> store_hword (
366
+ asi -> store_hword (
376
367
p -> as ,
377
368
p -> x [rs1 ]+ imm12s ,
378
369
p -> x [rs2 ]
379
370
);
380
- tt -> step (t , 1 );
381
371
break ;
382
372
383
373
case 2 : /* SW */
384
- as -> store_word (
374
+ asi -> store_word (
385
375
p -> as ,
386
376
p -> x [rs1 ]+ imm12s ,
387
377
p -> x [rs2 ]
388
378
);
389
- tt -> step (t , 2 );
390
379
break ;
391
380
392
381
case 3 : /* SD */
393
- as -> store_dword (
382
+ asi -> store_dword (
394
383
p -> as ,
395
384
p -> x [rs1 ]+ imm12s ,
396
385
p -> x [rs2 ]
397
386
);
398
- tt -> step (t , 4 );
399
387
break ;
400
388
401
389
default :
@@ -421,7 +409,7 @@ step(Processor *p, Timeline *t) {
421
409
422
410
case 3 : /* SLTIU */
423
411
p -> x [rd ] =
424
- (Uint64_t )p -> x [rs1 ] < (Uint64_t )imm12 ;
412
+ (uint64_t )p -> x [rs1 ] < (uint64_t )imm12 ;
425
413
break ;
426
414
427
415
case 4 : /* XORI */
@@ -435,7 +423,7 @@ step(Processor *p, Timeline *t) {
435
423
}
436
424
else {
437
425
p -> x [rd ] =
438
- (Uint64_t )p -> x [rs1 ] >> (Uint64_t )imm12 ;
426
+ (uint64_t )p -> x [rs1 ] >> (uint64_t )imm12 ;
439
427
}
440
428
break ;
441
429
@@ -548,7 +536,7 @@ step(Processor *p, Timeline *t) {
548
536
549
537
case 3 : /* SLTU */
550
538
p -> x [rd ] =
551
- (Uint64_t )p -> x [rs1 ] < (Uint64_t )p -> x [rs2 ];
539
+ (uint64_t )p -> x [rs1 ] < (uint64_t )p -> x [rs2 ];
552
540
break ;
553
541
554
542
case 4 : /* XOR */
@@ -562,8 +550,8 @@ step(Processor *p, Timeline *t) {
562
550
}
563
551
else {
564
552
p -> x [rd ] =
565
- (Uint64_t )p -> x [rs1 ] >>
566
- (Uint64_t )p -> x [rs2 ];
553
+ (uint64_t )p -> x [rs1 ] >>
554
+ (uint64_t )p -> x [rs2 ];
567
555
}
568
556
break ;
569
557
0 commit comments