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Commit 7c9f0f3

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Implement RAM, get DX-Forth image to start execution.
1 parent 5e5ea6e commit 7c9f0f3

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3 files changed

+163
-15
lines changed

3 files changed

+163
-15
lines changed

software/src/e2/all.do

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
redo-ifchange e2
1+
redo-ifchange e2 rom-image.bin

software/src/e2/dxforth/dxforth.asm.m4

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,8 +31,8 @@ _bios_copy:
3131
blt a0,a1,_bios_copy
3232

3333
_bios_boot:
34-
ld a2,_n3-_bios_entry(gp)
35-
jalr x0,0(a2)
34+
lw D,_n3-_bios_entry(gp)
35+
jalr x0,0(D)
3636

3737
_n1: word _start
3838
_n2: word _end

software/src/e2/main.c

Lines changed: 160 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -17,11 +17,12 @@ struct Segment {
1717
struct RootAS {
1818
AddressSpace as;
1919
Segment rom_seg;
20+
Segment ram_seg;
2021
};
2122

2223

2324
uint64_t
24-
rom_fetch_dword(AddressSpace *as, uint64_t addr) {
25+
mem_fetch_dword(AddressSpace *as, uint64_t addr) {
2526
Segment *s = (Segment *)as;
2627
int i;
2728

@@ -44,7 +45,7 @@ rom_fetch_dword(AddressSpace *as, uint64_t addr) {
4445
}
4546

4647
uint32_t
47-
rom_fetch_word(AddressSpace *as, uint64_t addr) {
48+
mem_fetch_word(AddressSpace *as, uint64_t addr) {
4849
Segment *s = (Segment *)as;
4950
int i;
5051

@@ -60,10 +61,11 @@ rom_fetch_word(AddressSpace *as, uint64_t addr) {
6061
| (s->image[i+2] << 16)
6162
| (s->image[i+3] << 24)
6263
);
63-
}
64+
};
65+
6466

6567
uint16_t
66-
rom_fetch_hword(AddressSpace *as, uint64_t addr) {
68+
mem_fetch_hword(AddressSpace *as, uint64_t addr) {
6769
Segment *s = (Segment *)as;
6870
int i;
6971

@@ -80,7 +82,7 @@ rom_fetch_hword(AddressSpace *as, uint64_t addr) {
8082
}
8183

8284
uint8_t
83-
rom_fetch_byte(AddressSpace *as, uint64_t addr) {
85+
mem_fetch_byte(AddressSpace *as, uint64_t addr) {
8486
Segment *s = (Segment *)as;
8587
int i;
8688

@@ -117,25 +119,101 @@ rom_store_byte(AddressSpace *as, uint64_t addr, uint8_t datum) {
117119
/* Do nothing, for we are ROM. */
118120
}
119121

122+
void
123+
ram_store_dword(AddressSpace *as, uint64_t addr, uint64_t datum) {
124+
Segment *s = (Segment *)as;
125+
int i;
126+
127+
if(addr & 7) {
128+
fprintf(stderr, "TODO: raise a misalignment trap to the processor\n");
129+
}
130+
131+
i = (int)(addr - s->bottom);
132+
s->image[i] = (uint8_t)(datum & 0xFF);
133+
s->image[i+1] = (uint8_t)((datum >> 8) & 0xFF);
134+
s->image[i+2] = (uint8_t)((datum >> 16) & 0xFF);
135+
s->image[i+3] = (uint8_t)((datum >> 24) & 0xFF);
136+
s->image[i+4] = (uint8_t)((datum >> 32) & 0xFF);
137+
s->image[i+5] = (uint8_t)((datum >> 40) & 0xFF);
138+
s->image[i+6] = (uint8_t)((datum >> 48) & 0xFF);
139+
s->image[i+7] = (uint8_t)((datum >> 56) & 0xFF);
140+
}
141+
142+
void
143+
ram_store_word(AddressSpace *as, uint64_t addr, uint32_t datum) {
144+
Segment *s = (Segment *)as;
145+
int i;
146+
147+
if(addr & 3) {
148+
fprintf(stderr, "TODO: raise a misalignment trap to the processor\n");
149+
}
150+
151+
i = (int)(addr - s->bottom);
152+
s->image[i] = (uint8_t)(datum & 0xFF);
153+
s->image[i+1] = (uint8_t)((datum >> 8) & 0xFF);
154+
s->image[i+2] = (uint8_t)((datum >> 16) & 0xFF);
155+
s->image[i+3] = (uint8_t)((datum >> 24) & 0xFF);
156+
}
157+
158+
void
159+
ram_store_hword(AddressSpace *as, uint64_t addr, uint16_t datum) {
160+
Segment *s = (Segment *)as;
161+
int i;
162+
163+
if(addr & 1) {
164+
fprintf(stderr, "TODO: raise a misalignment trap to the processor\n");
165+
}
166+
167+
i = (int)(addr - s->bottom);
168+
s->image[i] = (uint8_t)(datum & 0xFF);
169+
s->image[i+1] = (uint8_t)((datum >> 8) & 0xFF);
170+
}
171+
172+
void
173+
ram_store_byte(AddressSpace *as, uint64_t addr, uint8_t datum) {
174+
Segment *s = (Segment *)as;
175+
int i;
176+
177+
i = (int)(addr - s->bottom);
178+
s->image[i] = datum;
179+
}
180+
120181
struct IAddressSpace rom_segment_interface = {
121-
.fetch_dword = rom_fetch_dword,
122-
.fetch_word = rom_fetch_word,
123-
.fetch_hword = rom_fetch_hword,
124-
.fetch_byte = rom_fetch_byte,
182+
.fetch_dword = mem_fetch_dword,
183+
.fetch_word = mem_fetch_word,
184+
.fetch_hword = mem_fetch_hword,
185+
.fetch_byte = mem_fetch_byte,
125186
.store_dword = rom_store_dword,
126187
.store_word = rom_store_word,
127188
.store_hword = rom_store_hword,
128189
.store_byte = rom_store_byte,
129190
};
130191

131192

193+
struct IAddressSpace ram_segment_interface = {
194+
.fetch_dword = mem_fetch_dword,
195+
.fetch_word = mem_fetch_word,
196+
.fetch_hword = mem_fetch_hword,
197+
.fetch_byte = mem_fetch_byte,
198+
.store_dword = ram_store_dword,
199+
.store_word = ram_store_word,
200+
.store_hword = ram_store_hword,
201+
.store_byte = ram_store_byte,
202+
};
203+
204+
132205
uint64_t
133206
root_fetch_dword(AddressSpace *as, uint64_t addr) {
134207
RootAS *root = (RootAS *)as;
135208

209+
fprintf(stderr, "$%016llX @D\n", addr);
210+
136211
if((root->rom_seg.bottom <= addr) && (addr < root->rom_seg.top))
137212
return root->rom_seg.as.i->fetch_dword(&root->rom_seg.as, addr);
138213

214+
if((root->ram_seg.bottom <= addr) && (addr < root->ram_seg.top))
215+
return root->ram_seg.as.i->fetch_dword(&root->ram_seg.as, addr);
216+
139217
fprintf(stderr, "TODO: raise access error trap to CPU\n");
140218
return 0xCCCCCCCCCCCCCCCC;
141219
}
@@ -144,9 +222,14 @@ uint32_t
144222
root_fetch_word(AddressSpace *as, uint64_t addr) {
145223
RootAS *root = (RootAS *)as;
146224

225+
fprintf(stderr, "$%016llX @W\n", addr);
226+
147227
if((root->rom_seg.bottom <= addr) && (addr < root->rom_seg.top))
148228
return root->rom_seg.as.i->fetch_word(&root->rom_seg.as, addr);
149229

230+
if((root->ram_seg.bottom <= addr) && (addr < root->ram_seg.top))
231+
return root->ram_seg.as.i->fetch_word(&root->ram_seg.as, addr);
232+
150233
fprintf(stderr, "TODO: raise access error trap to CPU\n");
151234
return 0xCCCCCCCC;
152235
}
@@ -155,8 +238,13 @@ uint16_t
155238
root_fetch_hword(AddressSpace *as, uint64_t addr) {
156239
RootAS *root = (RootAS *)as;
157240

241+
fprintf(stderr, "$%016llX @H\n", addr);
242+
158243
if((root->rom_seg.bottom <= addr) && (addr < root->rom_seg.top))
159-
return root->rom_seg.as.i->fetch_dword(&root->rom_seg.as, addr);
244+
return root->rom_seg.as.i->fetch_hword(&root->rom_seg.as, addr);
245+
246+
if((root->ram_seg.bottom <= addr) && (addr < root->ram_seg.top))
247+
return root->ram_seg.as.i->fetch_hword(&root->ram_seg.as, addr);
160248

161249
fprintf(stderr, "TODO: raise access error trap to CPU\n");
162250
return 0xCCCC;
@@ -166,8 +254,13 @@ uint8_t
166254
root_fetch_byte(AddressSpace *as, uint64_t addr) {
167255
RootAS *root = (RootAS *)as;
168256

257+
fprintf(stderr, "$%016llX @B\n", addr);
258+
169259
if((root->rom_seg.bottom <= addr) && (addr < root->rom_seg.top))
170-
return root->rom_seg.as.i->fetch_dword(&root->rom_seg.as, addr);
260+
return root->rom_seg.as.i->fetch_byte(&root->rom_seg.as, addr);
261+
262+
if((root->ram_seg.bottom <= addr) && (addr < root->ram_seg.top))
263+
return root->ram_seg.as.i->fetch_byte(&root->ram_seg.as, addr);
171264

172265
fprintf(stderr, "TODO: raise access error trap to CPU\n");
173266
return 0xCC;
@@ -177,47 +270,75 @@ void
177270
root_store_dword(AddressSpace *as, uint64_t addr, uint64_t datum) {
178271
RootAS *root = (RootAS *)as;
179272

273+
fprintf(stderr, "$%016llX $%016llX !D\n", datum, addr);
274+
180275
if((root->rom_seg.bottom <= addr) && (addr < root->rom_seg.top)) {
181276
root->rom_seg.as.i->store_dword(&root->rom_seg.as, addr, datum);
182277
return;
183278
}
184279

280+
if((root->ram_seg.bottom <= addr) && (addr < root->ram_seg.top)) {
281+
root->ram_seg.as.i->store_dword(&root->ram_seg.as, addr, datum);
282+
return;
283+
}
284+
185285
fprintf(stderr, "TODO: raise access error trap to CPU\n");
186286
}
187287

188288
void
189289
root_store_word(AddressSpace *as, uint64_t addr, uint32_t datum) {
190290
RootAS *root = (RootAS *)as;
191291

292+
fprintf(stderr, "$%08lX $%016llX !W\n", datum, addr);
293+
192294
if((root->rom_seg.bottom <= addr) && (addr < root->rom_seg.top)) {
193295
root->rom_seg.as.i->store_word(&root->rom_seg.as, addr, datum);
194296
return;
195297
}
196298

299+
if((root->ram_seg.bottom <= addr) && (addr < root->ram_seg.top)) {
300+
root->ram_seg.as.i->store_word(&root->ram_seg.as, addr, datum);
301+
return;
302+
}
303+
197304
fprintf(stderr, "TODO: raise access error trap to CPU\n");
198305
}
199306

200307
void
201308
root_store_hword(AddressSpace *as, uint64_t addr, uint16_t datum) {
202309
RootAS *root = (RootAS *)as;
203310

311+
fprintf(stderr, "$%04X $%016llX !H\n", datum, addr);
312+
204313
if((root->rom_seg.bottom <= addr) && (addr < root->rom_seg.top)) {
205314
root->rom_seg.as.i->store_hword(&root->rom_seg.as, addr, datum);
206315
return;
207316
}
208317

318+
if((root->ram_seg.bottom <= addr) && (addr < root->ram_seg.top)) {
319+
root->ram_seg.as.i->store_hword(&root->ram_seg.as, addr, datum);
320+
return;
321+
}
322+
209323
fprintf(stderr, "TODO: raise access error trap to CPU\n");
210324
}
211325

212326
void
213327
root_store_byte(AddressSpace *as, uint64_t addr, uint8_t datum) {
214328
RootAS *root = (RootAS *)as;
215329

330+
fprintf(stderr, "$%02X $%016llX !B\n", datum, addr);
331+
216332
if((root->rom_seg.bottom <= addr) && (addr < root->rom_seg.top)) {
217333
root->rom_seg.as.i->store_byte(&root->rom_seg.as, addr, datum);
218334
return;
219335
}
220336

337+
if((root->ram_seg.bottom <= addr) && (addr < root->ram_seg.top)) {
338+
root->ram_seg.as.i->store_byte(&root->ram_seg.as, addr, datum);
339+
return;
340+
}
341+
221342
fprintf(stderr, "TODO: raise access error trap to CPU\n");
222343
}
223344

@@ -236,26 +357,53 @@ void
236357
dispose_root_address_space(RootAS *ras) {
237358
if(ras) {
238359
if(ras->rom_seg.image) free(ras->rom_seg.image);
360+
if(ras->ram_seg.image) free(ras->ram_seg.image);
239361
free(ras);
240362
}
241363
}
242364

243365
RootAS *
244366
new_root_address_space(void) {
245367
RootAS *ras = (RootAS *)(malloc(sizeof(RootAS)));
368+
FILE *fh;
369+
size_t size, actual;
370+
246371
if(ras) {
247372
memset(ras, 0, sizeof(RootAS));
248373
ras->as.i = &root_interface;
249374

250375
ras->rom_seg.as.i = &rom_segment_interface;
251376
ras->rom_seg.bottom = 0x0000000000000000;
252377
ras->rom_seg.top = 0x0000000000100000;
253-
ras->rom_seg.image = malloc(ras->rom_seg.top - ras->rom_seg.bottom);
378+
size = ras->rom_seg.top - ras->rom_seg.bottom;
379+
ras->rom_seg.image = malloc(size);
254380
if(!ras->rom_seg.image) {
255381
fprintf(stderr, "cannot allocate 1MB ROM image\n");
256382
dispose_root_address_space(ras);
257383
return NULL;
258384
}
385+
memset(ras->rom_seg.image, 0xAA, size);
386+
fh = fopen("rom-image.bin", "rb");
387+
if(!fh) {
388+
fprintf(stderr, "cannot read rom-image.bin\n");
389+
dispose_root_address_space(ras);
390+
return NULL;
391+
}
392+
actual = fread(ras->rom_seg.image, 1, size, fh);
393+
if(actual < size) {
394+
fprintf(stderr, "WARNING: Expected %d byte file, but got %d.\n", size, actual);
395+
}
396+
fclose(fh);
397+
398+
ras->ram_seg.as.i = &ram_segment_interface;
399+
ras->ram_seg.bottom = 0x0000000040000000;
400+
ras->ram_seg.top = 0x0000000040100000;
401+
ras->ram_seg.image = malloc(ras->ram_seg.top - ras->ram_seg.bottom);
402+
if(!ras->ram_seg.image) {
403+
fprintf(stderr, "cannot allocate 1MB RAM image\n");
404+
dispose_root_address_space(ras);
405+
return NULL;
406+
}
259407
}
260408
return ras;
261409
}

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