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When there is a secondary processor, decoder logic is out of sync. #81

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kongty opened this issue Apr 14, 2020 · 0 comments
Open

When there is a secondary processor, decoder logic is out of sync. #81

kongty opened this issue Apr 14, 2020 · 0 comments

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@kongty
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kongty commented Apr 14, 2020 •
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When there are two processor interfaces, decoder logic is out of sync when using parallel mode.

address and data signals are synced to one cycle earlier than write or `read signal, so it does not write to registers.

I will add an example soon.
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