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How to connect the APB bus to the generated verilog module? #73

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zhajio1988 opened this issue Aug 21, 2019 · 3 comments
Open

How to connect the APB bus to the generated verilog module? #73

zhajio1988 opened this issue Aug 21, 2019 · 3 comments

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@zhajio1988
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hi,
i want to use APB master to configure register.
if i use ORDT to generate the register module, which processor interface do i should use? (Parallel processor interface, Leaf processor interface...)
thanks a lot.

@sdnellen
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i'd use parallel - should get you very close to what is needed for apb.

@zhajio1988
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@sdnellen thanks, but why don't implement a apb bus or ahb bus register file? Copyright problem?

@sdnellen
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just time - never needed apb specifically. if you provide tested convert logic from parallel to apb, can add it as an option

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