@@ -569,17 +569,20 @@ class Slice()(implicit p: Parameters) extends HuanCunModule {
569569 io.ctl_resp.valid := false .B
570570 io.ctl_ecc.valid := false .B
571571 }
572- val reqbuff_perf = a_req_buffer.perfEvents.map(_._1).zip(a_req_buffer.perfinfo)
573- val mshralloc_perf = mshrAlloc.perfEvents.map(_._1).zip(mshrAlloc.perfinfo)
574- val probq_perf = probeHelperOpt.get.perfEvents.map(_._1).zip(probeHelperOpt.get.perfinfo)
575- val direct_perf = directory.asInstanceOf [noninclusive.Directory ].perfEvents.map(_._1).zip(directory.asInstanceOf [noninclusive.Directory ].perfinfo)
576- val huancun_perf = reqbuff_perf ++ mshralloc_perf ++ probq_perf ++ direct_perf
577-
578572 val perfinfo = IO (Output (Vec (numPCntHc, (UInt (6 .W )))))
579- for (((perf_out,(perf_name,perf)),i) <- perfinfo.zip(huancun_perf).zipWithIndex) {
580- perf_out := perf
581- if (print_hcperfcounter){
582- println(s " Huancun perf $i: $perf_name" )
573+ perfinfo := DontCare
574+ if (! cacheParams.inclusive){
575+ val reqbuff_perf = a_req_buffer.perfEvents.map(_._1).zip(a_req_buffer.perfinfo)
576+ val mshralloc_perf = mshrAlloc.perfEvents.map(_._1).zip(mshrAlloc.perfinfo)
577+ val probq_perf = probeHelperOpt.get.perfEvents.map(_._1).zip(probeHelperOpt.get.perfinfo)
578+ val direct_perf = directory.asInstanceOf [noninclusive.Directory ].perfEvents.map(_._1).zip(directory.asInstanceOf [noninclusive.Directory ].perfinfo)
579+ val huancun_perf = reqbuff_perf ++ mshralloc_perf ++ probq_perf ++ direct_perf
580+
581+ for (((perf_out,(perf_name,perf)),i) <- perfinfo.zip(huancun_perf).zipWithIndex) {
582+ perf_out := perf
583+ if (print_hcperfcounter){
584+ println(s " Huancun perf $i: $perf_name" )
585+ }
583586 }
584587 }
585588}
0 commit comments