.verilog-format

--indentation_spaces=2
--assignment_statement_alignment=align
--case_items_alignment=align
--class_member_variable_alignment=align
--distribution_items_alignment=align
--enum_assignment_statement_alignment=align
--formal_parameters_alignment=align
--module_net_variable_alignment=align
--named_parameter_alignment=align
--named_port_alignment=align
--port_declarations_alignment=align
--struct_union_members_alignment=align

--formal_parameters_indentation=indent
--named_parameter_indentation=indent
--named_port_indentation=indent
--port_declarations_indentation=indent

--compact_indexing_and_selections=true
--expand_coverpoints=false
--port_declarations_right_align_packed_dimensions=false
--port_declarations_right_align_unpacked_dimensions=false
--try_wrap_long_lines=false
--wrap_end_else_clauses=false