Merge pull request #308 from JeffDeCola/develop

JeffDeCola · web-flow · commit d4999730303c · 2025-04-09T08:15:22.000-07:00
updating pics to .svg and checking all links
diff --git a/combinational-logic/alus/jeff_74x181/README.md b/combinational-logic/alus/jeff_74x181/README.md
@@ -1,5 +1,8 @@
 # JEFF 74x181 EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _4-bit alu (arithmetic logic unit) and function generator.
 Provides 16 binary logic operations and 16 arithmetic operations
 on two 4-bit words.
diff --git a/combinational-logic/data-operators/full_adder/README.md b/combinational-logic/data-operators/full_adder/README.md
@@ -1,5 +1,8 @@
 # FULL ADDER EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _A 2-bit full adder._
 
 Table of Contents
diff --git a/combinational-logic/data-operators/half_adder/README.md b/combinational-logic/data-operators/half_adder/README.md
@@ -1,5 +1,8 @@
 # HALF ADDER EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _A 2-bit half adder._
 
 Table of Contents
diff --git a/combinational-logic/decoders-and-encoders/decoder_3_8/README.md b/combinational-logic/decoders-and-encoders/decoder_3_8/README.md
@@ -1,5 +1,8 @@
 # DECODER 3-8 EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _Decoder - Three inputs decodes to 1 of 8 outputs (hot)._
 
 Table of Contents
diff --git a/combinational-logic/decoders-and-encoders/encoder_8_3/README.md b/combinational-logic/decoders-and-encoders/encoder_8_3/README.md
@@ -1,5 +1,8 @@
 # ENCODER 8-3 EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _Encoder - Eights inputs (1 hot) encodes to output._
 
 Table of Contents
diff --git a/combinational-logic/decoders-and-encoders/encoder_to_decoder/README.md b/combinational-logic/decoders-and-encoders/encoder_to_decoder/README.md
@@ -1,5 +1,8 @@
 # ENCODER TO DECODER EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _Combining the
 [encoder_8_3](https://github.com/JeffDeCola/my-verilog-examples/tree/master/combinational-logic/decoders-and-encoders/encoder_8_3)
 to the
diff --git a/combinational-logic/multiplexers-and-demultiplexers/demux_1x4/README.md b/combinational-logic/multiplexers-and-demultiplexers/demux_1x4/README.md
@@ -1,5 +1,8 @@
 # DEMUX 1x4 EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _Demultiplexer - One input, four outputs._
 
 Table of Contents
diff --git a/combinational-logic/multiplexers-and-demultiplexers/jeff_74x151/README.md b/combinational-logic/multiplexers-and-demultiplexers/jeff_74x151/README.md
@@ -1,5 +1,8 @@
 # JEFF 74x151 EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _8-line to 1-line data selector/multiplexer.
 Based on the 7400-series integrated circuits used in my
 [programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._
diff --git a/combinational-logic/multiplexers-and-demultiplexers/jeff_74x157/README.md b/combinational-logic/multiplexers-and-demultiplexers/jeff_74x157/README.md
@@ -1,5 +1,8 @@
 # JEFF 74x157 EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _Quad 2-line to 1-line data selector/multiplexer, non-inverting outputs.
 Based on the 7400-series integrated circuits used in my
 [programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._
diff --git a/combinational-logic/multiplexers-and-demultiplexers/mux_4x1/README.md b/combinational-logic/multiplexers-and-demultiplexers/mux_4x1/README.md
@@ -1,5 +1,8 @@
 # MUX 4x1 EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _Multiplexer - Four inputs, one output._
 
 Table of Contents
diff --git a/combinational-logic/multiplexers-and-demultiplexers/mux_to_demux/README.md b/combinational-logic/multiplexers-and-demultiplexers/mux_to_demux/README.md
@@ -1,5 +1,7 @@
 # MUX TO DEMUX EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
 _Combining the
 [mux_4x1](https://github.com/JeffDeCola/my-verilog-examples/tree/master/combinational-logic/multiplexers-and-demultiplexers/mux_4x1)
 to the
diff --git a/docs/pics/sequential-logic/ti-74x161-schematic.jpg b/docs/pics/sequential-logic/ti-74x161-schematic.jpg
diff --git a/docs/pics/sequential-logic/ti-74x161-schematic.svg b/docs/pics/sequential-logic/ti-74x161-schematic.svg
diff --git a/fpga-development-boards/buttons/buttons/README.md b/fpga-development-boards/buttons/buttons/README.md
@@ -1,5 +1,8 @@
 # BUTTONS EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _A few different ways to use buttons on a FPGA development board._
 
 Table of Contents
diff --git a/sequential-logic/arbiters/priority_arbiter/README.md b/sequential-logic/arbiters/priority_arbiter/README.md
@@ -1,5 +1,8 @@
 # PRIORITY ARBITER EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _A three level priority arbiter with asynchronous reset._
 
 Table of Contents
diff --git a/sequential-logic/counters/jeff_74x161/README.md b/sequential-logic/counters/jeff_74x161/README.md
@@ -1,5 +1,8 @@
 # JEFF 74x161 EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _Synchronous presettable 4-bit binary counter, asynchronous clear.
 Based on the 7400-series integrated circuits used in my
 [programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._
@@ -36,7 +39,7 @@ FPGA development board._
 I designed this processor form the 1976 Texas Instruments spec sheet.
 The `clr_bar` is connected directly to the JK flip-flops.
 
-![IMAGE - ti-74x161-schematic.jpg - IMAGE](../../../docs/pics/sequential-logic/ti-74x161-schematic.jpg)
+![IMAGE - ti-74x161-schematic.jpg - IMAGE](../../../docs/pics/sequential-logic/ti-74x161-schematic.svg)
 
 ## TRUTH TABLE
 
