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‎README.md

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# MY VERILOG EXAMPLES
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[![Tag Latest](https://img.shields.io/github/v/tag/jeffdecola/my-verilog-examples)](https://github.com/JeffDeCola/my-verilog-examples/tags)
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[![codeclimate Issue Count](https://codeclimate.com/github/JeffDeCola/my-verilog-examples/badges/issue_count.svg)](https://codeclimate.com/github/JeffDeCola/my-verilog-examples/issues)
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[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
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[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
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[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
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_A place to keep my synthesizable verilog examples._
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Documentation and Reference
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* [verilog](https://github.com/JeffDeCola/my-cheat-sheets/tree/master/hardware/development/languages/verilog-cheat-sheet)
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cheat sheet
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* [iverilog](https://github.com/JeffDeCola/my-cheat-sheets/tree/master/hardware/tools/simulation/iverilog-cheat-sheet)
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is a free tool for simulation and synthesis
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* [GTKWave](https://github.com/JeffDeCola/my-cheat-sheets/tree/master/hardware/tools/simulation/gtkwave-cheat-sheet)
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* [programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)
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_A programable 8-bit microprocessor. Originally designed in VHDL for part of
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[my master's thesis](https://github.com/JeffDeCola/my_masters_thesis)._
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[my master's thesis](https://github.com/JeffDeCola/my-masters-thesis)._
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* PIPELINES
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‎basic-code/combinational-logic/and2/README.md

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# AND2 EXAMPLE
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[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
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[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
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_2-input AND gate used in my
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[programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._
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‎basic-code/combinational-logic/nand4/README.md

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# NAND4 EXAMPLE
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[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
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_4-input NAND gate used in my
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[programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._
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‎basic-code/combinational-logic/nor2/README.md

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# NOR2 EXAMPLE
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[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
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[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
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_2-input NOR gate used in my
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[programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._
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‎basic-code/combinational-logic/not1/README.md

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# NOT1 EXAMPLE
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[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
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_NOT gate used in my
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[programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._
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‎basic-code/combinational-logic/or2/README.md

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# OR2 EXAMPLE
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[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
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[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
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_2-input OR gate used in my
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[programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._
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‎basic-code/combinational-logic/xor2/README.md

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# XOR2 EXAMPLE
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[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
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_2-input XOR gate used in my
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[programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._
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‎basic-code/sequential-logic/d_flip_flop/README.md

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# D FLIP-FLOP EXAMPLE
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_A d flip-flop which is **pulse-triggered**
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can save input data on output._
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‎basic-code/sequential-logic/d_flip_flop_pos_edge_sync_en/README.md

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# D FLIP-FLOP POS EDGE SYNC EN EXAMPLE
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[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
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_A **posedge-triggered** d flip-flop
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with synchronous enable
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used in my

‎basic-code/sequential-logic/d_flip_flop_pulse_triggered/README.md

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# D FLIP-FLOP PULSE-TRIGGERED EXAMPLE
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[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
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_A pulse-triggered d flip-flop (cascading)
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can save input data on output._
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‎basic-code/sequential-logic/jk_flip_flop/README.md

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# JK FLIP-FLOP EXAMPLE
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```text
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THIS IS FOR EXAMPLE ONLY SINCE THIS HAS A RACE CONDITION
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WHEN J =1 and K = 1.

‎basic-code/sequential-logic/jk_flip_flop_pos_edge_sync_clear/README.md

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# JK FLIP-FLOP POS EDGE SYNC CLEAR EXAMPLE
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[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
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_A **posedge-triggered** jk flip-flop
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with synchronous clear
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used in my

‎basic-code/sequential-logic/jk_flip_flop_pulse_triggered/README.md

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# JK FLIP-FLOP PULSE-TRIGGERED EXAMPLE
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_A pulse-triggered jk flip-flop (cascading)
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‎basic-code/sequential-logic/sr_flip_flop/README.md

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# SR FLIP-FLOP EXAMPLE
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[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
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_A sr (set ready) flip-flop which is **pulse-triggered**
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can be set and reset._
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‎basic-code/sequential-logic/sr_latch/README.md

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# SR LATCH EXAMPLE
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_A sr (set ready) latch which is **level-triggered**
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that can be set and reset.
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The latch forms the basic building block

‎basic-code/sequential-logic/t_flip_flop/README.md

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# T FLIP-FLOP EXAMPLE
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```text
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THIS IS FOR EXAMPLE ONLY SINCE THIS T FLIP-FLOP IT BUILT FROM
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A JK FLIP-FLOP THAT HAS A RACE CONDITION WHEN J =1 and K = 1.

‎combinational-logic/alus/jeff_74x181/README.md

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I designed this alu from the 1972 Texas Instruments spec sheet.
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I love the care and thought put into this.
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![IMAGE - ti-74x181-schematic.jpg - IMAGE](../../../docs/pics/combinational-logic/ti-74x181-schematic.jpg)
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![IMAGE - ti-74x181-schematic.jpg - IMAGE](../../../docs/pics/combinational-logic/ti-74x181-schematic.svg)
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## TRUTH TABLE
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‎docs/pics/combinational-logic/ti-74x181-schematic.jpg

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‎docs/pics/combinational-logic/ti-74x181-schematic.svg

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‎sequential-logic/memory/fifo_asynchronous/README.md

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# FIFO SYNCHRONOUS EXAMPLE
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# FIFO ASYNCHRONOUS EXAMPLE
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_An asynchronous fifo using dual-port asynchronous RAM._
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