updating pics to .svg and checking all links

Author: JeffDeCola

docs/pics/sequential-logic/dual_port_ram_asynchronous.jpg

@@ -1,7 +1,20 @@
 # DUAL-PORT RAM ASYNCHRONOUS EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _Dual-port asynchronous RAM using two different clocks._
 
+Other Memory Architectures
+
+* [single_port_ram_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/single_port_ram_synchronous)
+* [dual_port_ram_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/dual_port_ram_synchronous)
+* [dual_port_ram_asynchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/dual_port_ram_asynchronous)
+  **(You are here)**
+* [fifo_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/fifo_synchronous)
+* [fifo_asynchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/fifo_asynchronous)
+* [lifo_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/lifo_synchronous)
+
 Table of Contents
 
 * [OVERVIEW](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/dual_port_ram_asynchronous#overview)
@@ -34,7 +47,7 @@ FPGA development board._
 
 This may help,
 
-![IMAGE - dual_port_ram_asynchronous.jpg - IMAGE](../../../docs/pics/sequential-logic/dual_port_ram_asynchronous.jpg)
+![IMAGE - dual_port_ram_asynchronous.svg - IMAGE](../../../docs/pics/sequential-logic/dual_port_ram_asynchronous.svg)
 
 ## TRUTH TABLE
 

docs/pics/sequential-logic/dual_port_ram_asynchronous.svg

@@ -1,7 +1,20 @@
 # DUAL-PORT RAM SYNCHRONOUS EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _Dual-port synchronous RAM._
 
+Other Memory Architectures
+
+* [single_port_ram_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/single_port_ram_synchronous)
+* [dual_port_ram_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/dual_port_ram_synchronous)
+  **(You are here)**
+* [dual_port_ram_asynchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/dual_port_ram_asynchronous)
+* [fifo_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/fifo_synchronous)
+* [fifo_asynchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/fifo_asynchronous)
+* [lifo_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/lifo_synchronous)
+
 Table of Contents
 
 * [OVERVIEW](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/dual_port_ram_synchronous#overview)
@@ -34,7 +47,7 @@ FPGA development board._
 
 This may help,
 
-![IMAGE - dual_port_ram_synchronous.jpg - IMAGE](../../../docs/pics/sequential-logic/dual_port_ram_synchronous.jpg)
+![IMAGE - dual_port_ram_synchronous.svg - IMAGE](../../../docs/pics/sequential-logic/dual_port_ram_synchronous.svg)
 
 ## TRUTH TABLE
 

docs/pics/sequential-logic/dual_port_ram_synchronous.jpg

@@ -1,7 +1,20 @@
 # FIFO ASYNCHRONOUS EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _An asynchronous fifo using dual-port asynchronous RAM._
 
+Other Memory Architectures
+
+* [single_port_ram_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/single_port_ram_synchronous)
+* [dual_port_ram_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/dual_port_ram_synchronous)
+* [dual_port_ram_asynchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/dual_port_ram_asynchronous)
+* [fifo_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/fifo_synchronous)
+* [fifo_asynchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/fifo_asynchronous)
+  **(You are here)**
+* [lifo_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/lifo_synchronous)
+
 Table of Contents
 
 * [OVERVIEW](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/fifo_asynchronous#overview)
@@ -43,11 +56,11 @@ This fifo uses my dual port asynchronous RAM.
 
 The structure is,
 
-![IMAGE - fifo_asynchronous.jpg - IMAGE](../../../docs/pics/sequential-logic/fifo_asynchronous.jpg)
+![IMAGE - fifo_asynchronous.svg - IMAGE](../../../docs/pics/sequential-logic/fifo_asynchronous.svg)
 
 The full and empy logic is,
 
-![IMAGE - fifo_compare_and_status.jpg - IMAGE](../../../docs/pics/sequential-logic/fifo_compare_and_status.jpg)
+![IMAGE - fifo_compare_and_status.svg - IMAGE](../../../docs/pics/sequential-logic/fifo_compare_and_status.svg)
 
 ## TRUTH TABLE
 

docs/pics/sequential-logic/dual_port_ram_synchronous.svg

@@ -1,7 +1,20 @@
 # FIFO SYNCHRONOUS EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _A synchronous fifo using dual-port synchronous RAM._
 
+Other Memory Architectures
+
+* [single_port_ram_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/single_port_ram_synchronous)
+* [dual_port_ram_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/dual_port_ram_synchronous)
+* [dual_port_ram_asynchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/dual_port_ram_asynchronous)
+* [fifo_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/fifo_synchronous)
+  **(You are here)**
+* [fifo_asynchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/fifo_asynchronous)
+* [lifo_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/lifo_synchronous)
+
 Table of Contents
 
 * [OVERVIEW](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/fifo_synchronous#overview)
@@ -43,11 +56,11 @@ This fifo uses my dual port synchronous RAM.
 
 The structure is,
 
-![IMAGE - fifo_synchronous.jpg - IMAGE](../../../docs/pics/sequential-logic/fifo_synchronous.jpg)
+![IMAGE - fifo_synchronous.svg - IMAGE](../../../docs/pics/sequential-logic/fifo_synchronous.svg)
 
 The full and empty logic is,
 
-![IMAGE - fifo_compare_and_status.jpg - IMAGE](../../../docs/pics/sequential-logic/fifo_compare_and_status.jpg)
+![IMAGE - fifo_compare_and_status.svg - IMAGE](../../../docs/pics/sequential-logic/fifo_compare_and_status.svg)
 
 ## TRUTH TABLE
 

docs/pics/sequential-logic/fifo_asynchronous.jpg

@@ -1,7 +1,20 @@
 # LIFO SYNCHRONOUS EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _A synchronous lifo using dual-port synchronous RAM._
 
+Other Memory Architectures
+
+* [single_port_ram_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/single_port_ram_synchronous)
+* [dual_port_ram_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/dual_port_ram_synchronous)
+* [dual_port_ram_asynchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/dual_port_ram_asynchronous)
+* [fifo_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/fifo_synchronous)
+* [fifo_asynchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/fifo_asynchronous)
+* [lifo_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/lifo_synchronous)
+  **(You are here)**
+
 Table of Contents
 
 * [OVERVIEW](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/lifo_synchronous#overview)
@@ -43,11 +56,11 @@ This fifo uses my dual port synchronous RAM.
 
 The structure is,
 
-![IMAGE - lifo_synchronous.jpg - IMAGE](../../../docs/pics/sequential-logic/lifo_synchronous.jpg)
+![IMAGE - lifo_synchronous.svg - IMAGE](../../../docs/pics/sequential-logic/lifo_synchronous.svg)
 
 The full and empy logic is,
 
-![IMAGE - fifo_compare_and_status.jpg - IMAGE](../../../docs/pics/sequential-logic/lifo_compare_and_status.jpg)
+![IMAGE - fifo_compare_and_status.svg - IMAGE](../../../docs/pics/sequential-logic/lifo_compare_and_status.svg)
 
 ## TRUTH TABLE
 

docs/pics/sequential-logic/fifo_asynchronous.svg

@@ -1,7 +1,20 @@
 # SINGLE-PORT RAM SYNCHRONOUS EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _Single-port synchronous RAM._
 
+Other Memory Architectures
+
+* [single_port_ram_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/single_port_ram_synchronous)
+  **(You are here)**
+* [dual_port_ram_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/dual_port_ram_synchronous)
+* [dual_port_ram_asynchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/dual_port_ram_asynchronous)
+* [fifo_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/fifo_synchronous)
+* [fifo_asynchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/fifo_asynchronous)
+* [lifo_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/lifo_synchronous)
+
 Table of Contents
 
 * [OVERVIEW](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/single_port_ram_synchronous#overview)
@@ -33,7 +46,7 @@ FPGA development board._
 
 This may help,
 
-![IMAGE - single_port_ram_synchronous.jpg - IMAGE](../../../docs/pics/sequential-logic/single_port_ram_synchronous.jpg)
+![IMAGE - single_port_ram_synchronous.svg - IMAGE](../../../docs/pics/sequential-logic/single_port_ram_synchronous.svg)
 
 ## TRUTH TABLE
 

docs/pics/sequential-logic/fifo_compare_and_status.jpg

@@ -1,5 +1,8 @@
 # JEFF 74x377 EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _8-bit register, clock enable.
 Based on the 7400-series integrated circuits used in my
 [programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._

docs/pics/sequential-logic/fifo_compare_and_status.svg

@@ -1,5 +1,8 @@
 # SIMPLE 8-BIT REGISTER EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _A simple 8-bit register with synchronous load and clear._
 
 Table of Contents
@@ -28,7 +31,7 @@ FPGA development board._
 
 This may help,
 
-![IMAGE - simple-8-bit-register.jpg - IMAGE](../../../docs/pics/sequential-logic/simple-8-bit-register.jpg)
+![IMAGE - simple-8-bit-register.svg - IMAGE](../../../docs/pics/sequential-logic/simple-8-bit-register.svg)
 
 ## TRUTH TABLE
 

docs/pics/sequential-logic/fifo_synchronous.jpg

@@ -1,5 +1,8 @@
 # LEFT SHIFT REGISTER EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _A 4-bit left shift register._
 
 Table of Contents