updated fifos

Author: JeffDeCola

docs/pics/sequential-logic/dual_port_ram_asynchronous-waveform.jpg

@@ -18,6 +18,8 @@ Dual-port RAM is a type of computer memory that allows
 two separate devices to read and write data simultaneously.
 This is achieved by having two separate access ports, one for each device.
 
+The B port will have precedence if data is written to both ports at the same time.
+
 _I used
 [iverilog](https://github.com/JeffDeCola/my-cheat-sheets/tree/master/hardware/tools/simulation/iverilog-cheat-sheet)
 to simulate and
@@ -50,33 +52,41 @@ The
 behavioral model,
 
 ```verilog
-    // DATA TYPES
-    reg [7:0] mem [0:15];
-    reg [3:0] address_register_A, address_register_B;
+    // PARAMETERS
+    parameter DATA_WIDTH = 8;
+    parameter ADDR_WIDTH = 4;
+    parameter MEM_DEPTH = 16;
 
-    // OUTPUT (THIS MAKES IT SYNCHRONOUS)
-    assign data_out_A = mem[address_register_A];
-    assign data_out_B = mem[address_register_B];
+    // DATA TYPES
+    reg [DATA_WIDTH-1:0] mem [0:MEM_DEPTH-1];           // RAM (16x8)
 
-    // RAM
+    // PORT A
     // ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
     always @(posedge clk_A) begin
+        // WRITE (DATA PASS)
         if (we_A) begin
             mem[addr_A] <= data_in_A;
+            data_out_A <= data_in_A;
+        // READ    
         end else begin
-            address_register_A <= addr_A;
+            data_out_A <= mem[addr_A];
         end
     end
 
-    // RAM
+    // PORT B - HAS PRECEDENCE FOR WRITE
     // ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
     always @(posedge clk_B) begin
+        //WRITE (DATA PASS)
         if (we_B) begin
             mem[addr_B] <= data_in_B;
+            data_out_B <= data_in_B;
+        //READ
         end else begin
-            address_register_B <= addr_B;
+            data_out_B <= mem[addr_B];
         end
     end
+
+endmodule
 ```
 
 ## RUN (SIMULATE)
@@ -118,34 +128,34 @@ TEST START --------------------------------
 
                      | TIME(ns) | WE_A | ADDR_A | DATA_IN_A | DATA_OUT_A | WE_B | ADDR_B | DATA_IN_B | DATA_OUT_B |
                      ----------------------------------------------------------------------------------------------
-       1        INIT |       12 |                                        |  1   |  0000  | 00000000  |  xxxxxxxx  |
-   1            INIT |       15 |  1   |  0000  | 00000000  |  xxxxxxxx  |
-       2        WR_B |       26 |                                        |  1   |  0001  | 11110011  |  xxxxxxxx  |
-   2            WR_A |       35 |  1   |  0000  | 11110000  |  xxxxxxxx  |
-       3        WR_B |       40 |                                        |  1   |  0011  | 11001111  |  xxxxxxxx  |
-       4        WR_B |       54 |                                        |  1   |  1111  | 11101010  |  xxxxxxxx  |
-   3            WR_A |       55 |  1   |  0001  | 00001111  |  xxxxxxxx  |
-       5        RD_B |       68 |                                        |  0   |  0001  | xxxxxxxx  |  00001111  |
-   4            WR_A |       75 |  1   |  1110  | 10101010  |  xxxxxxxx  |
+       1        INIT |       12 |                                        |  1   |  0000  | 00000000  |  00000000  |
+   1           INIT_ |       15 |  1   |  0000  | 00000000  |  00000000  |
+       2        WR_B |       26 |                                        |  1   |  0001  | 11110011  |  11110011  |
+   2           WR_A_ |       35 |  1   |  0000  | 11110000  |  11110000  |
+       3        WR_B |       40 |                                        |  1   |  0011  | 11001111  |  11001111  |
+       4        WR_B |       54 |                                        |  1   |  1110  | 11101010  |  11101010  |
+   3           WR_A_ |       55 |  1   |  0001  | 00001111  |  00001111  |
+       5        RD_B |       68 |                                        |  0   |  1110  | xxxxxxxx  |  11101010  |
+   4           WR_A_ |       75 |  1   |  1110  | 10101010  |  10101010  |
        6        RD_B |       82 |                                        |  0   |  0011  | xxxxxxxx  |  11001111  |
-   5            RD_A |       95 |  0   |  0000  | xxxxxxxx  |  11110000  |
-       7        RD_B |       96 |                                        |  0   |  1111  | xxxxxxxx  |  11101010  |
-       8        RD_B |      110 |                                        |  0   |  1110  | xxxxxxxx  |  10101010  |
-   6            RD_A |      115 |  0   |  0001  | xxxxxxxx  |  00001111  |
+   5           RD_A_ |       95 |  0   |  1110  | xxxxxxxx  |  10101010  |
+       7        RD_B |       96 |                                        |  0   |  1111  | xxxxxxxx  |  xxxxxxxx  |
+       8        RD_B |      110 |                                        |  0   |  0011  | xxxxxxxx  |  11001111  |
+   6           RD_A_ |      115 |  0   |  0001  | xxxxxxxx  |  00001111  |
        9        RD_B |      124 |                                        |  0   |  1001  | xxxxxxxx  |  xxxxxxxx  |
-   7            RD_A |      135 |  0   |  1110  | xxxxxxxx  |  10101010  |
-      10        RD_B |      138 |                                        |  0   |  1111  | xxxxxxxx  |  11101010  |
-      11        WR_B |      152 |                                        |  1   |  1111  | 00000000  |  00000000  |
-   8            WR_A |      155 |  1   |  1001  | 00000111  |  10101010  |
-      12        WR_B |      166 |                                        |  1   |  0001  | 00011000  |  00000000  |
-   9            WR_A |      175 |  1   |  1111  | 11111010  |  10101010  |
-      13        RD_B |      180 |                                        |  0   |  1111  | xxxxxxxx  |  11111010  |
+   7           RD_A_ |      135 |  0   |  0011  | xxxxxxxx  |  11001111  |
+      10        RD_B |      138 |                                        |  0   |  1111  | xxxxxxxx  |  xxxxxxxx  |
+      11        WR_B |      152 |                                        |  1   |  1111  | 01000000  |  01000000  |
+   8           WR_A_ |      155 |  1   |  1001  | 00000111  |  00000111  |
+      12        WR_B |      166 |                                        |  1   |  0001  | 00011000  |  00011000  |
+   9           WR_A_ |      175 |  1   |  1111  | 11111010  |  11111010  |
+      13        RD_B |      180 |                                        |  0   |  0001  | xxxxxxxx  |  00011000  |
       14        RD_B |      194 |                                        |  0   |  0001  | xxxxxxxx  |  00011000  |
-  10            WR_A |      195 |  1   |  1100  | 00000011  |  10101010  |
-  11            WR_A |      215 |  1   |  0010  | 00001111  |  10101010  |
-  12            RD_A |      235 |  0   |  0001  | xxxxxxxx  |  00011000  |
-  13            RD_A |      255 |  0   |  1111  | xxxxxxxx  |  11111010  |
-  14            RD_A |      275 |  0   |  0001  | xxxxxxxx  |  00011000  |
+  10           WR_A_ |      195 |  1   |  1100  | 00000011  |  00000011  |
+  11           WR_A_ |      215 |  1   |  0010  | 00001111  |  00001111  |
+  12           RD_A_ |      235 |  0   |  0001  | xxxxxxxx  |  00011000  |
+  13           RD_A_ |      255 |  0   |  0001  | xxxxxxxx  |  00011000  |
+  14           RD_A_ |      275 |  0   |  0001  | xxxxxxxx  |  00011000  |
 
  VECTORS_A:   14
   ERRORS_A:    0

docs/pics/sequential-logic/fifo_asynchronous-waveform.jpg

@@ -1,37 +1,50 @@
-// Dual-port asynchronous RAM using two different clocks.
+// Dual-port asynchronous RAM.
 
 module dual_port_ram_asynchronous_behavioral(
-    input  clk_A, clk_B,                    // Clocks
-    input  we_A, we_B,                      // Write enable
-    input  [3:0] addr_A, addr_B,            // Address
-    input  [7:0] data_in_A, data_in_B,      // Data to write
-    output [7:0] data_out_A, data_out_B);   // Data to read
+    input  clk_A,                                       // Clock A
+    input  clk_B,                                       // Clock B
+    // PORT A
+    input  we_A,                                        // Write enable
+    input  [ADDR_WIDTH-1:0] addr_A,                     // Address
+    input  [DATA_WIDTH-1:0] data_in_A,                  // Data to write
+    output reg [DATA_WIDTH-1:0] data_out_A,             // Data to read
+    // PORT B
+    input  we_B,                                        // Write enable
+    input  [ADDR_WIDTH-1:0] addr_B,                     // Address
+    input  [DATA_WIDTH-1:0] data_in_B,                  // Data to write
+    output reg [DATA_WIDTH-1:0] data_out_B);            // Data to read
 
-    // DATA TYPES
-    reg [7:0] mem [0:15];
-    reg [3:0] address_register_A, address_register_B;
+    // PARAMETERS
+    parameter DATA_WIDTH = 8;
+    parameter ADDR_WIDTH = 4;
+    parameter MEM_DEPTH = 16;
 
-    // OUTPUT (THIS MAKES IT SYNCHRONOUS)
-    assign data_out_A = mem[address_register_A];
-    assign data_out_B = mem[address_register_B];
+    // DATA TYPES
+    reg [DATA_WIDTH-1:0] mem [0:MEM_DEPTH-1];           // RAM (16x8)
 
-    // RAM
+    // PORT A
     // ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
     always @(posedge clk_A) begin
+        // WRITE (DATA PASS)
         if (we_A) begin
             mem[addr_A] <= data_in_A;
+            data_out_A <= data_in_A;
+        // READ    
         end else begin
-            address_register_A <= addr_A;
+            data_out_A <= mem[addr_A];
         end
     end
 
-    // RAM
+    // PORT B - HAS PRECEDENCE FOR WRITE
     // ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
     always @(posedge clk_B) begin
+        //WRITE (DATA PASS)
         if (we_B) begin
             mem[addr_B] <= data_in_B;
+            data_out_B <= data_in_B;
+        //READ
         end else begin
-            address_register_B <= addr_B;
+            data_out_B <= mem[addr_B];
         end
     end
 

docs/pics/sequential-logic/fifo_asynchronous.jpg

@@ -1,32 +1,37 @@
 [*]
 [*] GTKWave Analyzer v3.3.115 (w)1999-2023 BSI
-[*] Tue May 16 01:20:39 2023
+[*] Sun May 21 18:37:39 2023
 [*]
 [dumpfile] "/home/jeff/verilog/my-verilog-examples/sequential-logic/memory/dual_port_ram_asynchronous/dual_port_ram_asynchronous_tb.vcd"
-[dumpfile_mtime] "Tue May 16 01:15:44 2023"
-[dumpfile_size] 4303
+[dumpfile_mtime] "Sun May 21 18:34:00 2023"
+[dumpfile_size] 4339
 [savefile] "/home/jeff/verilog/my-verilog-examples/sequential-logic/memory/dual_port_ram_asynchronous/dual_port_ram_asynchronous_tb.gtkw"
 [timestart] 0
 [size] 1319 600
 [pos] 33266 32949
-*-15.929993 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-15.929993 68000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] DUAL_PORT_RAM_ASYNCHRONOUS_TB.
 [sst_width] 204
 [signals_width] 150
 [sst_expanded] 1
 [sst_vpaned_height] 152
 @28
 DUAL_PORT_RAM_ASYNCHRONOUS_TB.CLK_A
+@200
+-
+@28
 DUAL_PORT_RAM_ASYNCHRONOUS_TB.WE_A
-@23
-DUAL_PORT_RAM_ASYNCHRONOUS_TB.ADDR_A[3:0]
 @22
+DUAL_PORT_RAM_ASYNCHRONOUS_TB.ADDR_A[3:0]
 DUAL_PORT_RAM_ASYNCHRONOUS_TB.DATA_IN_A[7:0]
 DUAL_PORT_RAM_ASYNCHRONOUS_TB.DATA_OUT_A[7:0]
 @200
 -
 @28
 DUAL_PORT_RAM_ASYNCHRONOUS_TB.CLK_B
+@201
+-
+@28
 DUAL_PORT_RAM_ASYNCHRONOUS_TB.WE_B
 @22
 DUAL_PORT_RAM_ASYNCHRONOUS_TB.ADDR_B[3:0]

docs/pics/sequential-logic/fifo_synchronous-waveform.jpg

@@ -80,9 +80,7 @@ module DUAL_PORT_RAM_ASYNCHRONOUS_TB;
 
     initial begin
         // WAIT FOR TEST TO FINISH
-        // THIS IS NOT PERFECT - I PROBABLY NEED TO FIX THIS FOR DIFFERENT CLOCK SPEEDS
-        @(END_B);
-        @(END_A);
+        wait (END_A == 1'b1 && END_B == 1'b1);
         $display();
         $display(" VECTORS_A: %4d", VECTORCOUNT_A);
         $display("  ERRORS_A: %4d", ERRORS_A);
@@ -115,6 +113,7 @@ module DUAL_PORT_RAM_ASYNCHRONOUS_TB;
             end
 
         end
+        // $display("Waiting for b to finish");
 
     end
 
@@ -139,6 +138,7 @@ module DUAL_PORT_RAM_ASYNCHRONOUS_TB;
             end
 
         end
+        // $display("Waiting for a to finish");
 
     end