Merge pull request #311 from JeffDeCola/develop

updating pics to .svg and checking all links

Author: JeffDeCola

README.md

@@ -105,7 +105,7 @@ The artifacts created are,
 
 Where the testbench structure is,
 
-![testbench-structure.jpg](docs/pics/testbench-structure.jpg)
+![testbench-structure.svg](docs/pics/testbench-structure.svg)
 
 ## BASIC CODE
 

docs/pics/systems/simple-pipeline.jpg

@@ -1,5 +1,8 @@
 # SIMPLE PIPELINE EXAMPLE
 
+[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)
+[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)
+
 _A simple pipeline._
 
 Table of Contents
@@ -43,7 +46,7 @@ FPGA development board._
 
 This may help,
 
-![IMAGE - simple-pipeline.jpg - IMAGE](../../../docs/pics/systems/simple-pipeline.jpg)
+![IMAGE - simple-pipeline.svg - IMAGE](../../../docs/pics/systems/simple-pipeline.svg)
 
 ## VERILOG CODE