-
Notifications
You must be signed in to change notification settings - Fork 1
/
Copy pathuart-omap_rtdm.c
1255 lines (984 loc) · 32.6 KB
/
uart-omap_rtdm.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of.h>
//#include <linux/of_i2c.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <linux/i2c-omap.h>
#include<linux/irq.h>
#include <linux/pinctrl/consumer.h>
#include <rtdm/rtdm_driver.h>
#include<rtdm/rtdm.h>
#define DEVICE_NAME_1 "omap_uart"
#define DRIVER_NAME_1 "omap_uart"
#include <linux/init.h>
#include <linux/console.h>
#include <linux/serial_reg.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/clk.h>
#include <linux/serial_core.h>
#include <linux/gpio.h>
#include <linux/platform_data/serial-omap.h>
#include<linux/kernel.h>
#define OMAP_MAX_HSUART_PORTS 6
#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
#define OMAP_UART_REV_42 0x0402
#define OMAP_UART_REV_46 0x0406
#define OMAP_UART_REV_52 0x0502
#define OMAP_UART_REV_63 0x0603
#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
/* SCR register bitmasks */
#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
/* FCR register bitmasks */
#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
/* MVR register bitmasks */
#define OMAP_UART_MVR_SCHEME_SHIFT 30
#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
#define OMAP_UART_MVR_MAJ_MASK 0x700
#define OMAP_UART_MVR_MAJ_SHIFT 8
#define OMAP_UART_MVR_MIN_MASK 0x3f
#define OMAP_UART_DMA_CH_FREE -1
#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
#define OMAP_MODE13X_SPEED 230400
/* WER = 0x7F
* Enable module level wakeup in WER reg
*/
#define OMAP_UART_WER_MOD_WKUP 0X7F
/* Enable XON/XOFF flow control on output */
#define OMAP_UART_SW_TX 0x08
/* Enable XON/XOFF flow control on input */
#define OMAP_UART_SW_RX 0x02
#define OMAP_UART_SW_CLR 0xF0
#define OMAP_UART_TCR_TRIG 0x0F
#define SOC_PRCM_REGS (0x44E00000)
#define SOC_PRCM_SIZE (0x400 )
#define CM_PER_UART4_CLKCTRL (1 << 1)
#define BUFFER_SIZE 64
struct circ_buf_1 {
char buf[BUFFER_SIZE];
int head;
int tail;
};
// void ringBufS_init (ringBufS *_this);
// int ringBufS_empty (ringBufS *_this);
// int ringBufS_full (ringBufS *_this);
// int ringBufS_get (ringBufS *_this);
// void ringBufS_put (ringBufS *_this, const unsigned char c);
// void ringBufS_flush (ringBufS *_this, const int clearBuffer);
typedef struct uart_omap_port {
struct device *dev;
unsigned char ier;
unsigned char lcr;
unsigned char mcr;
unsigned char fcr;
unsigned char efr;
unsigned char dll;
unsigned char dlh;
unsigned char mdr1;
unsigned char scr;
int use_dma;
/*
* Some bits in registers are cleared on a read, so they must
* be saved whenever the register is read but the bits will not
* be immediately processed.
*/
unsigned int lsr_break_flag;
unsigned char msr_saved_flags;
char name[20];
unsigned long port_activity;
int context_loss_cnt;
u32 errata;
u8 wakeups_enabled;
int DTR_gpio;
int DTR_inverted;
int DTR_active;
struct pm_qos_request pm_qos_request;
u32 latency;
u32 calc_latency;
struct work_struct qos_work;
struct pinctrl *pins;
unsigned int irq; /* irq number */
unsigned long irqflags; /* irq flags */
unsigned int fifosize; /* tx fifo size */
unsigned char regshift; /* reg offset shift */
unsigned int line; /* port index */
resource_size_t mapbase; /* for ioremap */
unsigned char __iomem *membase; /* read/write[bwl] */
upf_t flags;
unsigned int uartclk; /* base uart clock */
unsigned int mctrl;
unsigned int read_status_mask; /* driver specific */
unsigned int ignore_status_mask; /* driver specific */
u8 *buf_tx;
size_t buf_len_tx;
u8 *buf_rx;
size_t buf_len_rx;
rtdm_irq_t irq_handle;
rtdm_event_t w_event_tx;
rtdm_event_t w_event_rx;
rtdm_lock_t lock;
struct rtdm_device rtdm_dev;
unsigned long timeout,systime,systime1;
struct circ_buf_1 rbuf;
}MY_DEV;
void f_cir_buf(MY_DEV *up)
{
//up->rbuf=rtdm_malloc(sizeof(BUFFER_SIZE));
memset(up->rbuf.buf,0,BUFFER_SIZE);
up->rbuf.head = 0;
up->rbuf.tail= 0;
}
void write_buffer(MY_DEV *up, char data)
{
unsigned int next = (unsigned int)(up->rbuf.head + 1) % BUFFER_SIZE;
if (next != up->rbuf.tail)
{
up->rbuf.buf[up->rbuf.head] = data;
up->rbuf.head = next;
}
}
char read_buffer(MY_DEV *up)
{
// if the head isn't ahead of the tail, we don't have any characters
if (up->rbuf.head == up->rbuf.tail)
{
printk("buffer is empty\n");
return -1; // quit with an error
}
else
{
char data = up->rbuf.buf[up->rbuf.tail];
up->rbuf.tail = (unsigned int)(up->rbuf.tail + 1) % BUFFER_SIZE;
return data;
}
}
static inline unsigned int serial_in(struct uart_omap_port *up, int offset)//read
{
offset <<= up->regshift;
return readw(up->membase + offset);
}
static inline void serial_out(struct uart_omap_port *up, int offset, int value)//write
{
offset <<= up->regshift;
writew(value, up->membase + offset);
}
static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
{
u8 timeout = 255;
printk("serial_omap_mdr1_errataser start\n");
serial_out(up, UART_OMAP_MDR1, mdr1);
rtdm_task_sleep(2000);
serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
/*
* Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
* TX_FIFO_E bit is 1.
*/
while (UART_LSR_THRE != (serial_in(up, UART_LSR) & (UART_LSR_THRE | UART_LSR_DR)))
{
timeout--;
if (!timeout)
{
/* Should *never* happen. we warn and carry on */
dev_crit(up->dev, "Errata i202: timedout %x\n",serial_in(up, UART_LSR));
break;
}
rtdm_task_sleep(1000);
}
printk("serial_omap_mdr1_errataser end\n");
}
static inline void serial_omap_clear_fifos(struct uart_omap_port *up)//clearing FIFO before trasmiting
{
printk("..................................serial_omap_clear_fifos");
//UART_FCR is selested if LCR[7]=0 FCR[5:4] can only be writtern if EFR[4]=1
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);//enable FIFO(can change only when baud rate is not running DLL and DLH cleared to 0)
serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);//Clear RCVR FIFO and XMIT FIFO
serial_out(up, UART_FCR, 0);//disable tx and rx fifo:nochange in other value
printk(".............................serial_omap_clear_fifos end");
}
static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
{
printk("..................serial_omap_rdi\n");
//dump_stack();
u16 w;
if (!(lsr & UART_LSR_DR))
{ printk("Receive buffer is full\n");
return;
}
// while(up->buf_len_rx--)
{
w = serial_in(up, UART_RX);
printk("Receive buffer=%x\n",w);
// *up->buf_rx++ = w;
write_buffer(up,w);
// up->buf_len_rx--;
}
printk("...............serial_omap_rdi\n");
}
static unsigned int serial_omap_get_divisor(struct uart_omap_port *port, unsigned int baud)
{
unsigned int divisor;
printk(".................serial_omap_get_divisor\n");
if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
{ divisor = 13;
printk("x13 baudrate\n");
}
else
{
divisor = 16;
printk("x16 baudrate\n");
}
printk("............serial_omap_get_divisor end\n");
return port->uartclk/(baud * divisor);
}
static ssize_t uart_rd_rt(struct rtdm_dev_context *context,rtdm_user_info_t * user_info, void *buf,size_t nbyte)
{
int err;
int ret=0;
int count;
MY_DEV *up=(MY_DEV *)context->device->device_data;
u8 *tmp;
printk("..............uart_rd_rt start\n");
tmp=(u8 *)rtdm_malloc(nbyte);
up->buf_rx=(u8 *)tmp;
up->buf_len_rx = nbyte;
count =nbyte;
if (!(up->ier & UART_IER_RDI))
{
up->ier |= UART_IER_RDI;
serial_out(up, UART_IER, up->ier);
}
err=rtdm_event_wait(&up->w_event_rx);
if(err<0)
{
dev_err(up->dev,"controller timed out\n");
rtdm_printk("rtdm_event_timedwait: timeout\n");
return -ETIMEDOUT;
}
if(err==0)
{
ret=nbyte;
}
while(count--)
{
*tmp=read_buffer(up);
printk("Receive rd=%x\n",*tmp);
tmp = tmp +1;
}
tmp=tmp-nbyte;
if(rtdm_safe_copy_to_user(user_info,buf,(void *)tmp, nbyte))
rtdm_printk("ERROR : can't copy data from driver\n");
printk("............uart_rd_rt end\n");
rtdm_free(tmp);
return ret;
}
static void serial_omap_stop_tx(struct uart_omap_port *up)
{
printk(".......................serial_omap_stop_tx\n");
//disable transmit holding register interrupt
if (up->ier & UART_IER_THRI)
{
up->ier &= ~UART_IER_THRI;
serial_out(up, UART_IER, up->ier);
}
printk("..........................serial_omap_stop_tx end\n");
}
static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
{
u16 w;
//trasmit holding register empty
printk("trasmit_char.....start\n");
if(!(lsr & UART_LSR_THRE))
{ printk("Holding register is empty\n");
return;
}
//(void) serial_in(up, UART_LSR);
while (up->buf_len_tx)
{
// w = *up->buf_tx++;
w = read_buffer(up);
printk("up->buf_len_tx--=%d\n",up->buf_len_tx);
up->buf_len_tx--;
// rtdm_printk("BUFFER ADDRESS IN TRASMIT MODE=%x\n",up->buf);
rtdm_printk("buffer value in trasmit_char=%x\n",w);
serial_out(up, UART_TX, w);
}
if(up->buf_len_tx == 0)
{
serial_omap_stop_tx(up);
}
printk("trasmit_char......end\n");
}
static ssize_t uart_wr_rt(struct rtdm_dev_context *context,rtdm_user_info_t * user_info,const void *buf, size_t nbyte)
{
int ret=0;
int err;
int count;
char c;
MY_DEV *up=(MY_DEV *)context->device->device_data;
char *tmp;
up->buf_len_tx = nbyte;
printk("uart_wr_rt start\n");
tmp=rtdm_malloc(nbyte);
if ((rtdm_safe_copy_from_user(user_info,tmp, buf, up->buf_len_tx)))
rtdm_printk("ERROR : can't copy data to driver\n");
count=nbyte;
while(count--)
{
write_buffer(up,*tmp);
tmp=tmp+1;
// up->buf_tx=(char *)tmp;
// printk("up->buf_tx=%x\n",*up->buf_tx);
//enable Trasmitter holding Register
if (!(up->ier & UART_IER_THRI))
{
up->ier |= UART_IER_THRI;
up->systime = rtdm_clock_read();
serial_out(up, UART_IER, up->ier);
}
}
printk("Tx interrupt enable\n");
printk("rtdm_event_wait before\n");
err=rtdm_event_wait(&up->w_event_tx);
if(err<0)
{
dev_err(up->dev,"controller timed out\n");
rtdm_printk("rtdm_event_timedwait: timeout\n");
return -ETIMEDOUT;
}
up->systime1 = rtdm_clock_read();
up->timeout=(up->systime1)-(up->systime);
printk("scheduling latency=%ld\n",up->timeout);
if(err==0)
{
ret=nbyte;
}
printk("rtdm_event_wait after\n");
printk("uart_wr_rt end\n");
rtdm_free(tmp);
return ret;
}
#define CS5_1 0
#define CS6_1 1
#define CS7_1 2
#define CS8_1 3
#define BAUD_4800 0
#define BAUD_9600 1
#define BAUD_115200 2
static void serial_omap_set_termios(MY_DEV *up, unsigned int request)
{
int val;
unsigned char cval = 0;
unsigned int baud, quot;
rtdm_lockctx_t context1;
int err;
printk("serial_omap_set_termios\n");
printk("Local struct up=%x\n",up);
printk("request=%x\n",request);
val=request & 0x03;
printk("val=%x",val);
switch(val)
{
case CS5_1:
printk("CS5\n");
cval = UART_LCR_WLEN5;
break;
case CS6_1:
printk("CS6\n");
cval = UART_LCR_WLEN6;
break;
case CS7_1:
printk("CS7\n");
cval = UART_LCR_WLEN7;
break;
default:
case CS8_1:
printk("CS8\n");
cval = UART_LCR_WLEN8;
break;
}
if(request & 0x04)
{ printk("set two stop bits\n");
cval |= UART_LCR_STOP;
}
if(request & 0x08)
{ printk("set even patity\n");
cval |= UART_LCR_PARITY;
}
if(request & 0x10)
{ printk("set odd parity\n");
cval |= UART_LCR_EPAR;
}
val=request & 0x60;
val = val >> 5;
switch(val)
{
case BAUD_4800:
printk("BAUD_4800\n");
baud = 4800;
break;
case BAUD_9600:
printk("BAUD_9600\n");
baud = 9600;
break;
case BAUD_115200:
printk("BAUD_115200\n");
baud = 115200;
default:
printk("default\n");
baud = 9600;
}
// baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
quot = serial_omap_get_divisor(up, baud);//for getting dll and dlh register value
printk("serial_omap_get_divisor=%d\n",quot);
up->calc_latency = (USEC_PER_SEC * up->fifosize) / (baud / 8);
up->latency = up->calc_latency;
up->dll = quot & 0xff;
up->dlh = quot >> 8;
up->mdr1 = UART_OMAP_MDR1_DISABLE;
up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | UART_FCR_ENABLE_FIFO;
err = rtdm_irq_disable(&up->irq_handle);
if(err<0)
rtdm_printk("error in rtdm_irq_enable\n");
rtdm_lock_get_irqsave(&up->lock,context1);
up->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
// if (termios->c_iflag & INPCK)
// up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; //Frame error indicator, Parity error indicator
//
// if (termios->c_iflag & (BRKINT | PARMRK))
// up->port.read_status_mask |= UART_LSR_BI; //Break interrupt indicator
up->ignore_status_mask = 0;
//this should be passed from user space
// if (termios->c_iflag & IGNBRK) // IGNBRK Ignore BREAK condition on input.
// {
printk("Ignore Break condition on input\n");
up->ignore_status_mask |= UART_LSR_BI;
// }
up->ier &= ~UART_IER_MSI;
serial_out(up, UART_IER, up->ier);
printk("Enable interrupt\n");
serial_out(up, UART_LCR, cval); //writing the setting to Line control register /* reset DLAB */
up->lcr = cval; //saving the setting of line control register
up->scr = OMAP_UART_SCR_TX_EMPTY;
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_out(up, UART_DLL, 0);
serial_out(up, UART_DLM, 0);
serial_out(up, UART_LCR, 0);
//***********************************************************************
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); //config to mode B
up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;//value of efr register without enhance function write enable bit
up->efr &= ~UART_EFR_SCD; //remove special character detect enable
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); //writing to EFR register with enhance function write enable bit
//************************************************************************************
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); //config to mode A
up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR; //value to TCRTLR=0(No action) if 1 then we can enable TCR and TLR
serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); //writing value to the MCR with TCRTLR enable
/* FIFO ENABLE, DMA MODE */
up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; //enable the granularity of 1 for trigger RX level
//*******************************************************************
/* Set receive FIFO threshold to 16 characters and
* transmit FIFO threshold to 16 spaces
*/
up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; // dont set RX_FIFO_TRIG to 60 character
up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; //dont set TX_FIFO_TRIG to 56 character
up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | UART_FCR_ENABLE_FIFO; //Rx fifo trigger at 16 character | Tx fifo trigger at 32 char | FIFO_EN
serial_out(up, UART_FCR, up->fcr); //write to FCR
//********************************************************************
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); //config to mode B
serial_out(up, UART_OMAP_SCR, up->scr); //writing to SCR(supplementary control register)
//*******************************************************************
/* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); //config mode A
serial_out(up, UART_MCR, up->mcr); //writing to MCR without TCRTLR
//*******************************************************************
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); //config mode B
serial_out(up, UART_EFR, up->efr); //writing to EFR register without special character detect enable
//*******************************************************************
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); //config mode A
/* Protocol, Baud Rate, and Interrupt Settings */
if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) //
serial_omap_mdr1_errataset(up, up->mdr1);
else
serial_out(up, UART_OMAP_MDR1, up->mdr1);
//********************************************************************
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); //config mode B
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); //writing to EFR register with special character
serial_out(up, UART_LCR, 0); //writing line control register
serial_out(up, UART_IER, 0); //writing to IER
//********************************************************************
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_DLL, up->dll); /* LS of divisor */
serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
serial_out(up, UART_LCR, 0);
serial_out(up, UART_IER, up->ier);
//********************************************************************
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
serial_out(up, UART_EFR, up->efr);
serial_out(up, UART_LCR, cval);
if (baud > 230400 && baud != 3000000)
{ printk("baud > 230400\n");
up->mdr1 = UART_OMAP_MDR1_13X_MODE;
}
else
{ printk("baud < 230400\n");
up->mdr1 = UART_OMAP_MDR1_16X_MODE;
}
if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
{ printk("up->errata condition true\n");
serial_omap_mdr1_errataset(up, up->mdr1);
}
else
{ printk("up->errata condition false\n");
serial_out(up, UART_OMAP_MDR1, up->mdr1);
}
//***********************************************************************
/* Configure flow control */
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
/* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
// serial_out(up, UART_XON1, termios->c_cc[VSTART]);
// serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
/* Enable access to TCR/TLR */
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);//TCR trasmission control register value 0xFF
//no hardware control
up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
serial_out(up, UART_MCR, up->mcr); //write to MCR
printk("write to UART_MCR\n");
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); //write to LCR for switching to config mode B
printk("Switch to config mode B\n");
serial_out(up, UART_EFR, up->efr); //write to EFR
printk("write to EFR register\n");
serial_out(up, UART_LCR, up->lcr); //write to LCR
printk("write to LCR\n");
rtdm_lock_put_irqrestore(&up->lock,context1);
err = rtdm_irq_enable(&up->irq_handle);
if(err<0)
rtdm_printk("error in rtdm_irq_enable\n");
printk("serial_omap_set_termios end\n");
}
static int uart_ioctl_rt(struct rtdm_dev_context *context,rtdm_user_info_t * user_info,unsigned int req, void *arg)
{
MY_DEV *up=(MY_DEV *)context->device->device_data;
printk("Local struct up=%x\n",up);
printk("uart_ioctl_rt start\n");
printk("req from userspace=%x\n",req);
if(req != 0)
{
serial_omap_set_termios(up, req);
printk("uart_ioctl_rt end\n");
}
return 0;
}
static irqreturn_t serial_omap_irq(int irq,void *dev_id)
{
// irqreturn_t ret;
// MY_DEV *dev = dev_id;
rtdm_printk("..............my_isr_2..............\n");
return IRQ_HANDLED;
}
static int rtdm_my_isr(rtdm_irq_t *irq_context)
{
MY_DEV *up=rtdm_irq_get_arg(irq_context,MY_DEV);
up->systime1 = rtdm_clock_read();
up->timeout = up->systime1 - up->systime;
printk("Interrupt Latency=%dl\n",up->timeout);
up->systime1=0;
up->systime=0;
unsigned int iir,lsr;
unsigned int type;
irqreturn_t ret=IRQ_NONE;
int err;
int max_count = 256;
rtdm_lockctx_t context1;
printk("I am in rtdm_my_isr......!!!\n");
printk("Local struct up=%x\n",up);
err = rtdm_irq_disable(&up->irq_handle);
if(err<0)
rtdm_printk("error in rtdm_irq_enable\n");
rtdm_lock_get_irqsave(&up->lock,context1);
do{
iir = serial_in(up,UART_IIR);
if(iir & UART_IIR_NO_INT)
break;
ret=IRQ_HANDLED;
lsr = serial_in(up,UART_LSR);
type = iir & 0x3e;
switch(type)
{
case UART_IIR_THRI:
printk("type of int:UART_IIR_THRI\n");
transmit_chars(up,lsr);
rtdm_event_signal(&up->w_event_tx);
break;
case UART_IIR_RX_TIMEOUT:
/*FALLTHROUGH*/
case UART_IIR_RDI:
printk("type of int:UART_IIR_RDI\n");
serial_omap_rdi(up,lsr);
rtdm_event_signal(&up->w_event_rx);
break;
case UART_IIR_RLSI:
printk("type of int:UART_IIR_RLSI\n");
// serial_omap_rlsi(up,lsr);
break;
case UART_IIR_CTS_RTS_DSR:
break;
case UART_IIR_XOFF:
/*simpleThrough*/
default:
break;
}
}while(!(iir & UART_IIR_NO_INT) && max_count--);
rtdm_lock_put_irqrestore(&up->lock,context1);
err = rtdm_irq_enable(&up->irq_handle);
if(err<0)
rtdm_printk("error in rtdm_irq_enable\n");
printk("rtdm_irq ended\n");
up->systime = rtdm_clock_read();
return RTDM_IRQ_HANDLED;
}
static int uart_open_nrt(struct rtdm_dev_context *context,rtdm_user_info_t *user_info_t,int oflags_t)
{
MY_DEV *up=(MY_DEV *)context->device->device_data;
// rtdm_lockctx_t context1;
int retval;
printk("Local struct up=%x\n",up);
f_cir_buf(up);
rtdm_lock_init(&up->lock);
rtdm_event_init(&up->w_event_tx,0);
rtdm_event_init(&up->w_event_rx,0);
printk("name of irq=%s\n",up->name);
retval = request_irq(up->irq, serial_omap_irq,0, up->name, up);
// if (retval)
// return retval;
retval=rtdm_irq_request(&up->irq_handle,up->irq,rtdm_my_isr,0,up->name,up);
if(retval<0)
{
rtdm_printk("error in requesting irq\n");
dev_err(up->dev, "failure requesting irq %i\n", up->irq);
return retval;
}
dev_dbg(up->dev, "serial_omap_startup+%d\n", up->line);
serial_omap_clear_fifos(up);
serial_out(up,UART_MCR,UART_MCR_RTS);
(void)serial_in(up,UART_LSR);
if(serial_in(up,UART_LSR) & UART_LSR_DR)
(void)serial_in(up,UART_RX);
(void)serial_in(up,UART_IIR);
(void)serial_in(up,UART_MSR);
/*
* Now, initialize the UART
*/
serial_out(up, UART_LCR, UART_LCR_WLEN8);
printk("UART has word length of 8 bit\n");
up->msr_saved_flags=0;
//enabling interrupts
up->ier = UART_IER_RLSI | UART_IER_RDI;
serial_out(up,UART_IER,up->ier);
printk("enabling RLSI and RDI interrupt\n");
//enable module level wake up
serial_out(up,UART_OMAP_WER,OMAP_UART_WER_MOD_WKUP);
printk("OMAP_UART_WER_MOD_WKUP\n");
// up->port_activity=jiffies;
return 0;
}
static int uart_close_nrt(struct rtdm_dev_context *context,rtdm_user_info_t * user_info)
{
int err;
MY_DEV *up=(MY_DEV *)context->device->device_data;
dev_dbg(up->dev, "serial_omap_shutdown+%d\n", up->line);
up->ier = 0;
serial_out(up, UART_IER, 0);
//disable break condition and FIFOs
serial_out(up,UART_LCR,serial_in(up,UART_LCR) & ~UART_LCR_SBC);
serial_omap_clear_fifos(up);
//read data port to reset things and then free irq
if(serial_in(up,UART_LSR) & UART_LSR_DR)
(void)serial_in(up,UART_RX);
err=rtdm_irq_disable(&up->irq_handle);//enable irq
if(err<0)
{
rtdm_printk("error in rtdm_irq_disable\n");
return err;
}
rtdm_printk("rtdm_irq_disable\n");
rtdm_irq_free(&up->irq_handle);
free_irq(up->irq, up);
return 0;
}
#if defined(CONFIG_OF)
static const struct of_device_id omap_i2c_of_match[] = {
{ .compatible = "jay,serial" },
{ .compatible = "jay,serial" },
{ .compatible = "jay,serial" },
{},
};
MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
#endif
static struct rtdm_device uart_device = {
.struct_version = RTDM_DEVICE_STRUCT_VER,
.device_flags = RTDM_NAMED_DEVICE,
.context_size = sizeof(MY_DEV),
.device_name = DEVICE_NAME_1,
.proc_name = DEVICE_NAME_1,
.open_nrt = uart_open_nrt,
.ops={
.close_nrt = uart_close_nrt,
.read_rt = uart_rd_rt,
.write_rt = uart_wr_rt,
.ioctl_rt = uart_ioctl_rt,
},
.device_class =RTDM_CLASS_SERIAL,
.device_sub_class =2015,
.profile_version =1,
.driver_name =DRIVER_NAME,
.driver_version =RTDM_DRIVER_VER(1,1,0),
.peripheral_name ="RTDM UART MASTER",
.provider_name ="JAY KOTHARI",
};
static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
{
u32 mvr, scheme;
u16 revision, major, minor;
printk(".................omap_serial_fill_feature_erratas\n");
mvr = serial_in(up, UART_OMAP_MVER);//* Module version register */
/* Check revision register scheme */
scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
switch (scheme)
{
case 0: /* Legacy Scheme: OMAP2/3 */
/* MINOR_REV[0:4], MAJOR_REV[4:7] */
major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
printk("case_0\n");
break;
case 1:
/* New Scheme: OMAP4+ */
/* MINOR_REV[0:5], MAJOR_REV[8:10] */
major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
OMAP_UART_MVR_MAJ_SHIFT;
minor = (mvr & OMAP_UART_MVR_MIN_MASK);
printk("case_1\n");
break;
default:
dev_warn(up->dev,"Unknown %s revision, defaulting to highest\n",up->name);
/* highest possible revision */
major = 0xff;
minor = 0xff;
printk("default\n");
}
/* normalize revision for the driver */
revision = UART_BUILD_REVISION(major, minor);
switch (revision)
{
case OMAP_UART_REV_46:
printk("revision number: OMAP_UART_REV_46\n");
up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | UART_ERRATA_i291_DMA_FORCEIDLE);