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rme9652.c
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/*
* ALSA driver for RME Digi9652 audio interfaces
*
* Copyright (c) 1999 IEM - Winfried Ritsch
* Copyright (c) 1999-2001 Paul Davis
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/module.h>
#include <linux/io.h>
#include <sound/core.h>
#include <sound/control.h>
#include <sound/pcm.h>
#include <sound/info.h>
#include <sound/asoundef.h>
#include <sound/initval.h>
#include <asm/current.h>
static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
static bool precise_ptr[SNDRV_CARDS]; /* Enable precise pointer */
module_param_array(index, int, NULL, 0444);
MODULE_PARM_DESC(index, "Index value for RME Digi9652 (Hammerfall) soundcard.");
module_param_array(id, charp, NULL, 0444);
MODULE_PARM_DESC(id, "ID string for RME Digi9652 (Hammerfall) soundcard.");
module_param_array(enable, bool, NULL, 0444);
MODULE_PARM_DESC(enable, "Enable/disable specific RME96{52,36} soundcards.");
module_param_array(precise_ptr, bool, NULL, 0444);
MODULE_PARM_DESC(precise_ptr, "Enable precise pointer (doesn't work reliably).");
MODULE_AUTHOR("Paul Davis <pbd@op.net>, Winfried Ritsch");
MODULE_DESCRIPTION("RME Digi9652/Digi9636");
MODULE_LICENSE("GPL");
MODULE_SUPPORTED_DEVICE("{{RME,Hammerfall},"
"{RME,Hammerfall-Light}}");
/* The Hammerfall has two sets of 24 ADAT + 2 S/PDIF channels, one for
capture, one for playback. Both the ADAT and S/PDIF channels appear
to the host CPU in the same block of memory. There is no functional
difference between them in terms of access.
The Hammerfall Light is identical to the Hammerfall, except that it
has 2 sets 18 channels (16 ADAT + 2 S/PDIF) for capture and playback.
*/
#define RME9652_NCHANNELS 26
#define RME9636_NCHANNELS 18
/* Preferred sync source choices - used by "sync_pref" control switch */
#define RME9652_SYNC_FROM_SPDIF 0
#define RME9652_SYNC_FROM_ADAT1 1
#define RME9652_SYNC_FROM_ADAT2 2
#define RME9652_SYNC_FROM_ADAT3 3
/* Possible sources of S/PDIF input */
#define RME9652_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
#define RME9652_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
#define RME9652_SPDIFIN_INTERN 2 /* internal (CDROM) */
/* ------------- Status-Register bits --------------------- */
#define RME9652_IRQ (1<<0) /* IRQ is High if not reset by irq_clear */
#define RME9652_lock_2 (1<<1) /* ADAT 3-PLL: 1=locked, 0=unlocked */
#define RME9652_lock_1 (1<<2) /* ADAT 2-PLL: 1=locked, 0=unlocked */
#define RME9652_lock_0 (1<<3) /* ADAT 1-PLL: 1=locked, 0=unlocked */
#define RME9652_fs48 (1<<4) /* sample rate is 0=44.1/88.2,1=48/96 Khz */
#define RME9652_wsel_rd (1<<5) /* if Word-Clock is used and valid then 1 */
/* bits 6-15 encode h/w buffer pointer position */
#define RME9652_sync_2 (1<<16) /* if ADAT-IN 3 in sync to system clock */
#define RME9652_sync_1 (1<<17) /* if ADAT-IN 2 in sync to system clock */
#define RME9652_sync_0 (1<<18) /* if ADAT-IN 1 in sync to system clock */
#define RME9652_DS_rd (1<<19) /* 1=Double Speed Mode, 0=Normal Speed */
#define RME9652_tc_busy (1<<20) /* 1=time-code copy in progress (960ms) */
#define RME9652_tc_out (1<<21) /* time-code out bit */
#define RME9652_F_0 (1<<22) /* 000=64kHz, 100=88.2kHz, 011=96kHz */
#define RME9652_F_1 (1<<23) /* 111=32kHz, 110=44.1kHz, 101=48kHz, */
#define RME9652_F_2 (1<<24) /* external Crystal Chip if ERF=1 */
#define RME9652_ERF (1<<25) /* Error-Flag of SDPIF Receiver (1=No Lock) */
#define RME9652_buffer_id (1<<26) /* toggles by each interrupt on rec/play */
#define RME9652_tc_valid (1<<27) /* 1 = a signal is detected on time-code input */
#define RME9652_SPDIF_READ (1<<28) /* byte available from Rev 1.5+ S/PDIF interface */
#define RME9652_sync (RME9652_sync_0|RME9652_sync_1|RME9652_sync_2)
#define RME9652_lock (RME9652_lock_0|RME9652_lock_1|RME9652_lock_2)
#define RME9652_F (RME9652_F_0|RME9652_F_1|RME9652_F_2)
#define rme9652_decode_spdif_rate(x) ((x)>>22)
/* Bit 6..15 : h/w buffer pointer */
#define RME9652_buf_pos 0x000FFC0
/* Bits 31,30,29 are bits 5,4,3 of h/w pointer position on later
Rev G EEPROMS and Rev 1.5 cards or later.
*/
#define RME9652_REV15_buf_pos(x) ((((x)&0xE0000000)>>26)|((x)&RME9652_buf_pos))
/* amount of io space we remap for register access. i'm not sure we
even need this much, but 1K is nice round number :)
*/
#define RME9652_IO_EXTENT 1024
#define RME9652_init_buffer 0
#define RME9652_play_buffer 32 /* holds ptr to 26x64kBit host RAM */
#define RME9652_rec_buffer 36 /* holds ptr to 26x64kBit host RAM */
#define RME9652_control_register 64
#define RME9652_irq_clear 96
#define RME9652_time_code 100 /* useful if used with alesis adat */
#define RME9652_thru_base 128 /* 132...228 Thru for 26 channels */
/* Read-only registers */
/* Writing to any of the register locations writes to the status
register. We'll use the first location as our point of access.
*/
#define RME9652_status_register 0
/* --------- Control-Register Bits ---------------- */
#define RME9652_start_bit (1<<0) /* start record/play */
/* bits 1-3 encode buffersize/latency */
#define RME9652_Master (1<<4) /* Clock Mode Master=1,Slave/Auto=0 */
#define RME9652_IE (1<<5) /* Interrupt Enable */
#define RME9652_freq (1<<6) /* samplerate 0=44.1/88.2, 1=48/96 kHz */
#define RME9652_freq1 (1<<7) /* if 0, 32kHz, else always 1 */
#define RME9652_DS (1<<8) /* Doule Speed 0=44.1/48, 1=88.2/96 Khz */
#define RME9652_PRO (1<<9) /* S/PDIF out: 0=consumer, 1=professional */
#define RME9652_EMP (1<<10) /* Emphasis 0=None, 1=ON */
#define RME9652_Dolby (1<<11) /* Non-audio bit 1=set, 0=unset */
#define RME9652_opt_out (1<<12) /* Use 1st optical OUT as SPDIF: 1=yes,0=no */
#define RME9652_wsel (1<<13) /* use Wordclock as sync (overwrites master) */
#define RME9652_inp_0 (1<<14) /* SPDIF-IN: 00=optical (ADAT1), */
#define RME9652_inp_1 (1<<15) /* 01=koaxial (Cinch), 10=Internal CDROM */
#define RME9652_SyncPref_ADAT2 (1<<16)
#define RME9652_SyncPref_ADAT3 (1<<17)
#define RME9652_SPDIF_RESET (1<<18) /* Rev 1.5+: h/w S/PDIF receiver */
#define RME9652_SPDIF_SELECT (1<<19)
#define RME9652_SPDIF_CLOCK (1<<20)
#define RME9652_SPDIF_WRITE (1<<21)
#define RME9652_ADAT1_INTERNAL (1<<22) /* Rev 1.5+: if set, internal CD connector carries ADAT */
/* buffersize = 512Bytes * 2^n, where n is made from Bit2 ... Bit0 */
#define RME9652_latency 0x0e
#define rme9652_encode_latency(x) (((x)&0x7)<<1)
#define rme9652_decode_latency(x) (((x)>>1)&0x7)
#define rme9652_running_double_speed(s) ((s)->control_register & RME9652_DS)
#define RME9652_inp (RME9652_inp_0|RME9652_inp_1)
#define rme9652_encode_spdif_in(x) (((x)&0x3)<<14)
#define rme9652_decode_spdif_in(x) (((x)>>14)&0x3)
#define RME9652_SyncPref_Mask (RME9652_SyncPref_ADAT2|RME9652_SyncPref_ADAT3)
#define RME9652_SyncPref_ADAT1 0
#define RME9652_SyncPref_SPDIF (RME9652_SyncPref_ADAT2|RME9652_SyncPref_ADAT3)
/* the size of a substream (1 mono data stream) */
#define RME9652_CHANNEL_BUFFER_SAMPLES (16*1024)
#define RME9652_CHANNEL_BUFFER_BYTES (4*RME9652_CHANNEL_BUFFER_SAMPLES)
/* the size of the area we need to allocate for DMA transfers. the
size is the same regardless of the number of channels - the
9636 still uses the same memory area.
Note that we allocate 1 more channel than is apparently needed
because the h/w seems to write 1 byte beyond the end of the last
page. Sigh.
*/
#define RME9652_DMA_AREA_BYTES ((RME9652_NCHANNELS+1) * RME9652_CHANNEL_BUFFER_BYTES)
#define RME9652_DMA_AREA_KILOBYTES (RME9652_DMA_AREA_BYTES/1024)
struct snd_rme9652 {
int dev;
spinlock_t lock;
int irq;
unsigned long port;
void __iomem *iobase;
int precise_ptr;
u32 control_register; /* cached value */
u32 thru_bits; /* thru 1=on, 0=off channel 1=Bit1... channel 26= Bit26 */
u32 creg_spdif;
u32 creg_spdif_stream;
char *card_name; /* hammerfall or hammerfall light names */
size_t hw_offsetmask; /* &-with status register to get real hw_offset */
size_t prev_hw_offset; /* previous hw offset */
size_t max_jitter; /* maximum jitter in frames for
hw pointer */
size_t period_bytes; /* guess what this is */
unsigned char ds_channels;
unsigned char ss_channels; /* different for hammerfall/hammerfall-light */
struct snd_dma_buffer playback_dma_buf;
struct snd_dma_buffer capture_dma_buf;
unsigned char *capture_buffer; /* suitably aligned address */
unsigned char *playback_buffer; /* suitably aligned address */
pid_t capture_pid;
pid_t playback_pid;
struct snd_pcm_substream *capture_substream;
struct snd_pcm_substream *playback_substream;
int running;
int passthru; /* non-zero if doing pass-thru */
int hw_rev; /* h/w rev * 10 (i.e. 1.5 has hw_rev = 15) */
int last_spdif_sample_rate; /* so that we can catch externally ... */
int last_adat_sample_rate; /* ... induced rate changes */
char *channel_map;
struct snd_card *card;
struct snd_pcm *pcm;
struct pci_dev *pci;
struct snd_kcontrol *spdif_ctl;
};
/* These tables map the ALSA channels 1..N to the channels that we
need to use in order to find the relevant channel buffer. RME
refer to this kind of mapping as between "the ADAT channel and
the DMA channel." We index it using the logical audio channel,
and the value is the DMA channel (i.e. channel buffer number)
where the data for that channel can be read/written from/to.
*/
static char channel_map_9652_ss[26] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
18, 19, 20, 21, 22, 23, 24, 25
};
static char channel_map_9636_ss[26] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
/* channels 16 and 17 are S/PDIF */
24, 25,
/* channels 18-25 don't exist */
-1, -1, -1, -1, -1, -1, -1, -1
};
static char channel_map_9652_ds[26] = {
/* ADAT channels are remapped */
1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
/* channels 12 and 13 are S/PDIF */
24, 25,
/* others don't exist */
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
};
static char channel_map_9636_ds[26] = {
/* ADAT channels are remapped */
1, 3, 5, 7, 9, 11, 13, 15,
/* channels 8 and 9 are S/PDIF */
24, 25,
/* others don't exist */
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
};
static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
{
dmab->dev.type = SNDRV_DMA_TYPE_DEV;
dmab->dev.dev = snd_dma_pci_data(pci);
if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
size, dmab) < 0)
return -ENOMEM;
return 0;
}
static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
{
if (dmab->area)
snd_dma_free_pages(dmab);
}
static const struct pci_device_id snd_rme9652_ids[] = {
{
.vendor = 0x10ee,
.device = 0x3fc4,
.subvendor = PCI_ANY_ID,
.subdevice = PCI_ANY_ID,
}, /* RME Digi9652 */
{ 0, },
};
MODULE_DEVICE_TABLE(pci, snd_rme9652_ids);
static inline void rme9652_write(struct snd_rme9652 *rme9652, int reg, int val)
{
writel(val, rme9652->iobase + reg);
}
static inline unsigned int rme9652_read(struct snd_rme9652 *rme9652, int reg)
{
return readl(rme9652->iobase + reg);
}
static inline int snd_rme9652_use_is_exclusive(struct snd_rme9652 *rme9652)
{
unsigned long flags;
int ret = 1;
spin_lock_irqsave(&rme9652->lock, flags);
if ((rme9652->playback_pid != rme9652->capture_pid) &&
(rme9652->playback_pid >= 0) && (rme9652->capture_pid >= 0)) {
ret = 0;
}
spin_unlock_irqrestore(&rme9652->lock, flags);
return ret;
}
static inline int rme9652_adat_sample_rate(struct snd_rme9652 *rme9652)
{
if (rme9652_running_double_speed(rme9652)) {
return (rme9652_read(rme9652, RME9652_status_register) &
RME9652_fs48) ? 96000 : 88200;
} else {
return (rme9652_read(rme9652, RME9652_status_register) &
RME9652_fs48) ? 48000 : 44100;
}
}
static inline void rme9652_compute_period_size(struct snd_rme9652 *rme9652)
{
unsigned int i;
i = rme9652->control_register & RME9652_latency;
rme9652->period_bytes = 1 << ((rme9652_decode_latency(i) + 8));
rme9652->hw_offsetmask =
(rme9652->period_bytes * 2 - 1) & RME9652_buf_pos;
rme9652->max_jitter = 80;
}
static snd_pcm_uframes_t rme9652_hw_pointer(struct snd_rme9652 *rme9652)
{
int status;
unsigned int offset, frag;
snd_pcm_uframes_t period_size = rme9652->period_bytes / 4;
snd_pcm_sframes_t delta;
status = rme9652_read(rme9652, RME9652_status_register);
if (!rme9652->precise_ptr)
return (status & RME9652_buffer_id) ? period_size : 0;
offset = status & RME9652_buf_pos;
/* The hardware may give a backward movement for up to 80 frames
Martin Kirst <martin.kirst@freenet.de> knows the details.
*/
delta = rme9652->prev_hw_offset - offset;
delta &= 0xffff;
if (delta <= (snd_pcm_sframes_t)rme9652->max_jitter * 4)
offset = rme9652->prev_hw_offset;
else
rme9652->prev_hw_offset = offset;
offset &= rme9652->hw_offsetmask;
offset /= 4;
frag = status & RME9652_buffer_id;
if (offset < period_size) {
if (offset > rme9652->max_jitter) {
if (frag)
dev_err(rme9652->card->dev,
"Unexpected hw_pointer position (bufid == 0): status: %x offset: %d\n",
status, offset);
} else if (!frag)
return 0;
offset -= rme9652->max_jitter;
if ((int)offset < 0)
offset += period_size * 2;
} else {
if (offset > period_size + rme9652->max_jitter) {
if (!frag)
dev_err(rme9652->card->dev,
"Unexpected hw_pointer position (bufid == 1): status: %x offset: %d\n",
status, offset);
} else if (frag)
return period_size;
offset -= rme9652->max_jitter;
}
return offset;
}
static inline void rme9652_reset_hw_pointer(struct snd_rme9652 *rme9652)
{
int i;
/* reset the FIFO pointer to zero. We do this by writing to 8
registers, each of which is a 32bit wide register, and set
them all to zero. Note that s->iobase is a pointer to
int32, not pointer to char.
*/
for (i = 0; i < 8; i++) {
rme9652_write(rme9652, i * 4, 0);
udelay(10);
}
rme9652->prev_hw_offset = 0;
}
static inline void rme9652_start(struct snd_rme9652 *s)
{
s->control_register |= (RME9652_IE | RME9652_start_bit);
rme9652_write(s, RME9652_control_register, s->control_register);
}
static inline void rme9652_stop(struct snd_rme9652 *s)
{
s->control_register &= ~(RME9652_start_bit | RME9652_IE);
rme9652_write(s, RME9652_control_register, s->control_register);
}
static int rme9652_set_interrupt_interval(struct snd_rme9652 *s,
unsigned int frames)
{
int restart = 0;
int n;
spin_lock_irq(&s->lock);
if ((restart = s->running)) {
rme9652_stop(s);
}
frames >>= 7;
n = 0;
while (frames) {
n++;
frames >>= 1;
}
s->control_register &= ~RME9652_latency;
s->control_register |= rme9652_encode_latency(n);
rme9652_write(s, RME9652_control_register, s->control_register);
rme9652_compute_period_size(s);
if (restart)
rme9652_start(s);
spin_unlock_irq(&s->lock);
return 0;
}
static int rme9652_set_rate(struct snd_rme9652 *rme9652, int rate)
{
int restart;
int reject_if_open = 0;
int xrate;
if (!snd_rme9652_use_is_exclusive (rme9652)) {
return -EBUSY;
}
/* Changing from a "single speed" to a "double speed" rate is
not allowed if any substreams are open. This is because
such a change causes a shift in the location of
the DMA buffers and a reduction in the number of available
buffers.
Note that a similar but essentially insoluble problem
exists for externally-driven rate changes. All we can do
is to flag rate changes in the read/write routines.
*/
spin_lock_irq(&rme9652->lock);
xrate = rme9652_adat_sample_rate(rme9652);
switch (rate) {
case 44100:
if (xrate > 48000) {
reject_if_open = 1;
}
rate = 0;
break;
case 48000:
if (xrate > 48000) {
reject_if_open = 1;
}
rate = RME9652_freq;
break;
case 88200:
if (xrate < 48000) {
reject_if_open = 1;
}
rate = RME9652_DS;
break;
case 96000:
if (xrate < 48000) {
reject_if_open = 1;
}
rate = RME9652_DS | RME9652_freq;
break;
default:
spin_unlock_irq(&rme9652->lock);
return -EINVAL;
}
if (reject_if_open && (rme9652->capture_pid >= 0 || rme9652->playback_pid >= 0)) {
spin_unlock_irq(&rme9652->lock);
return -EBUSY;
}
if ((restart = rme9652->running)) {
rme9652_stop(rme9652);
}
rme9652->control_register &= ~(RME9652_freq | RME9652_DS);
rme9652->control_register |= rate;
rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
if (restart) {
rme9652_start(rme9652);
}
if (rate & RME9652_DS) {
if (rme9652->ss_channels == RME9652_NCHANNELS) {
rme9652->channel_map = channel_map_9652_ds;
} else {
rme9652->channel_map = channel_map_9636_ds;
}
} else {
if (rme9652->ss_channels == RME9652_NCHANNELS) {
rme9652->channel_map = channel_map_9652_ss;
} else {
rme9652->channel_map = channel_map_9636_ss;
}
}
spin_unlock_irq(&rme9652->lock);
return 0;
}
static void rme9652_set_thru(struct snd_rme9652 *rme9652, int channel, int enable)
{
int i;
rme9652->passthru = 0;
if (channel < 0) {
/* set thru for all channels */
if (enable) {
for (i = 0; i < RME9652_NCHANNELS; i++) {
rme9652->thru_bits |= (1 << i);
rme9652_write(rme9652, RME9652_thru_base + i * 4, 1);
}
} else {
for (i = 0; i < RME9652_NCHANNELS; i++) {
rme9652->thru_bits &= ~(1 << i);
rme9652_write(rme9652, RME9652_thru_base + i * 4, 0);
}
}
} else {
int mapped_channel;
mapped_channel = rme9652->channel_map[channel];
if (enable) {
rme9652->thru_bits |= (1 << mapped_channel);
} else {
rme9652->thru_bits &= ~(1 << mapped_channel);
}
rme9652_write(rme9652,
RME9652_thru_base + mapped_channel * 4,
enable ? 1 : 0);
}
}
static int rme9652_set_passthru(struct snd_rme9652 *rme9652, int onoff)
{
if (onoff) {
rme9652_set_thru(rme9652, -1, 1);
/* we don't want interrupts, so do a
custom version of rme9652_start().
*/
rme9652->control_register =
RME9652_inp_0 |
rme9652_encode_latency(7) |
RME9652_start_bit;
rme9652_reset_hw_pointer(rme9652);
rme9652_write(rme9652, RME9652_control_register,
rme9652->control_register);
rme9652->passthru = 1;
} else {
rme9652_set_thru(rme9652, -1, 0);
rme9652_stop(rme9652);
rme9652->passthru = 0;
}
return 0;
}
static void rme9652_spdif_set_bit (struct snd_rme9652 *rme9652, int mask, int onoff)
{
if (onoff)
rme9652->control_register |= mask;
else
rme9652->control_register &= ~mask;
rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
}
static void rme9652_spdif_write_byte (struct snd_rme9652 *rme9652, const int val)
{
long mask;
long i;
for (i = 0, mask = 0x80; i < 8; i++, mask >>= 1) {
if (val & mask)
rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_WRITE, 1);
else
rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_WRITE, 0);
rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 1);
rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 0);
}
}
static int rme9652_spdif_read_byte (struct snd_rme9652 *rme9652)
{
long mask;
long val;
long i;
val = 0;
for (i = 0, mask = 0x80; i < 8; i++, mask >>= 1) {
rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 1);
if (rme9652_read (rme9652, RME9652_status_register) & RME9652_SPDIF_READ)
val |= mask;
rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 0);
}
return val;
}
static void rme9652_write_spdif_codec (struct snd_rme9652 *rme9652, const int address, const int data)
{
rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 1);
rme9652_spdif_write_byte (rme9652, 0x20);
rme9652_spdif_write_byte (rme9652, address);
rme9652_spdif_write_byte (rme9652, data);
rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 0);
}
static int rme9652_spdif_read_codec (struct snd_rme9652 *rme9652, const int address)
{
int ret;
rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 1);
rme9652_spdif_write_byte (rme9652, 0x20);
rme9652_spdif_write_byte (rme9652, address);
rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 0);
rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 1);
rme9652_spdif_write_byte (rme9652, 0x21);
ret = rme9652_spdif_read_byte (rme9652);
rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 0);
return ret;
}
static void rme9652_initialize_spdif_receiver (struct snd_rme9652 *rme9652)
{
/* XXX what unsets this ? */
rme9652->control_register |= RME9652_SPDIF_RESET;
rme9652_write_spdif_codec (rme9652, 4, 0x40);
rme9652_write_spdif_codec (rme9652, 17, 0x13);
rme9652_write_spdif_codec (rme9652, 6, 0x02);
}
static inline int rme9652_spdif_sample_rate(struct snd_rme9652 *s)
{
unsigned int rate_bits;
if (rme9652_read(s, RME9652_status_register) & RME9652_ERF) {
return -1; /* error condition */
}
if (s->hw_rev == 15) {
int x, y, ret;
x = rme9652_spdif_read_codec (s, 30);
if (x != 0)
y = 48000 * 64 / x;
else
y = 0;
if (y > 30400 && y < 33600) ret = 32000;
else if (y > 41900 && y < 46000) ret = 44100;
else if (y > 46000 && y < 50400) ret = 48000;
else if (y > 60800 && y < 67200) ret = 64000;
else if (y > 83700 && y < 92000) ret = 88200;
else if (y > 92000 && y < 100000) ret = 96000;
else ret = 0;
return ret;
}
rate_bits = rme9652_read(s, RME9652_status_register) & RME9652_F;
switch (rme9652_decode_spdif_rate(rate_bits)) {
case 0x7:
return 32000;
break;
case 0x6:
return 44100;
break;
case 0x5:
return 48000;
break;
case 0x4:
return 88200;
break;
case 0x3:
return 96000;
break;
case 0x0:
return 64000;
break;
default:
dev_err(s->card->dev,
"%s: unknown S/PDIF input rate (bits = 0x%x)\n",
s->card_name, rate_bits);
return 0;
break;
}
}
/*-----------------------------------------------------------------------------
Control Interface
----------------------------------------------------------------------------*/
static u32 snd_rme9652_convert_from_aes(struct snd_aes_iec958 *aes)
{
u32 val = 0;
val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME9652_PRO : 0;
val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME9652_Dolby : 0;
if (val & RME9652_PRO)
val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME9652_EMP : 0;
else
val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME9652_EMP : 0;
return val;
}
static void snd_rme9652_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
{
aes->status[0] = ((val & RME9652_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
((val & RME9652_Dolby) ? IEC958_AES0_NONAUDIO : 0);
if (val & RME9652_PRO)
aes->status[0] |= (val & RME9652_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
else
aes->status[0] |= (val & RME9652_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
}
static int snd_rme9652_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
uinfo->count = 1;
return 0;
}
static int snd_rme9652_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
snd_rme9652_convert_to_aes(&ucontrol->value.iec958, rme9652->creg_spdif);
return 0;
}
static int snd_rme9652_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
int change;
u32 val;
val = snd_rme9652_convert_from_aes(&ucontrol->value.iec958);
spin_lock_irq(&rme9652->lock);
change = val != rme9652->creg_spdif;
rme9652->creg_spdif = val;
spin_unlock_irq(&rme9652->lock);
return change;
}
static int snd_rme9652_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
uinfo->count = 1;
return 0;
}
static int snd_rme9652_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
snd_rme9652_convert_to_aes(&ucontrol->value.iec958, rme9652->creg_spdif_stream);
return 0;
}
static int snd_rme9652_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
int change;
u32 val;
val = snd_rme9652_convert_from_aes(&ucontrol->value.iec958);
spin_lock_irq(&rme9652->lock);
change = val != rme9652->creg_spdif_stream;
rme9652->creg_spdif_stream = val;
rme9652->control_register &= ~(RME9652_PRO | RME9652_Dolby | RME9652_EMP);
rme9652_write(rme9652, RME9652_control_register, rme9652->control_register |= val);
spin_unlock_irq(&rme9652->lock);
return change;
}
static int snd_rme9652_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
{
uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
uinfo->count = 1;
return 0;
}
static int snd_rme9652_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
ucontrol->value.iec958.status[0] = kcontrol->private_value;
return 0;
}
#define RME9652_ADAT1_IN(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
.info = snd_rme9652_info_adat1_in, \
.get = snd_rme9652_get_adat1_in, \
.put = snd_rme9652_put_adat1_in }
static unsigned int rme9652_adat1_in(struct snd_rme9652 *rme9652)
{
if (rme9652->control_register & RME9652_ADAT1_INTERNAL)
return 1;
return 0;
}
static int rme9652_set_adat1_input(struct snd_rme9652 *rme9652, int internal)
{
int restart = 0;
if (internal) {
rme9652->control_register |= RME9652_ADAT1_INTERNAL;
} else {
rme9652->control_register &= ~RME9652_ADAT1_INTERNAL;
}
/* XXX do we actually need to stop the card when we do this ? */
if ((restart = rme9652->running)) {
rme9652_stop(rme9652);
}
rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
if (restart) {
rme9652_start(rme9652);
}
return 0;
}
static int snd_rme9652_info_adat1_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
{
static const char * const texts[2] = {"ADAT1", "Internal"};
return snd_ctl_enum_info(uinfo, 1, 2, texts);
}
static int snd_rme9652_get_adat1_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
spin_lock_irq(&rme9652->lock);
ucontrol->value.enumerated.item[0] = rme9652_adat1_in(rme9652);
spin_unlock_irq(&rme9652->lock);
return 0;
}
static int snd_rme9652_put_adat1_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
int change;
unsigned int val;
if (!snd_rme9652_use_is_exclusive(rme9652))
return -EBUSY;
val = ucontrol->value.enumerated.item[0] % 2;
spin_lock_irq(&rme9652->lock);
change = val != rme9652_adat1_in(rme9652);
if (change)
rme9652_set_adat1_input(rme9652, val);
spin_unlock_irq(&rme9652->lock);
return change;
}
#define RME9652_SPDIF_IN(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
.info = snd_rme9652_info_spdif_in, \
.get = snd_rme9652_get_spdif_in, .put = snd_rme9652_put_spdif_in }
static unsigned int rme9652_spdif_in(struct snd_rme9652 *rme9652)
{
return rme9652_decode_spdif_in(rme9652->control_register &
RME9652_inp);
}
static int rme9652_set_spdif_input(struct snd_rme9652 *rme9652, int in)
{
int restart = 0;
rme9652->control_register &= ~RME9652_inp;
rme9652->control_register |= rme9652_encode_spdif_in(in);
if ((restart = rme9652->running)) {
rme9652_stop(rme9652);
}
rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
if (restart) {
rme9652_start(rme9652);
}
return 0;
}
static int snd_rme9652_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
{
static const char * const texts[3] = {"ADAT1", "Coaxial", "Internal"};
return snd_ctl_enum_info(uinfo, 1, 3, texts);
}
static int snd_rme9652_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
spin_lock_irq(&rme9652->lock);
ucontrol->value.enumerated.item[0] = rme9652_spdif_in(rme9652);
spin_unlock_irq(&rme9652->lock);
return 0;