diff --git a/README.md b/README.md index 43c3c84..4c31b0a 100644 --- a/README.md +++ b/README.md @@ -22,13 +22,14 @@ The following resources contain more information: * [CSDIDAC Middleware RELEASE.md](./RELEASE.md) * [CSDIDAC Middleware API Reference Guide](https://cypresssemiconductorco.github.io/csdidac/csdidac_api_reference_manual/html/index.html) * [ModusToolbox Software Environment, Quick Start Guide, Documentation, and Videos](https://www.cypress.com/products/modustoolbox-software-environment) -* [CSDIDAC Middleware Code Example for MBED OS](https://github.com/cypresssemiconductorco) -* [CSDIDAC Middleware Code Examples at GITHUB](https://github.com/cypresssemiconductorco) +* [CSDIDAC Middleware Code Example for MBED OS](https://github.com/cypresssemiconductorco/mbed-os-example-csdidac) * [ModusToolbox Device Configurator Tool Guide](https://www.cypress.com/ModusToolboxDeviceConfig) * [CapSense Middleware API Reference Guide](https://cypresssemiconductorco.github.io/capsense/capsense_api_reference_manual/html/index.html) * [CSDADC Middleware API Reference Guide](https://cypresssemiconductorco.github.io/csdadc/csdadc_api_reference_manual/html/index.html) * [PSoC 6 Technical Reference Manual](https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-63-ble-architecture-technical-reference) * [PSoC 63 with BLE Datasheet Programmable System-on-Chip datasheet](http://www.cypress.com/ds218787) +* [PSoC 4000S Family: PSoC 4 Architecture Technical Reference Manual (TRM)](https://www.cypress.com/documentation/technical-reference-manuals/psoc-4000s-family-psoc-4-architecture-technical-reference) +* [PSoC 4100S and PSoC 4100S Plus: PSoC 4 Architecture Technical Reference Manual (TRM)](https://www.cypress.com/documentation/technical-reference-manuals/psoc-4100s-and-psoc-4100s-plus-psoc-4-architecture) * [Cypress Semiconductor](http://www.cypress.com) --- diff --git a/RELEASE.md b/RELEASE.md index ad8fdc7..394a2cc 100644 --- a/RELEASE.md +++ b/RELEASE.md @@ -1,46 +1,44 @@ -# Cypress CSDIDAC Middleware Library 2.0 +# Cypress CSDIDAC Middleware Library 2.10 ### What's Included? Please refer to the [README.md](./README.md) and the [API Reference Guide](https://cypresssemiconductorco.github.io/csdidac/csdidac_api_reference_manual/html/index.html) for a complete description of the CSDIDAC Middleware. The revision history of the CSDIDAC Middleware is also available on the [API Reference Guide Changelog](https://cypresssemiconductorco.github.io/csdidac/csdidac_api_reference_manual/html/index.html#group_csdidac_changelog). New in this release: -* Added the new option of joining two IDAC channels -* Updated CSDIDAC configuration structure to be aligned with the list of parameters in ModusToolbox CSD personality +* Added the support for the PSoC 4100S Plus devices -### Defect Fixes -* Fixing a compilation error for non CSDIDAC-capable devices: CSDIDAC MW sources are enclosed with the conditional compilation -* Renamed periClk to cpuClk in CSDIDAC configuration structure - ### Supported Software and Tools This version of the CSDIDAC Middleware was validated for compatibility with the following Software and Tools: -| Software and Tools | Version | -| :--- | :----: | -| ModusToolbox Software Environment | 2.0 | -| - ModusToolbox Device Configurator | 2.0 | -| - ModusToolbox CSD Personality in Device Configurator | 2.0 | -| PSoC6 Peripheral Driver Library (PDL) | 1.2.0 | -| GCC Compiler | 7.2.1 | -| IAR Compiler | 8.32 | -| ARM Compiler 6 | 6.11 | -| MBED OS | 5.13.1 | -| FreeRTOS | 10.0.1 | +| Software and Tools | Version | +| :--- | :----: | +| ModusToolbox Software Environment | 2.1 | +| - ModusToolbox Device Configurator | 2.1 | +| - ModusToolbox CSD Personality for PSoC4 devices in Device Configurator | 1.0 | +| - ModusToolbox CSD Personality for PSoC6 devices in Device Configurator | 2.0 | +| PSoC4 Peripheral Driver Library (PDL) | 1.0.0 | +| PSoC6 Peripheral Driver Library (PDL) | 1.5.0 | +| GCC Compiler | 7.2.1 | +| IAR Compiler | 8.32 | +| ARM Compiler 6 | 6.11 | +| MBED OS | 5.15.1 | +| FreeRTOS | 10.0.1 | ### More information The following resources contain more information: * [CSDIDAC Middleware RELEASE.md](./RELEASE.md) * [CSDIDAC Middleware API Reference Guide](https://cypresssemiconductorco.github.io/csdidac/csdidac_api_reference_manual/html/index.html) * [ModusToolbox Software Environment, Quick Start Guide, Documentation, and Videos](https://www.cypress.com/products/modustoolbox-software-environment) -* [CSDIDAC Middleware Code Example for MBED OS](https://github.com/cypresssemiconductorco) -* [CSDIDAC Middleware Code Examples at GITHUB](https://github.com/cypresssemiconductorco) +* [CSDIDAC Middleware Code Example for MBED OS](https://github.com/cypresssemiconductorco/mbed-os-example-csdidac) * [ModusToolbox Device Configurator Tool Guide](https://www.cypress.com/ModusToolboxDeviceConfig) * [CapSense Middleware API Reference Guide](https://cypresssemiconductorco.github.io/capsense/capsense_api_reference_manual/html/index.html) * [CSDADC Middleware API Reference Guide](https://cypresssemiconductorco.github.io/csdadc/csdadc_api_reference_manual/html/index.html) * [PSoC 6 Technical Reference Manual](https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-63-ble-architecture-technical-reference) * [PSoC 63 with BLE Datasheet Programmable System-on-Chip datasheet](http://www.cypress.com/ds218787) +* [PSoC 4000S Family: PSoC 4 Architecture Technical Reference Manual (TRM)](https://www.cypress.com/documentation/technical-reference-manuals/psoc-4000s-family-psoc-4-architecture-technical-reference) +* [PSoC 4100S and PSoC 4100S Plus: PSoC 4 Architecture Technical Reference Manual (TRM)](https://www.cypress.com/documentation/technical-reference-manuals/psoc-4100s-and-psoc-4100s-plus-psoc-4-architecture) * [Cypress Semiconductor](http://www.cypress.com) --- -© Cypress Semiconductor Corporation, 2019. +© Cypress Semiconductor Corporation, 2019-2020. diff --git a/cy_csdidac.c b/cy_csdidac.c index 63ddfb2..7983509 100644 --- a/cy_csdidac.c +++ b/cy_csdidac.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_csdidac.c -* \version 2.0 +* \version 2.10 * * \brief * This file provides the CSD HW block IDAC functionality implementation. * ******************************************************************************** * \copyright -* Copyright 2019, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2019-2020, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,7 +21,7 @@ #include "cy_gpio.h" #include "cy_csd.h" -#if defined(CY_IP_MXCSDV2) +#if (defined(CY_IP_MXCSDV2) || defined(CY_IP_M0S8CSDV2)) /******************************************************************************* @@ -71,7 +71,7 @@ static void Cy_CSDIDAC_DisconnectChannelB(cy_stc_csdidac_context_t * context); #define CY_CSDIDAC_LEG2_EN_MASK (1uL << CY_CSDIDAC_LEG2_EN_POS) #define CY_CSDIDAC_RANGE_MASK (CY_CSDIDAC_LSB_MASK | CY_CSDIDAC_LEG1_EN_MASK | CY_CSDIDAC_LEG2_EN_MASK) -/* +/* * All the defines below correspond to IDAC LSB in pA */ #define CY_CSDIDAC_LSB_37 ( 37500u) @@ -159,54 +159,54 @@ static void Cy_CSDIDAC_DisconnectChannelB(cy_stc_csdidac_context_t * context); .idacB = 0x00000000uL,\ } - + /******************************************************************************* * Function Name: Cy_CSDIDAC_Init ****************************************************************************//** * -* Captures the CSD HW block and configures it to the default state. -* This function is called by the application program prior to calling +* Captures the CSD HW block and configures it to the default state. +* This function is called by the application program prior to calling * any other middleware function. * -* Initializes the CSDIDAC middleware. Acquires, locks, and initializes +* Initializes the CSDIDAC middleware. Acquires, locks, and initializes * the CSD HW block by using the low-level CSD driver. * The function performs the following tasks: * * Verifies the input parameters. The CY_CSDIDAC_BAD_PARAM is returned if * verification fails. * * Acquires and locks the CSD HW block for use of the CSDIDAC, if the CSD HW * block is in a free state. -* * If the CSD HW block is acquired, it is initialized with -* the CSDIDAC middleware by the default configuration. -* The output pins are not connected to the CSD HW block. +* * If the CSD HW block is acquired, it is initialized with +* the CSDIDAC middleware by the default configuration. +* The output pins are not connected to the CSD HW block. * The outputs are disabled and CY_CSDIDAC_SUCCESS is returned. -* -* To connect an output pin and enable an output current, the -* Cy_CSDIDAC_OutputEnable() or Cy_CSDIDAC_OutputEnableExt() functions +* +* To connect an output pin and enable an output current, the +* Cy_CSDIDAC_OutputEnable() or Cy_CSDIDAC_OutputEnableExt() functions * are used. * If there is no CSD HW block, the CY_CSDIDAC_HW_BUSY status is returned, * and the CSDIDAC middleware waits for the CSD HW block to be in the idle * state to initialize. * * \param config -* The pointer to the configuration structure \ref cy_stc_csdidac_config_t that -* contains the CSDIDAC middleware initial configuration data generated +* The pointer to the configuration structure \ref cy_stc_csdidac_config_t that +* contains the CSDIDAC middleware initial configuration data generated * by the CSD personality of the ModusToolbox Device Configurator tool. * * \param context * The pointer to the CSDIDAC context structure \ref cy_stc_csdidac_context_t -* passed by the user. After the initialization, this structure contains -* both CSDIDAC configuration and internal data. It is used during the whole +* passed by the user. After the initialization, this structure contains +* both CSDIDAC configuration and internal data. It is used during the whole * CSDIDAC operation. * * \return * The function returns the status of its operation. * * CY_CSDIDAC_SUCCESS - The operation is performed successfully. -* * CY_CSDIDAC_BAD_PARAM - The input pointer is NULL or an invalid +* * CY_CSDIDAC_BAD_PARAM - The input pointer is NULL or an invalid * parameter is passed. * * CY_CSDIDAC_HW_LOCKED - The CSD HW block is already in use by other * middleware. * * CY_CSDIDAC_HW_FAILURE - The CSD HW block failure. -* * CY_CSDIDAC_BAD_CONFIGURATION - The CSDIDAC configuration structure +* * CY_CSDIDAC_BAD_CONFIGURATION - The CSDIDAC configuration structure * initialization issue. * *******************************************************************************/ @@ -250,16 +250,16 @@ cy_en_csdidac_status_t Cy_CSDIDAC_Init( * Stops the middleware operation and releases the CSD HW block. * * If any output channel is enabled, it will be disabled and disconnected. -* -* After the CSDIDAC middleware is stopped, the CSD HW block may be -* reconfigured by the application program or other middleware for any -* other usage. -* +* +* After the CSDIDAC middleware is stopped, the CSD HW block may be +* reconfigured by the application program or other middleware for any +* other usage. +* * When the middleware operation is stopped by the Cy_CSDIDAC_DeInit() * function, a subsequent call of the Cy_CSDIDAC_Init() function repeats the -* initialization process. However, to implement Time-multiplexed mode -* (sharing the CSD HW Block between multiple middleware), -* the Cy_CSDIDAC_Save() and Cy_CSDIDAC_Restore() functions are used +* initialization process. However, to implement Time-multiplexed mode +* (sharing the CSD HW Block between multiple middleware), +* the Cy_CSDIDAC_Save() and Cy_CSDIDAC_Restore() functions are used * instead of the Cy_CSDIDAC_DeInit() and Cy_CSDIDAC_Init() functions. * * \param context @@ -268,7 +268,7 @@ cy_en_csdidac_status_t Cy_CSDIDAC_Init( * \return * The function returns the status of its operation. * * CY_CSDIDAC_SUCCESS - The operation is performed successfully. -* * CY_CSDIDAC_BAD_PARAM - The input pointer is NULL or an invalid +* * CY_CSDIDAC_BAD_PARAM - The input pointer is NULL or an invalid * parameter is passed. * * CY_CSDIDAC_HW_LOCKED - The CSD HW block is already in use by other * middleware. @@ -289,8 +289,8 @@ cy_en_csdidac_status_t Cy_CSDIDAC_DeInit(cy_stc_csdidac_context_t * context) * * This function sets the desired CSDIDAC middleware configuration. * The function performs the following: -* * Verifies the input parameters -* * Verifies whether the CSD HW block is captured by the CSDIDAC middleware +* * Verifies the input parameters +* * Verifies whether the CSD HW block is captured by the CSDIDAC middleware * and that there are no active IDAC outputs. * * Initializes the CSD HW block registers with data passed through the * config parameter of this function if the above verifications are @@ -306,13 +306,13 @@ cy_en_csdidac_status_t Cy_CSDIDAC_DeInit(cy_stc_csdidac_context_t * context) * \return * The function returns the status of its operation. * * CY_CSDIDAC_SUCCESS - The operation is performed successfully. -* * CY_CSDIDAC_BAD_PARAM - The input pointer is NULL or an invalid +* * CY_CSDIDAC_BAD_PARAM - The input pointer is NULL or an invalid * parameter is passed. -* * CY_CSDIDAC_HW_BUSY - Any IDAC output is enabled. The operation +* * CY_CSDIDAC_HW_BUSY - Any IDAC output is enabled. The operation * cannot be completed. * * CY_CSDIDAC_HW_LOCKED - The CSD HW block is already in use by other * middleware. -* * CY_CSDIDAC_BAD_CONFIGURATION - The CSDIDAC configuration structure +* * CY_CSDIDAC_BAD_CONFIGURATION - The CSDIDAC configuration structure * initialization issue. * *******************************************************************************/ @@ -322,7 +322,7 @@ cy_en_csdidac_status_t Cy_CSDIDAC_WriteConfig( { cy_en_csdidac_status_t result = CY_CSDIDAC_BAD_PARAM; uint32_t tmpRegValue = CY_CSDIDAC_SW_REFGEN_SEL_IBCB_ON; - + if ((NULL != config) && (NULL != context)) { if(true == Cy_CSDIDAC_IsIdacConfigValid(config)) @@ -372,8 +372,8 @@ cy_en_csdidac_status_t Cy_CSDIDAC_WriteConfig( * Provides a delay required for the CSD HW block to settle after a wakeup * from CPU / System Deep Sleep. * -* This function provides a delay after exiting CPU / System Deep Sleep. -* After the CSD HW block has been powered off, an extra delay is required +* This function provides a delay after exiting CPU / System Deep Sleep. +* After the CSD HW block has been powered off, an extra delay is required * to establish the CSD HW block correct operation. * * \param context @@ -407,12 +407,12 @@ cy_en_csdidac_status_t Cy_CSDIDAC_Wakeup(const cy_stc_csdidac_context_t * contex * * This function handles CPU active to CPU / System Deep Sleep power mode transition * for the CSDIDAC middleware. -* Calling this function directly from the application program is not -* recommended. Instead, Cy_SysPm_CpuEnterDeepSleep() is used for CPU active to +* Calling this function directly from the application program is not +* recommended. Instead, Cy_SysPm_CpuEnterDeepSleep() is used for CPU active to * CPU / System Deep Sleep power mode transition of the device. * \note -* After the CPU Deep Sleep transition, the device automatically goes -* to System Deep Sleep if all conditions are fulfilled: another core is +* After the CPU Deep Sleep transition, the device automatically goes +* to System Deep Sleep if all conditions are fulfilled: another core is * in CPU Deep Sleep, all the peripherals are ready to System Deep Sleep, etc. * (see details in the device TRM). * @@ -473,13 +473,13 @@ cy_en_syspm_status_t Cy_CSDIDAC_DeepSleepCallback( * This function, along with Cy_CSDIDAC_Restore(), is specifically designed * to support time multiplexing of the CSD HW block between multiple * middleware. When the CSD HW block is shared by more than one middleware, -* this function can be used to save the current state of the CSDIDAC middleware +* this function can be used to save the current state of the CSDIDAC middleware * and the CSD HW block prior to releasing the CSD HW block for use by other * middleware. -* +* * This function performs the following operations: * * Saves the current configuration of the CSD HW block and CSDIDAC middleware. -* * Configures the output pins to the default state and disconnects them from +* * Configures the output pins to the default state and disconnects them from * the CSD HW block. Releases the CSD HW block. * * \param context @@ -490,7 +490,7 @@ cy_en_syspm_status_t Cy_CSDIDAC_DeepSleepCallback( * * CY_CSDIDAC_SUCCESS - The operation is performed successfully. * * CY_CSDIDAC_BAD_PARAM - The input pointer is NULL or an invalid parameter * is passed. The operation is not completed. -* * CY_CSDIDAC_HW_LOCKED - The CSD HW block is already in use by other middleware. +* * CY_CSDIDAC_HW_LOCKED - The CSD HW block is already in use by other middleware. * The CSDIDAC middleware cannot save the state * without the initialization or restore operation. * * CY_CSDIDAC_HW_FAILURE - A CSD HW block failure. @@ -511,7 +511,7 @@ cy_en_csdidac_status_t Cy_CSDIDAC_Save(cy_stc_csdidac_context_t * context) /* Releases the HW CSD block. */ initStatus = Cy_CSD_DeInit(context->cfgCopy.base, CY_CSD_IDAC_KEY, context->cfgCopy.csdCxtPtr); - + if (CY_CSD_SUCCESS == initStatus) { result = CY_CSDIDAC_SUCCESS; @@ -519,7 +519,7 @@ cy_en_csdidac_status_t Cy_CSDIDAC_Save(cy_stc_csdidac_context_t * context) else { result = CY_CSDIDAC_HW_FAILURE; - } + } } else { @@ -538,27 +538,27 @@ cy_en_csdidac_status_t Cy_CSDIDAC_Save(cy_stc_csdidac_context_t * context) * Resumes the middleware operation if the Cy_CSDIDAC_Save() function was * called previously. * -* This function, along with the Cy_CSDIDAC_Save() function, is specifically +* This function, along with the Cy_CSDIDAC_Save() function, is specifically * designed to support the CSD HW block time-multiplexing * among multiple middleware. When the CSD HW block is shared by more than one -* middleware, this function can be used to restore the CSD HW block previous -* state and the CSDIDAC middleware saved using the Cy_CSDIDAC_Save() function. -* -* This function performs the Cy_CSDIDAC_Init() function, part tasks -* namely captures the CSD HW block. Use the Cy_CSDIDAC_Save() and -* Cy_CSDIDAC_Restore() functions to implement Time-multiplexed mode +* middleware, this function can be used to restore the CSD HW block previous +* state and the CSDIDAC middleware saved using the Cy_CSDIDAC_Save() function. +* +* This function performs the Cy_CSDIDAC_Init() function, part tasks +* namely captures the CSD HW block. Use the Cy_CSDIDAC_Save() and +* Cy_CSDIDAC_Restore() functions to implement Time-multiplexed mode * instead of using the Cy_CSDIDAC_DeInit() and Cy_CSDIDAC_Init() functions. * * \param context -* The pointer to the CSDIDAC middleware context +* The pointer to the CSDIDAC middleware context * structure \ref cy_stc_csdidac_context_t. * * \return * The function returns the status of its operation. * * CY_CSDIDAC_SUCCESS - The operation is performed successfully. -* * CY_CSDIDAC_BAD_PARAM - The input pointer is NULL or an invalid +* * CY_CSDIDAC_BAD_PARAM - The input pointer is NULL or an invalid * parameter is passed. -* * CY_CSDIDAC_HW_LOCKED - The CSD HW block is already in use by +* * CY_CSDIDAC_HW_LOCKED - The CSD HW block is already in use by * another middleware. * * CY_CSDIDAC_HW_FAILURE - The CSD HW block failure. * @@ -602,7 +602,7 @@ cy_en_csdidac_status_t Cy_CSDIDAC_Restore(cy_stc_csdidac_context_t * context) watchdogCounter--; } while((CY_CSD_BUSY == initStatus) && (0u != watchdogCounter)); - + if (CY_CSD_SUCCESS == initStatus) { /* Captures the CSD HW block for the IDAC functionality. */ @@ -635,37 +635,37 @@ cy_en_csdidac_status_t Cy_CSDIDAC_Restore(cy_stc_csdidac_context_t * context) * * This function performs the following: * * Verifies the input parameters. -* * Identifies LSB and IDAC code required to generate the specified +* * Identifies LSB and IDAC code required to generate the specified * output current and configures the CSD HW block accordingly. -* * Configures and enables the CSDIDAC specified output and returns +* * Configures and enables the CSDIDAC specified output and returns * the status code. * * \param ch -* The CSDIDAC supports two outputs (A and B), this parameter +* The CSDIDAC supports two outputs (A and B), this parameter * specifies the output to be enabled. * * \param current * A current value for an IDAC output in nA with a sign. If the parameter is * positive, a sourcing current is generated. If the parameter is -* negative, the sinking current is generated. The middleware -* identifies LSB and code values required to achieve the specified output -* current. The middleware chooses the minimum possible LSB to generate the +* negative, the sinking current is generated. The middleware +* identifies LSB and code values required to achieve the specified output +* current. The middleware chooses the minimum possible LSB to generate the * current to minimize a quantization error. NOTE! the quantization * error in the output current based on the LSB size (37.5/ * 75/300/600/2400/4800 nA). For instance, if this function * is called to set 123456 nA, the actual output current is rounded -* to the nearest value of multiple to 2400 nA, i.e 122400 nA. The absolute -* value of this parameter is in the range from 0x00u +* to the nearest value of multiple to 2400 nA, i.e 122400 nA. The absolute +* value of this parameter is in the range from 0x00u * to \ref CY_CSDIDAC_MAX_CURRENT_NA. * * \param context -* The pointer to the CSDIDAC middleware context +* The pointer to the CSDIDAC middleware context * structure \ref cy_stc_csdidac_context_t. * * \return * The function returns the status of its operation. * * CY_CSDIDAC_SUCCESS - The operation is performed successfully. -* * CY_CSDIDAC_BAD_PARAM - The input pointer is NULL or an invalid parameter +* * CY_CSDIDAC_BAD_PARAM - The input pointer is NULL or an invalid parameter * is passed. * *******************************************************************************/ @@ -744,11 +744,11 @@ cy_en_csdidac_status_t Cy_CSDIDAC_OutputEnable( * * This function performs the following: * * Verifies the input parameters. -* * Configures and enables the specified output of CSDIDAC and returns the +* * Configures and enables the specified output of CSDIDAC and returns the * status code. * * \param outputCh -* CSDIDAC supports two outputs, this parameter specifies the output to +* CSDIDAC supports two outputs, this parameter specifies the output to * be enabled. * * \param polarity @@ -762,13 +762,13 @@ cy_en_csdidac_status_t Cy_CSDIDAC_OutputEnable( * to \ref CY_CSDIDAC_MAX_CODE. * * \param context -* The pointer to the CSDIDAC middleware context +* The pointer to the CSDIDAC middleware context * structure \ref cy_stc_csdidac_context_t. * * \return * The function returns the status of its operation. * * CY_CSDIDAC_SUCCESS - The operation is performed successfully. -* * CY_CSDIDAC_BAD_PARAM - The input pointer is NULL or an invalid parameter +* * CY_CSDIDAC_BAD_PARAM - The input pointer is NULL or an invalid parameter * is passed. * *******************************************************************************/ @@ -916,7 +916,7 @@ static void Cy_CSDIDAC_ConnectChannelB( * Disconnects the output channel A pin, if it is configured. * * \param context -* The pointer to the CSDIDAC middleware context +* The pointer to the CSDIDAC middleware context * structure \ref cy_stc_csdidac_context_t. * *******************************************************************************/ @@ -945,7 +945,7 @@ static void Cy_CSDIDAC_DisconnectChannelA(cy_stc_csdidac_context_t * context) * Disconnects the output channel B pin, if it is configured. * * \param context -* The pointer to the CSDIDAC middleware context +* The pointer to the CSDIDAC middleware context * structure \ref cy_stc_csdidac_context_t. * *******************************************************************************/ @@ -981,13 +981,13 @@ static void Cy_CSDIDAC_DisconnectChannelB(cy_stc_csdidac_context_t * context) * The channel to disconnect. * * \param context -* The pointer to the CSDIDAC middleware context +* The pointer to the CSDIDAC middleware context * structure \ref cy_stc_csdidac_context_t. * * \return * The function returns the status of its operation. * * CY_CSDIDAC_SUCCESS - The operation is performed successfully. -* * CY_CSDIDAC_BAD_PARAM - The input pointer is NULL or an invalid parameter +* * CY_CSDIDAC_BAD_PARAM - The input pointer is NULL or an invalid parameter * is passed. * *******************************************************************************/ @@ -1014,7 +1014,7 @@ cy_en_csdidac_status_t Cy_CSDIDAC_OutputDisable( return (retVal); } -#endif /* CY_IP_MXCSDV2 */ +#endif /* (defined(CY_IP_MXCSDV2) || defined(CY_IP_M0S8CSDV2)) */ /* [] END OF FILE */ diff --git a/cy_csdidac.h b/cy_csdidac.h index c8d3371..62d8db1 100644 --- a/cy_csdidac.h +++ b/cy_csdidac.h @@ -1,25 +1,25 @@ /***************************************************************************//** * \file cy_csdidac.h -* \version 2.0 +* \version 2.10 * * \brief -* This file provides the function prototypes and constants specific +* This file provides the function prototypes and constants specific * to the CSDIDAC middleware. * ******************************************************************************** * \copyright -* Copyright 2019, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2019-2020, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. *******************************************************************************/ /** -* \mainpage Cypress CSDIDAC Middleware Library +* \mainpage CSDIDAC Middleware Library * -* The CSDIDAC middleware is the Cypress IDAC solution that uses the +* The CSDIDAC middleware is the IDAC solution that uses the * CSD HW block. Any GPIO that can be connected to AMUX-A/B (refer to the * particular device datasheet for information) can be an CSDIDAC output -* under software control. +* under software control. * The CSD HW block is mainly used to implement the touch sense applications and * proximity sensors (refer to the * @@ -30,15 +30,15 @@ * Features: * * A two-channel IDAC with the 7-bit resolution. * * The IDAC A and IDAC B channels can be enabled/disabled independently. -* * The IDAC A and IDAC B channels can be configured with sourcing/sinking +* * The IDAC A and IDAC B channels can be configured with sourcing/sinking * current independently. -* * The IDAC A and IDAC B channels can be joined to increase a maximum output +* * The IDAC A and IDAC B channels can be joined to increase a maximum output * current. -* * The IDAC A and IDAC B channels can be enabled/disabled simultaneously +* * The IDAC A and IDAC B channels can be enabled/disabled simultaneously * by using the CY_CSDIDAC_AB option. -* * The 0 to 609.6 uA (609600 nA) current range is available for each IDAC +* * The 0 to 609.6 uA (609600 nA) current range is available for each IDAC * channel. -* * Each IDAC can use independently one of the six available LSB depending +* * Each IDAC can use independently one of the six available LSB depending * on a desired output current: * * @@ -91,28 +91,28 @@ * \ref group_csdidac_changelog also describes the impact of changes to * your code. * -* The CSD HW block enables the multiple sensing capabilities on PSoC devices -* including the self-cap and mutual-cap capacitive touch sensing solution, -* 10-bit ADC, IDAC, and Comparator. The CSD driver is a low-level -* peripheral driver, a wrapper to manage access to the CSD HW block. -* Any middleware access to the CSD HW block is through the CSD Driver. -* -* The CSD HW block can support only one function at a time. However, all -* supported functionality (like CapSense, CSDADC, CSDIDAC, etc.) can be -* time-multiplexed in a design. I.e. you can save the existing state -* of the CapSense middleware, restore the state of the CSDIDAC middleware, +* The CSD HW block enables the multiple sensing capabilities on PSoC devices +* including the self-cap and mutual-cap capacitive touch sensing solution, +* 10-bit ADC, IDAC, and Comparator. The CSD driver is a low-level +* peripheral driver, a wrapper to manage access to the CSD HW block. +* Any middleware access to the CSD HW block is through the CSD Driver. +* +* The CSD HW block can support only one function at a time. However, all +* supported functionality (like CapSense, CSDADC, CSDIDAC, etc.) can be +* time-multiplexed in a design. I.e. you can save the existing state +* of the CapSense middleware, restore the state of the CSDIDAC middleware, * perform DAC operations, and then switch back to the CapSense functionality. -* For more details and code examples, refer to the description of the +* For more details and code examples, refer to the description of the * Cy_CSDIDAC_Save() and Cy_CSDIDAC_Restore() functions. -* +* * \image html capsense_solution.png "CapSense Solution" width=800px * \image latex capsense_solution.png -* -* This section describes only the CSDIDAC middleware. Refer to the corresponding +* +* This section describes only the CSDIDAC middleware. Refer to the corresponding * sections for documentation of other middleware supported by the CSD HW block. * The CSDIDAC library is designed to be used with the CSD driver. -* The application program does not need to interact with the CSD driver -* and/or other drivers such as GPIO or SysClk directly. All of that is +* The application program does not need to interact with the CSD driver +* and/or other drivers such as GPIO or SysClk directly. All of that is * configured and managed by the middleware. * * The Cy_CSDIDAC API is described in the following sections: @@ -125,13 +125,13 @@ * \section section_csdidac_quick_start Quick Start Guide ******************************************************************************** * -* Cypress CSDIDAC middleware can be used in various Development Environments +* The CSDIDAC middleware can be used in various Development Environments * such as ModusToolbox, MBED, etc. Refer to the \ref section_csdidac_toolchain. * The quickest way to get started is using the Code Examples. -* Cypress Semiconductor continuously extends its portfolio of the code examples +* The continually expanding portfolio of the code examples is available * at the Cypress Semiconductor website -* and at the -* Cypress Semiconductor GitHub. +* and on +* GitHub. * * This quick start guide assumes that the environment is configured to use the * PSoC 6 Peripheral Driver Library(psoc6pdl) for development and the @@ -145,7 +145,7 @@ * \note * Put the CSDIDAC name to the Alias field of the CSD resource if the * Device Configurator is used. -* +* * 2. Include cy_csdidac.h to get access to all CSDIDAC API and cy_pdl.h to get * access to API of peripheral drivers according to the example below: * \snippet csdidac/snippet/main.c snippet_required_includes @@ -169,9 +169,9 @@ * with the following parameters: * 1. Device VDDA: 3.3V. * 2. Device Peri Clock frequency: 48MHz. -* 3. IDAC A is sourcing current of 50 uA to GPIO pin P6[2]. -* 4. IDAC B is sinking current of 0.5uA from GPIO pin P6[3]. -* +* 3. IDAC A is sourcing current of 50 uA to GPIO pin P0[4]. +* 4. IDAC B is sinking current of 0.5uA from GPIO pin P0[5]. +* * There are two methods for the CSDIDAC Middleware configuration: * 1. \ref subsection_csdidac_mtb_configuring * 2. \ref subsection_csdidac_manual_configuring @@ -185,7 +185,7 @@ * Device Configurator Tool provides the user interface to set up and * automatically generate the initialization code (including analog routing) and * configuration structures. -* +* * Manual implementation of the initialization code (including analog routing) * and configuration structures is recommended for expert Users only. This will * include the code for the following settings which in case of the @@ -238,7 +238,7 @@ * * The Peripheral Clock Divider assignment and analog routing are parts of * the init_cycfg_all() routine. Place the call of the init_cycfg_all() function * before using any CSDIDAC API functions to ensure initialization of all -* external resources required for the CSDIDAC operation. +* external resources required for the CSDIDAC operation. * Refer to the main() routine code snippet in * \ref section_csdidac_quick_start * * The CSDIDAC configuration structure declaration in the @@ -268,7 +268,7 @@ * is used. * Otherwise, ensure the CSDIDAC Middleware is included in your project. * 2. Define the CSD HW block base address. See the code example below: -* \snippet csdidac/snippet/main.c snippet_csd_hw_definition +* \snippet csdidac/snippet/main.c snippet_csd_hw_definition * 3. Declare the CSD HW driver context structure and initialize the * lockKey field with the CY_CSD_NONE_KEY value. See the code example below: * \snippet csdidac/snippet/main.c snippet_csd_context_declaration @@ -282,16 +282,26 @@ * \snippet csdidac/snippet/main.c snippet_Cy_CSDIDAC_Clock_Assignment * 6. Set the configuration of the HSIOM_AMUX_SPLIT_CTL switches to route signal * from CSD HW block to the pins configured as the CSDIDAC output channels. -* The AMUX_SPLIT_CTL[4] switches are closed to connect -* port P6 with the CSD HW block. Refer to the +* +* The AMUX bus has segments that are separated with the HSIOM_AMUX_SPLIT_CTL switches. +* The code below closes the AMUX_SPLIT_CTL switches, which route the IDAC output +* signal from the CSD block to the pin. In this example, IDAC output channels +* are assigned to the P0[4] and P[5] pins. The AMUX_SPLIT_CTL[5] and AMUX_SPLIT_CTL[6] +* switches must be closed in the PSoC6 device. The P0[4] and P[5] pins in the +* PSoC4 device belong to the AMUX bus segment, which is connected to the CSD block +* directly. In this case, the AMUX_SPLIT_CTL switches are not closed. +* Refer to the * Technical Reference Manual * (TRM) for more information regarding the analog interconnection. * See the code example below and refer to the main() routine code snippet in * \ref section_csdidac_quick_start * \snippet csdidac/snippet/main.c snippet_Cy_CSDIDAC_Amux_Configuration * \note -* Some CSDIDAC configurations are restricted. The CSD personality has a -* mechanism to prevent writing an invalid configuration. If CSDIDAC is manually +* If you use a KIT, check on the schematics, if pins P0[4] and P0[5] are +* free. If not, use some other pins and update the AMUX_SPLIT_CTL registers. +* \note +* Some CSDIDAC configurations are restricted. The CSD personality has a +* mechanism to prevent writing an invalid configuration. If CSDIDAC is manually * created, avoid the following combinations: * * both IDAC channels are disabled * * one IDAC channel is disabled and another channel is joined to it @@ -311,24 +321,25 @@ ******************************************************************************** * \subsection group_csdidac_low_power_design Low power design ******************************************************************************** -* The CSD HW block and CSDIDAC middleware can operate in CPU active and -* CPU sleep power modes. It is also +* The CSD HW block and CSDIDAC middleware can operate in CPU active and +* CPU sleep power modes. It is also * possible to switch between low power and ultra low power system modes. -* In System Deep Sleep and Hibernate power modes, the CSD HW block is powered off and +* In System Deep Sleep and Hibernate power modes, the CSD HW block is powered off and * CSDIDAC operations are not performed. Before entering CPU / System Deep Sleep, -* disable CSDIDAC output current generation. If output +* disable CSDIDAC output current generation. If output * currents are not disabled, a CPU Deep Sleep transition will fail. -* When the device wakes up from CPU / System Deep Sleep, the CSD HW block resumes operation -* without the need for re-initialization and the CSDIDAC operations can be -* continued with configuration that was set before a CPU / System Deep Sleep transition. -* When the device wakes up from Hibernate power mode, the CSD HW block +* When the device wakes up from CPU / System Deep Sleep, the CSD HW block resumes operation +* without the need for re-initialization and the CSDIDAC operations can be +* continued with configuration that was set before a CPU / System Deep Sleep transition. +* When the device wakes up from Hibernate power mode, the CSD HW block * does not retain the configuration and CSDIDAC requires re-initialization. * * \note -* 1. Analog start up time for the CSD HW block is 25 us. Initiate -* any kind of operation only after 25 us from System Deep Sleep / Hibernate exit. +* 1. Analog start up time for the CSD HW block is 25 us for PSoC6 devices and +* 10 us for PSoC4 devices. Initiate any kind of operation only after 25 us +* for PSoC6 devices and 10 us for PSoC4 devices from System Deep Sleep / Hibernate exit. * -* 2. Entering CPU Deep Sleep mode does not mean the device enters +* 2. Entering CPU Deep Sleep mode does not mean the device enters * System Deep Sleep. For more detail about switching to System Deep Sleep, * refer to the device TRM. * @@ -340,18 +351,18 @@ * The CSD HW block can operate in CPU sleep mode. The user can start CSDIDAC * and move CPU into sleep mode to reduce power consumption. After wake-up CPU * from sleep, the user can perform other operations, e.g. disable IDACs. -* Then, the user configures the CSDIDAC middleware as described in -* \ref section_csdidac_configuration, and updates the main() routine with -* the following code: +* Then, the user configures the CSDIDAC middleware as described in +* \ref section_csdidac_configuration, and updates the main() routine with +* the following code: * \snippet csdidac/snippet/main.c snippet_Cy_CSDIDAC_Sleep * * Deep Sleep mode
* To use the CSDIDAC middleware in CPU / System Deep Sleep mode, the user configures -* a wake-up source (e.g. a pin, WDT, LPC or another entities, that are active -* in CPU / System Deep Sleep mode), configures the CSDIDAC middleware as described in -* \ref section_csdidac_configuration, configures CSDIDAC and other drivers' and -* middleware's (if presented) Deep Sleep Callback structures, registers -* callbacks, and updates the main() routine with the following code: +* a wake-up source (e.g. a pin, WDT, LPC or another entities, that are active +* in CPU / System Deep Sleep mode), configures the CSDIDAC middleware as described in +* \ref section_csdidac_configuration, configures CSDIDAC and other drivers' and +* middleware's (if present) Deep Sleep Callback structures, registers +* callbacks, and updates the main() routine with the following code: * \snippet csdidac/snippet/main.c snippet_CSDIDAC_DeepSleep_structures * \snippet csdidac/snippet/main.c snippet_Cy_CSDIDAC_DeepSleep * @@ -366,9 +377,9 @@ * \section section_csdidac_toolchain Supported Software and Tools ******************************************************************************** * -* This version of the CSDIDAC Middleware was validated for compatibility +* This version of the CSDIDAC Middleware was validated for compatibility * with the following Software and Tools: -* +* *
* * @@ -376,19 +387,27 @@ * * * -* +* * * * -* +* * * -* +* +* +* +* +* * * * +* +* +* +* * -* +* * * * @@ -403,8 +422,8 @@ * * * -* -* +* +* * * * @@ -445,7 +464,7 @@ * * * -* * * * -* * * @@ -471,31 +490,40 @@ *
Software and Tools
ModusToolbox Software Environment2.02.1
- ModusToolbox Device Configurator2.02.1
- ModusToolbox CSD Personality in Device Configurator- ModusToolbox CSD Personality for PSoC4 devices in Device Configurator1.0
- ModusToolbox CSD Personality for PSoC6 devices in Device Configurator2.0
PSoC4 Peripheral Driver Library (PDL)1.0.0
PSoC6 Peripheral Driver Library (PDL)1.2.01.5.0
GCC Compiler6.11
MBED OS5.13.1MBED OS (only for PSoC6)5.15.1
FreeRTOS
11.4ADo not perform a conversion between the pointer to an object +* Do not perform a conversion between the pointer to an object * and an integer type.Such a conversion is performed with CSDIDAC context * in the DeepSleepCallback() function. @@ -455,8 +474,8 @@ * 1.2 R Constant: De-reference of the NULL pointer. These violations are reported as a result of using -* offset macros of the CSD Driver with corresponding documented +* These violations are reported as a result of using +* offset macros of the CSD Driver with corresponding documented * violation 20.6. Refer to the CSD Driver API Reference Guide.
* * +* +* +* +* +* +* +* +* +* * -* * * * -* * * * -* * * * -* * * * -* * * @@ -510,70 +538,112 @@ * \section group_csdidac_more_information More Information ******************************************************************************** * +* Important information about the CapSense-technology overview, appropriate +* device for the design, CapSense system and sensor design guidelines, +* different interfaces and tuning guidelines necessary for a successful design +* of a CapSense system is available in the Getting Started with CapSense +* document and the product-specific CapSense design guide. It is highly +* recommended to start with these documents. They can be found at www.cypress.com. +* * For more information, refer to the following documents: * -* * -* ModusToolbox Software Environment, Quick Start Guide, Documentation, -* and Videos +* * CapSense and CSDIDAC Overview: * -* * CSDIDAC Middleware -* Code Example for MBED OS +* * CSDIDAC Middleware +* Code Example for MBED OS * -* * CSDIDAC Middleware -* Code Examples at GITHUB +* * +* CapSense Middleware API Reference Guide * -* * ModusToolbox -* Device Configurator Tool Guide +* * ModusToolbox Overview: * -* * -* CapSense Middleware API Reference Guide +* * +* ModusToolbox Software Environment, Quick Start Guide, Documentation, +* and Videos * -* * -* CSDADC Middleware API Reference Guide +* * ModusToolbox +* Device Configurator Tool Guide * -* * -* PDL API Reference +* * Kits: * -* * -* PSoC 6 Technical Reference Manual +* * +* CY8CKIT-145-40XX PSoC 4000S CapSense Prototyping Kit * -* * -* PSoC 63 with BLE Datasheet Programmable System-on-Chip datasheet +* * +* CY8CKIT-149 PSoC 4100S Plus Prototyping Kit * -* * Cypress Semiconductor +* * +* CY8CKIT-041-40XX PSoC 4 S-Series Pioneer Kit +* +* * +* CY8CKIT-041-41XX PSoC 4100S CapSense Pioneer Kit +* +* * +* CY8CKIT-062-BLE PSoC 6 BLE Pioneer Kit +* +* * +* CY8CKIT-062-WiFi-BT PSoC 6 WiFi-BT Pioneer Kit +* +* * +* CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Prototyping Kit +* +* * General Information: +* +* * +* PSoC 4 PDL API Reference +* +* * +* PSoC 6 PDL API Reference +* +* * +* PSoC 6 Technical Reference Manual +* +* * +* PSoC 63 with BLE Datasheet Programmable System-on-Chip datasheet +* +* * +* PSoC 4000S Family: PSoC 4 Architecture Technical Reference Manual (TRM) +* +* * +* PSoC 4100S and PSoC 4100S Plus: PSoC 4 Architecture Technical Reference Manual (TRM) +* +* * +* Cypress Semiconductor GitHub +* +* * Cypress Semiconductor * * \note -* The links to another software component’s documentation (middleware and PDL) -* point to GitHub to the latest available version of the software. -* To get documentation of the specified version, download from GitHub and unzip +* The links to another software component's documentation (middleware and PDL) +* point to GitHub to the latest available version of the software. +* To get documentation of the specified version, download from GitHub and unzip * the component archive. The documentation is available in the docs folder. * * \defgroup group_csdidac_macros Macros * \brief -* This section describes the CSDIDAC macros. These macros can be used for +* This section describes the CSDIDAC macros. These macros can be used for * checking a maximum IDAC code and a maximum IDAC output current. -* For detailed information about macros, see each macro description. +* For detailed information about macros, see each macro description. * * \defgroup group_csdidac_enums Enumerated types * \brief -* Describes the enumeration types defined by the CSDIDAC. These enumerations +* Describes the enumeration types defined by the CSDIDAC. These enumerations * can be used for checking CSDIDAC functions' return status, -* for defining a CSDIDAC LSB and polarity, and for choosing IDAC for an +* for defining a CSDIDAC LSB and polarity, and for choosing IDAC for an * operation and defining its states. For detailed information about -* enumerations, see each enumeration description. +* enumerations, see each enumeration description. * * \defgroup group_csdidac_data_structures Data Structures * \brief -* Describes the data structures defined by the CSDIDAC. The CSDIDAC -* middleware use structures for output channel pins, -* middleware configuration, and context. The pin structure is included -* in the configuration structure and both of them can be defined by the -* user with the CSD personality in the Device Configurator or manually +* Describes the data structures defined by the CSDIDAC. The CSDIDAC +* middleware use structures for output channel pins, +* middleware configuration, and context. The pin structure is included +* in the configuration structure and both of them can be defined by the +* user with the CSD personality in the Device Configurator or manually * if the user doesn't use ModusToolbox. -* The context structure contains a copy of the configuration structure -* and current CSDIDAC middleware state data. The context -* structure should be allocated by the user and be passed to all -* CSDIDAC middleware functions. CSDIDAC middleware structure sizes +* The context structure contains a copy of the configuration structure +* and current CSDIDAC middleware state data. The context +* structure should be allocated by the user and be passed to all +* CSDIDAC middleware functions. CSDIDAC middleware structure sizes * are shown in the table below: * *
VersionChangesReason for Change
2.10Added the support of PSoC 4 CapSense Forth Generation devicesDevices support
Minor documentation updateDocumentation cleanup
2.0The joining two IDAC channels option is added to increase +* The joining two IDAC channels option is added to increase * the maximum CSDIDAC output current Feature enchancement
The cy_stc_csdidac_config_t structure is changed: the periClk field -* replaced with cpuClk, busOnlyA and busOnlyB fields replaced with +* The cy_stc_csdidac_config_t structure is changed: the periClk field +* replaced with cpuClk, busOnlyA and busOnlyB fields replaced with * configA and configB fields respectively, the field order is changed. * The \ref cy_en_csdidac_channel_config_t enumeration type is added.User experience improvement
The \ref CY_CSDIDAC_HW_FAILURE and +* The \ref CY_CSDIDAC_HW_FAILURE and * the \ref CY_CSDIDAC_BAD_CONFIGURATION return status cases are added * to the \ref cy_en_csdidac_status_t enumeration typeUser experience improvement
The \ref CY_CSDIDAC_AB choosing case for both IDACs is added +* The \ref CY_CSDIDAC_AB choosing case for both IDACs is added * to the \ref cy_en_csdidac_choice_t enumeration typeFeature enchancement
The CSDIDAC MW sources are enclosed with the conditional compilation to +* The CSDIDAC MW sources are enclosed with the conditional compilation to * ensure a successful compilation for non-CapSense-capable devicesCompilation for non-CapSense-capable devices
@@ -606,7 +676,7 @@ #include "cy_device_headers.h" #include "cy_csd.h" -#if defined(CY_IP_MXCSDV2) +#if (defined(CY_IP_MXCSDV2) || defined(CY_IP_M0S8CSDV2)) /* The C binding of definitions to build with the C++ compiler. */ #ifdef __cplusplus @@ -622,21 +692,24 @@ extern "C" { #define CY_CSDIDAC_MW_VERSION_MAJOR (2) /** Middleware minor version */ -#define CY_CSDIDAC_MW_VERSION_MINOR (0) +#define CY_CSDIDAC_MW_VERSION_MINOR (10) + +/** Middleware version */ +#define CY_CSDIDAC_MW_VERSION (210) /** CSDIDAC ID. The user can identify the CSDIDAC middleware error codes by this macro. */ #define CY_CSDIDAC_ID (CY_PDL_DRV_ID(0x44u)) -/** -* The CSDIDAC max code value. The user provides the code -* parameter for the Cy_CSDIDAC_OutputEnableExt() function +/** +* The CSDIDAC max code value. The user provides the code +* parameter for the Cy_CSDIDAC_OutputEnableExt() function * in the range from 0u to CY_CSDIDAC_MAX_CODE. */ #define CY_CSDIDAC_MAX_CODE (127u) -/** -* The CSDIDAC max output current value. The user provides -* the value of the current parameter for the Cy_CSDIDAC_OutputEnable() +/** +* The CSDIDAC max output current value. The user provides +* the value of the current parameter for the Cy_CSDIDAC_OutputEnable() * function in range from 0 to +/-(CY_CSDIDAC_MAX_CURRENT_NA). */ #define CY_CSDIDAC_MAX_CURRENT_NA (609600uL) @@ -654,28 +727,28 @@ extern "C" { /** CSDIDAC return enumeration type */ typedef enum { - CY_CSDIDAC_SUCCESS = (0u), + CY_CSDIDAC_SUCCESS = (0u), /**< The operation executed successfully. */ CY_CSDIDAC_BAD_PARAM = (CY_CSDIDAC_ID + (uint32_t)CY_PDL_STATUS_ERROR + 1u), - /**< - * An input parameter is invalid. + /**< + * An input parameter is invalid. * The user checks whether all * the input parameters are valid. */ CY_CSDIDAC_HW_BUSY = (CY_CSDIDAC_ID + (uint32_t)CY_PDL_STATUS_ERROR + 2u), - /**< - * The CSD HW block is busy, - * i.e. any of current channel (A or B) - * is enabled. + /**< + * The CSD HW block is busy, + * i.e. any of current channel (A or B) + * is enabled. */ CY_CSDIDAC_HW_LOCKED = (CY_CSDIDAC_ID + (uint32_t)CY_PDL_STATUS_ERROR + 3u), - /**< - * The CSD HW block is acquired and - * locked by other middleware - * or application. The CSDIDAC - * middleware waits for + /**< + * The CSD HW block is acquired and + * locked by other middleware + * or application. The CSDIDAC + * middleware waits for * the CSD HW block release - * to acquire it for use. + * to acquire it for use. */ CY_CSDIDAC_HW_FAILURE = (CY_CSDIDAC_ID + (uint32_t)CY_PDL_STATUS_ERROR + 4u), /**< @@ -706,14 +779,14 @@ typedef enum } cy_en_csdidac_status_t; /** -* The CSDIDAC output current LSB enumeration type. The user can choose +* The CSDIDAC output current LSB enumeration type. The user can choose * LSB when the Cy_CSDIDAC_OutputEnableExt() function is called and -* can check which LSB was chosen by the Cy_CSDIDAC_OutputEnable() +* can check which LSB was chosen by the Cy_CSDIDAC_OutputEnable() * function in the cy_stc_csdidac_context_t structure. */ typedef enum -{ +{ CY_CSDIDAC_LSB_37_IDX = 0u, /**< Index for 37.5 nA LSB */ CY_CSDIDAC_LSB_75_IDX = 1u, /**< Index for 75.0 nA LSB */ CY_CSDIDAC_LSB_300_IDX = 2u, /**< Index for 0.3 uA LSB */ @@ -723,9 +796,9 @@ typedef enum }cy_en_csdidac_lsb_t; /** -* The CSDIDAC polarity enumeration type. The user can choose the polarity -* when the Cy_CSDIDAC_OutputEnableExt() function is called and can -* check which polarity was chosen by the Cy_CSDIDAC_OutputEnable() +* The CSDIDAC polarity enumeration type. The user can choose the polarity +* when the Cy_CSDIDAC_OutputEnableExt() function is called and can +* check which polarity was chosen by the Cy_CSDIDAC_OutputEnable() * function in the cy_stc_csdidac_context_t structure. */ typedef enum @@ -735,8 +808,8 @@ typedef enum }cy_en_csdidac_polarity_t; /** -* The CSDIDAC channel enabling enumeration type. The user can check which -* channel (A or B or both) is currently enabled +* The CSDIDAC channel enabling enumeration type. The user can check which +* channel (A or B or both) is currently enabled * in the cy_stc_csdidac_context_t structure. */ typedef enum @@ -746,8 +819,8 @@ typedef enum }cy_en_csdidac_state_t; /** -* The CSDIDAC choosing enumeration type. The user can choose channel A or B -* to operate with the Cy_CSDIDAC_OutputEnableExt(), Cy_CSDIDAC_OutputDisable(), +* The CSDIDAC choosing enumeration type. The user can choose channel A or B +* to operate with the Cy_CSDIDAC_OutputEnableExt(), Cy_CSDIDAC_OutputDisable(), * or Cy_CSDIDAC_OutputEnable() functions. */ typedef enum @@ -758,7 +831,7 @@ typedef enum } cy_en_csdidac_choice_t; /** -* The CSDIDAC channel configuration defines either disabled or enabled with +* The CSDIDAC channel configuration defines either disabled or enabled with * specific routing. */ typedef enum @@ -1077,7 +1150,7 @@ __STATIC_INLINE bool Cy_CSDIDAC_IsIdacConfigValid(const cy_stc_csdidac_config_t } #endif /* __cplusplus */ -#endif /* CY_IP_MXCSDV2 */ +#endif /* (defined(CY_IP_MXCSDV2) || defined(CY_IP_M0S8CSDV2)) */ #endif /* CY_CSDIDAC_H */ diff --git a/docs/csdidac_api_reference_manual/html/IFXCYP_one-line.png b/docs/csdidac_api_reference_manual/html/IFXCYP_one-line.png new file mode 100644 index 0000000..c6d2b8e Binary files /dev/null and b/docs/csdidac_api_reference_manual/html/IFXCYP_one-line.png differ diff --git a/docs/csdidac_api_reference_manual/html/annotated.html b/docs/csdidac_api_reference_manual/html/annotated.html index 27d95a2..139b346 100644 --- a/docs/csdidac_api_reference_manual/html/annotated.html +++ b/docs/csdidac_api_reference_manual/html/annotated.html @@ -6,7 +6,7 @@ -Cypress CSDIDAC Middleware Library 2.0: Data Structures +CSDIDAC Middleware Library 2.10: Data Structures @@ -28,9 +28,9 @@
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Cypress CSDIDAC Middleware Library 2.0
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Cypress CSDIDAC Middleware Library 2.0
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Cypress CSDIDAC Middleware Library 2.0
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Cypress CSDIDAC Middleware Library 2.0
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Cypress CSDIDAC Middleware Library 2.0
+
CSDIDAC Middleware Library 2.10
- + @@ -347,7 +347,7 @@

  • - Generated for Cypress CSDIDAC Middleware Library 2.0 by Cypress Semiconductor Corporation. + Generated for CSDIDAC Middleware Library 2.10 by Cypress Semiconductor Corporation. All rights reserved.
diff --git a/docs/csdidac_api_reference_manual/html/group__group__csdidac__functions.html b/docs/csdidac_api_reference_manual/html/group__group__csdidac__functions.html index e671035..702a7ca 100644 --- a/docs/csdidac_api_reference_manual/html/group__group__csdidac__functions.html +++ b/docs/csdidac_api_reference_manual/html/group__group__csdidac__functions.html @@ -6,7 +6,7 @@ -Cypress CSDIDAC Middleware Library 2.0: Functions +CSDIDAC Middleware Library 2.10: Functions @@ -28,9 +28,9 @@

-
Cypress CSDIDAC Middleware Library 2.0
+
CSDIDAC Middleware Library 2.10
- + @@ -585,7 +585,7 @@

diff --git a/docs/csdidac_api_reference_manual/html/group__group__csdidac__macros.html b/docs/csdidac_api_reference_manual/html/group__group__csdidac__macros.html index aec9cff..f4534be 100644 --- a/docs/csdidac_api_reference_manual/html/group__group__csdidac__macros.html +++ b/docs/csdidac_api_reference_manual/html/group__group__csdidac__macros.html @@ -6,7 +6,7 @@ -Cypress CSDIDAC Middleware Library 2.0: Macros +CSDIDAC Middleware Library 2.10: Macros @@ -28,9 +28,9 @@

-
Cypress CSDIDAC Middleware Library 2.0
+
CSDIDAC Middleware Library 2.10
- + @@ -97,9 +97,13 @@ +#define  + + + @@ -168,7 +172,7 @@

diff --git a/docs/csdidac_api_reference_manual/html/group__group__csdidac__macros.js b/docs/csdidac_api_reference_manual/html/group__group__csdidac__macros.js index bdc1e54..c306c43 100644 --- a/docs/csdidac_api_reference_manual/html/group__group__csdidac__macros.js +++ b/docs/csdidac_api_reference_manual/html/group__group__csdidac__macros.js @@ -2,6 +2,7 @@ var group__group__csdidac__macros = [ [ "CY_CSDIDAC_MW_VERSION_MAJOR", "group__group__csdidac__macros.html#ga9375f31416f3ad518a47e53a52a0bd36", null ], [ "CY_CSDIDAC_MW_VERSION_MINOR", "group__group__csdidac__macros.html#ga9e48ea89b7352aeb1d4c9de2af0df9d2", null ], + [ "CY_CSDIDAC_MW_VERSION", "group__group__csdidac__macros.html#gaa13c574206a03b76ceec914dd444307f", null ], [ "CY_CSDIDAC_ID", "group__group__csdidac__macros.html#ga35cda9dfe000e55322b274fd4de3feaa", null ], [ "CY_CSDIDAC_MAX_CODE", "group__group__csdidac__macros.html#ga2d7dda94153fedc16256295b59e962cd", null ], [ "CY_CSDIDAC_MAX_CURRENT_NA", "group__group__csdidac__macros.html#ga5975f4c5e4d22e842a4cd00128322e8b", null ] diff --git a/docs/csdidac_api_reference_manual/html/index.html b/docs/csdidac_api_reference_manual/html/index.html index 2896625..82c36c6 100644 --- a/docs/csdidac_api_reference_manual/html/index.html +++ b/docs/csdidac_api_reference_manual/html/index.html @@ -6,7 +6,7 @@ -Cypress CSDIDAC Middleware Library 2.0: Cypress CSDIDAC Middleware Library +CSDIDAC Middleware Library 2.10: CSDIDAC Middleware Library @@ -28,9 +28,9 @@

-
Cypress CSDIDAC Middleware Library 2.0
+
CSDIDAC Middleware Library 2.10
 Middleware major version.
 
-#define CY_CSDIDAC_MW_VERSION_MINOR   (0)
CY_CSDIDAC_MW_VERSION_MINOR   (10)
 Middleware minor version.
 
+#define CY_CSDIDAC_MW_VERSION   (210)
 Middleware version.
 
#define CY_CSDIDAC_ID   (CY_PDL_DRV_ID(0x44u))
 CSDIDAC ID. More...
 
- + @@ -81,10 +81,10 @@
-
Cypress CSDIDAC Middleware Library
+
CSDIDAC Middleware Library
-

The CSDIDAC middleware is the Cypress IDAC solution that uses the CSD HW block. Any GPIO that can be connected to AMUX-A/B (refer to the particular device datasheet for information) can be an CSDIDAC output under software control. The CSD HW block is mainly used to implement the touch sense applications and proximity sensors (refer to the CapSense Middleware API Reference Guide), but can also be used to implement the IDAC, which is especially useful for the devices that do not include another hardware option to implement IDAC.

+

The CSDIDAC middleware is the IDAC solution that uses the CSD HW block. Any GPIO that can be connected to AMUX-A/B (refer to the particular device datasheet for information) can be an CSDIDAC output under software control. The CSD HW block is mainly used to implement the touch sense applications and proximity sensors (refer to the CapSense Middleware API Reference Guide), but can also be used to implement the IDAC, which is especially useful for the devices that do not include another hardware option to implement IDAC.

Features:

  • A two-channel IDAC with the 7-bit resolution.
  • The IDAC A and IDAC B channels can be enabled/disabled independently.
    • @@ -130,7 +130,7 @@

Quick Start Guide

-

Cypress CSDIDAC middleware can be used in various Development Environments such as ModusToolbox, MBED, etc. Refer to the Supported Software and Tools. The quickest way to get started is using the Code Examples. Cypress Semiconductor continuously extends its portfolio of the code examples at the Cypress Semiconductor website and at the Cypress Semiconductor GitHub.

+

The CSDIDAC middleware can be used in various Development Environments such as ModusToolbox, MBED, etc. Refer to the Supported Software and Tools. The quickest way to get started is using the Code Examples. The continually expanding portfolio of the code examples is available at the Cypress Semiconductor website and on GitHub.

This quick start guide assumes that the environment is configured to use the PSoC 6 Peripheral Driver Library(psoc6pdl) for development and the PSoC 6 Peripheral Driver Library(psoc6pdl) is included in the project.

The steps required to set up the CSDIDAC and get the desired current:

    @@ -139,7 +139,7 @@

  1. Include cy_csdidac.h to get access to all CSDIDAC API and cy_pdl.h to get access to API of peripheral drivers according to the example below:
    #include "cy_pdl.h"
    #include "cy_csdidac.h"
  2. If you use the MBED OS, include the cycfg.h file to get access to the System Configuration:
    #include "cycfg.h"
  3. Declare the 'cy_csdidac_context' variable as per example below:
    /* CSDIDAC context declaration */
    cy_stc_csdidac_context_t csdidac_context;
    4. -
  4. Update the main() routine with the following code:
    /* UNCOMMENT THIS CODE if you use the MBED OS: */
    //init_cycfg_clocks();
    //init_cycfg_routing();
    //init_cycfg_peripherals();
    /* UNCOMMENT THIS CODE if you implement the initialization code manually
    * to assign the Peripheral Clock Divider to the CSD HW block
    * and to configure the divider value.
    */
    //Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0u);
    //Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0u);
    //Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0u, 0u);
    //Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0u);
    /* UNCOMMENT THIS CODE if you implement the initialization code manually to
    * set configuration of the HSIOM_AMUX_SPLIT_CTL switches.
    */
    //#if(1u == CY_IP_MXS40IOSS_VERSION)
    // HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
    // HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
    // HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
    // HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
    //#elif(2u == CY_IP_MXS40IOSS_VERSION)
    // HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
    // HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
    // HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
    // HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
    //#else
    // #error Not supported device
    //#endif
    /* Captures the CSD HW block and initializes it to the default state. */
    Cy_CSDIDAC_Init(&CSDIDAC_csdidac_config, &csdidac_context);
    /* Generates a sourcing current of 50 uA (50000 nA) on the IDAC A output. */
    Cy_CSDIDAC_OutputEnable(CY_CSDIDAC_A, 50000, &csdidac_context);
    /* Generates a sinking current of 0.5uA (-500 nA) on the IDAC B output. */
    Cy_CSDIDAC_OutputEnable(CY_CSDIDAC_B, -500, &csdidac_context);
    5. +
  5. Update the main() routine with the following code:
    /* UNCOMMENT THIS CODE if you use the MBED OS: */
    //init_cycfg_clocks();
    //init_cycfg_routing();
    //init_cycfg_peripherals();
    /* UNCOMMENT THIS CODE if you implement the initialization code manually
    * to assign the Peripheral Clock Divider to the CSD HW block
    * and to configure the divider value.
    */
    //#if defined(CY_IP_MXCSDV2)
    // Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0u);
    // Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0u);
    // Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0u, 0u);
    // Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0u);
    //#elif defined(CY_IP_M0S8CSDV2)
    // Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0u);
    // Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_16_BIT, 0u);
    // Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0u, 0u);
    // Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0u);
    //#else
    // #error Not supported device
    //#endif /* CY_IP_MXCSDV2 */
    /* UNCOMMENT THIS CODE if you implement the initialization code manually to
    * set configuration of the HSIOM_AMUX_SPLIT_CTL switches.
    * The AMUX bus has segments that are separated with the HSIOM_AMUX_SPLIT_CTL
    * switches. The code below closes the AMUX_SPLIT_CTL switches, which route
    * the IDAC output signal from the CSD block to the pin.
    * In this example, IDAC output channels are assigned to the P0[4] and P[5] pins.
    * The AMUX_SPLIT_CTL[5] and AMUX_SPLIT_CTL[6] switches must be closed in the
    * PSoC6 device. The P0[4] and P[5] pins in the PSoC4 device belong to the
    * AMUX bus segment, which is connected to the CSD block directly. In this case,
    * the AMUX_SPLIT_CTL switches are not closed.
    */
    //#if defined(CY_IP_MXCSDV2)
    //#if(1u == CY_IP_MXS40IOSS_VERSION)
    // HSIOM->AMUX_SPLIT_CTL[5] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
    // HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
    // HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
    // HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
    // HSIOM->AMUX_SPLIT_CTL[6] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
    // HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
    // HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
    // HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
    //#elif(2u == CY_IP_MXS40IOSS_VERSION)
    // HSIOM->AMUX_SPLIT_CTL[5] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
    // HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
    // HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
    // HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
    // HSIOM->AMUX_SPLIT_CTL[6] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
    // HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
    // HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
    // HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
    //#else
    // #error Not supported device
    //#endif
    //#endif
    /* Captures the CSD HW block and initializes it to the default state. */
    Cy_CSDIDAC_Init(&CSDIDAC_csdidac_config, &csdidac_context);
    /* Generates a sourcing current of 50 uA (50000 nA) on the IDAC A output. */
    Cy_CSDIDAC_OutputEnable(CY_CSDIDAC_A, 50000, &csdidac_context);
    /* Generates a sinking current of 0.5uA (-500 nA) on the IDAC B output. */
    Cy_CSDIDAC_OutputEnable(CY_CSDIDAC_B, -500, &csdidac_context);

Configuration Considerations

@@ -147,8 +147,8 @@

Sigma Delta)" section of the PSoC 6 Peripheral Driver Library (psoc6pdl) API Reference Manual. This section guides how to set up the CSDIDAC middleware for the operation with the following parameters:

  1. Device VDDA: 3.3V.
  2. Device Peri Clock frequency: 48MHz.
    3. -
  3. IDAC A is sourcing current of 50 uA to GPIO pin P6[2].
    4. -
  4. IDAC B is sinking current of 0.5uA from GPIO pin P6[3].
    5. +
  5. IDAC A is sourcing current of 50 uA to GPIO pin P0[4].
    6. +
  6. IDAC B is sinking current of 0.5uA from GPIO pin P0[5].

There are two methods for the CSDIDAC Middleware configuration:

  1. Use ModusToolbox Device Configurator Tool to generate initialization code
    2. @@ -196,16 +196,20 @@

    The steps required to implement the initialization code manually:

    1. Launch the ModusToolbox Middleware Selector and enable the CSD IDAC middleware. This step is required only if the ModusToolbox IDE is used. Otherwise, ensure the CSDIDAC Middleware is included in your project.
    2. Define the CSD HW block base address. See the code example below:
      #define CSDIDAC_HW (CSD0)
      3. -
    3. Declare the CSD HW driver context structure and initialize the lockKey field with the CY_CSD_NONE_KEY value. See the code example below:
      cy_stc_csd_context_t csdDriverContext =
      {
      .lockKey = CY_CSD_NONE_KEY, /* Initialization of the lockKey with the CY_CSD_NONE_KEY
      is required */
      };
      4. -
    4. Declare the CSDIDAC configuration structure and initialize it according to the desired parameters. See the code example below:
      /* Assign the IDAC A channel to P6[2] */
      static const cy_stc_csdidac_pin_t csdIdacAPin =
      {
      .ioPcPtr = GPIO_PRT6,
      .pin = 2u,
      };
      /* Assign the IDAC B channel to P6[3] */
      static const cy_stc_csdidac_pin_t csdIdacBPin =
      {
      .ioPcPtr = GPIO_PRT6,
      .pin = 3u,
      };
      const cy_stc_csdidac_config_t CSDIDAC_csdidac_config =
      {
      .base = CSDIDAC_HW, /* The CSD0 HW block is selected for CSDIDAC operation. */
      .csdCxtPtr = &csdDriverContext, /* Points to the CSD driver context structure. */
      .configA = CY_CSDIDAC_GPIO, /* Routes the IDAC A output to the pin. */
      .configB = CY_CSDIDAC_GPIO, /* Routes the IDAC B output to the pin. */
      .ptrPinA = (const cy_stc_csdidac_pin_t *) &csdIdacAPin, /* Points to the structure with configured IDAC A Port/Pin. */
      .ptrPinB = (const cy_stc_csdidac_pin_t *) &csdIdacBPin, /* Points to the structure with configured IDAC B Port/Pin. */
      .cpuClk = 48000000u, /* Provides the absolute CPU clock frequency in the current design (configured to 48MHz). */
      .csdInitTime = 25u, /* Configures the CSD0 wake-up initialization time to 25 us (as default). */
      };
      5. -
    5. Assign the Peripheral Clock Divider to the CSD HW block and configure the divider value. See the code example below and refer to the main() routine code snippet in Quick Start Guide
      /*
      * The code below performs the following operations:
      * 1. Disable the Peripheral Clock Divider with index #0 before it
      * is assigned to the CSD HW block.
      * 2. Assign the Peripheral Clock Divider with index #0 to the CSD HW block.
      * 3. Configure the assigned divider with divider value 0 (to divide by 1).
      * 4. Enable the assigned divider.
      *
      * PCLK_CSD_CLOCK - Connects the divider to the CSD HW block
      * CY_SYSCLK_DIV_8_BIT - Uses the 8-bit divider. This divider is to
      * limit the CSD clock frequency to 50 MHz. The Peri Clock frequency
      * is 48 MHz (refer to the Configuration Considerations section), so the divider
      * value is 0 (to divide by 1). No need for a wider divider type.
      *
      * 0 = select divider with index #0.
      */
      Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0u);
      Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0u);
      Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0u, 0u);
      Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0u);
      6. -
    6. Set the configuration of the HSIOM_AMUX_SPLIT_CTL switches to route signal from CSD HW block to the pins configured as the CSDIDAC output channels. The AMUX_SPLIT_CTL[4] switches are closed to connect port P6 with the CSD HW block. Refer to the Technical Reference Manual (TRM) for more information regarding the analog interconnection. See the code example below and refer to the main() routine code snippet in Quick Start Guide
      #if(1u == CY_IP_MXS40IOSS_VERSION)
      HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | /* Closes the left AMUX-A switch of AMUX splitter #4. */
      HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | /* Closes the right AMUX-A switch of AMUX splitter #4. */
      HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | /* Closes the left AMUX-B switch of AMUX splitter #4. */
      HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; /* Closes the right AMUX-B switch of AMUX splitter #4. */
      #elif(2u == CY_IP_MXS40IOSS_VERSION)
      HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | /* Closes the left AMUX-A switch of AMUX splitter #4. */
      HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | /* Closes the right AMUX-A switch of AMUX splitter #4. */
      HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | /* Closes the left AMUX-B switch of AMUX splitter #4. */
      HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; /* Closes the right AMUX-B switch of AMUX splitter #4. */
      #else
      #error Not supported device
      #endif /* (1u == CY_IP_MXS40IOSS_VERSION) */
      Note
      Some CSDIDAC configurations are restricted. The CSD personality has a mechanism to prevent writing an invalid configuration. If CSDIDAC is manually created, avoid the following combinations:
        +
      • Declare the CSD HW driver context structure and initialize the lockKey field with the CY_CSD_NONE_KEY value. See the code example below:
        cy_stc_csd_context_t csdDriverContext =
        {
        .lockKey = CY_CSD_NONE_KEY, /* Initialization of the lockKey with the CY_CSD_NONE_KEY
        is required */
        };
        • +
      • Declare the CSDIDAC configuration structure and initialize it according to the desired parameters. See the code example below:
        /* Assign the IDAC A channel to P0[4] */
        static const cy_stc_csdidac_pin_t csdIdacAPin =
        {
        .ioPcPtr = GPIO_PRT0,
        .pin = 4u,
        };
        /* Assign the IDAC B channel to P0[5] */
        static const cy_stc_csdidac_pin_t csdIdacBPin =
        {
        .ioPcPtr = GPIO_PRT0,
        .pin = 5u,
        };
        const cy_stc_csdidac_config_t CSDIDAC_csdidac_config =
        {
        .base = CSDIDAC_HW, /* The CSD0 HW block is selected for CSDIDAC operation. */
        .csdCxtPtr = &csdDriverContext, /* Points to the CSD driver context structure. */
        .configA = CY_CSDIDAC_GPIO, /* Routes the IDAC A output to the pin. */
        .configB = CY_CSDIDAC_GPIO, /* Routes the IDAC B output to the pin. */
        .ptrPinA = (const cy_stc_csdidac_pin_t *) &csdIdacAPin, /* Points to the structure with configured IDAC A Port/Pin. */
        .ptrPinB = (const cy_stc_csdidac_pin_t *) &csdIdacBPin, /* Points to the structure with configured IDAC B Port/Pin. */
        .cpuClk = 48000000u, /* Provides the absolute CPU clock frequency in the current design (configured to 48MHz). */
        #if defined(CY_IP_MXCSDV2)
        .csdInitTime = 25u, /* Configures the CSD0 wake-up initialization time to 25 us (as default) for the PSoC 6 device. */
        #else
        .csdInitTime = 10u, /* Configures the CSD0 wake-up initialization time to 10 us (as default) for the PSoC 4 device. */
        #endif /* CY_IP_MXCSDV2 */
        };
        • +
      • Assign the Peripheral Clock Divider to the CSD HW block and configure the divider value. See the code example below and refer to the main() routine code snippet in Quick Start Guide
        /*
        * The code below performs the following operations:
        * 1. Disable the Peripheral Clock Divider with index #0 before it
        * is assigned to the CSD HW block.
        * 2. Assign the Peripheral Clock Divider with index #0 to the CSD HW block.
        * 3. Configure the assigned divider with divider value 0 (to divide by 1).
        * 4. Enable the assigned divider.
        *
        * PCLK_CSD_CLOCK - Connects the divider to the CSD HW block
        * CY_SYSCLK_DIV_8_BIT - Uses the 8-bit divider. This divider is to
        * limit the CSD clock frequency to 50 MHz. The Peri Clock frequency
        * is 48 MHz (refer to the Configuration Considerations section), so the divider
        * value is 0 (to divide by 1). No need for a wider divider type.
        *
        * 0 = select divider with index #0.
        */
        #if defined(CY_IP_MXCSDV2)
        Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0u);
        Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0u);
        Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0u, 0u);
        Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0u);
        #elif defined(CY_IP_M0S8CSDV2)
        Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0u);
        Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_16_BIT, 0u);
        Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0u, 0u);
        Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0u);
        #else
        #error Not supported device
        #endif /* CY_IP_MXCSDV2 */
        • +

      • Set the configuration of the HSIOM_AMUX_SPLIT_CTL switches to route signal from CSD HW block to the pins configured as the CSDIDAC output channels.

        +

        The AMUX bus has segments that are separated with the HSIOM_AMUX_SPLIT_CTL switches. The code below closes the AMUX_SPLIT_CTL switches, which route the IDAC output signal from the CSD block to the pin. In this example, IDAC output channels are assigned to the P0[4] and P[5] pins. The AMUX_SPLIT_CTL[5] and AMUX_SPLIT_CTL[6] switches must be closed in the PSoC6 device. The P0[4] and P[5] pins in the PSoC4 device belong to the AMUX bus segment, which is connected to the CSD block directly. In this case, the AMUX_SPLIT_CTL switches are not closed. Refer to the Technical Reference Manual (TRM) for more information regarding the analog interconnection. See the code example below and refer to the main() routine code snippet in Quick Start Guide

        #if defined(CY_IP_MXCSDV2)
        #if(1u == CY_IP_MXS40IOSS_VERSION)
        HSIOM->AMUX_SPLIT_CTL[5] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | /* Closes the left AMUX-A switch of AMUX splitter #5. */
        HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | /* Closes the right AMUX-A switch of AMUX splitter #5. */
        HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | /* Closes the left AMUX-B switch of AMUX splitter #5. */
        HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; /* Closes the right AMUX-B switch of AMUX splitter #5. */
        HSIOM->AMUX_SPLIT_CTL[6] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | /* Closes the left AMUX-A switch of AMUX splitter #6. */
        HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | /* Closes the right AMUX-A switch of AMUX splitter #6. */
        HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | /* Closes the left AMUX-B switch of AMUX splitter #6. */
        HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; /* Closes the right AMUX-B switch of AMUX splitter #6. */
        #elif(2u == CY_IP_MXS40IOSS_VERSION)
        HSIOM->AMUX_SPLIT_CTL[5] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | /* Closes the left AMUX-A switch of AMUX splitter #5. */
        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | /* Closes the right AMUX-A switch of AMUX splitter #5. */
        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | /* Closes the left AMUX-B switch of AMUX splitter #5. */
        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; /* Closes the right AMUX-B switch of AMUX splitter #5. */
        HSIOM->AMUX_SPLIT_CTL[6] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | /* Closes the left AMUX-A switch of AMUX splitter #6. */
        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk | /* Closes the right AMUX-A switch of AMUX splitter #6. */
        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | /* Closes the left AMUX-B switch of AMUX splitter #6. */
        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk; /* Closes the right AMUX-B switch of AMUX splitter #6. */
        #else
        #error Not supported device
        #endif /* (1u == CY_IP_MXS40IOSS_VERSION) */
        #endif /* CY_IP_MXCSDV2 */
        Note
        If you use a KIT, check on the schematics, if pins P0[4] and P0[5] are free. If not, use some other pins and update the AMUX_SPLIT_CTL registers.
        +
        +Some CSDIDAC configurations are restricted. The CSD personality has a mechanism to prevent writing an invalid configuration. If CSDIDAC is manually created, avoid the following combinations:
        • both IDAC channels are disabled
        • one IDAC channel is disabled and another channel is joined to it
        • the IDAC A channel and IDAC B channel are joined to each other
        -Refer to Quick Start Guide section for the application layer code required to set up the CSDIDAC and to get the desired current on the assigned pin.
        • +

        Refer to Quick Start Guide section for the application layer code required to set up the CSDIDAC and to get the desired current on the assigned pin.

        +

    Use Cases

    @@ -214,14 +218,14 @@

    Low power design

    The CSD HW block and CSDIDAC middleware can operate in CPU active and CPU sleep power modes. It is also possible to switch between low power and ultra low power system modes. In System Deep Sleep and Hibernate power modes, the CSD HW block is powered off and CSDIDAC operations are not performed. Before entering CPU / System Deep Sleep, disable CSDIDAC output current generation. If output currents are not disabled, a CPU Deep Sleep transition will fail. When the device wakes up from CPU / System Deep Sleep, the CSD HW block resumes operation without the need for re-initialization and the CSDIDAC operations can be continued with configuration that was set before a CPU / System Deep Sleep transition. When the device wakes up from Hibernate power mode, the CSD HW block does not retain the configuration and CSDIDAC requires re-initialization.

    Note
      -
    1. Analog start up time for the CSD HW block is 25 us. Initiate any kind of operation only after 25 us from System Deep Sleep / Hibernate exit.
      2. +
    2. Analog start up time for the CSD HW block is 25 us for PSoC6 devices and 10 us for PSoC4 devices. Initiate any kind of operation only after 25 us for PSoC6 devices and 10 us for PSoC4 devices from System Deep Sleep / Hibernate exit.
    3. Entering CPU Deep Sleep mode does not mean the device enters System Deep Sleep. For more detail about switching to System Deep Sleep, refer to the device TRM.

    Refer to the Cy_CSDIDAC_DeepSleepCallback() function description and to the SysPm (System Power Management) driver documentation for the low power design considerations.

    Sleep mode
    - The CSD HW block can operate in CPU sleep mode. The user can start CSDIDAC and move CPU into sleep mode to reduce power consumption. After wake-up CPU from sleep, the user can perform other operations, e.g. disable IDACs. Then, the user configures the CSDIDAC middleware as described in Configuration Considerations, and updates the main() routine with the following code:

    /* Scenario: There is a need to generate two output currents while CPU is in Sleep mode. */
    /* ... */
    for (;;)
    {
    /* Starts CSDIDAC generation of two output currents. */
    if (CY_CSDIDAC_SUCCESS != Cy_CSDIDAC_OutputEnable(CY_CSDIDAC_A, 50000, &csdidac_context))
    {
    /* You can place error handler code here. */
    }
    if (CY_CSDIDAC_SUCCESS != Cy_CSDIDAC_OutputEnable(CY_CSDIDAC_B, -500, &csdidac_context))
    {
    /* You can place error handler code here. */
    }
    /*
    * Goes to CPU Sleep mode and waits for an interrupt (or another wake-up event).
    * It is the user's responsibility to provide an interrupt source for a reliable CPU wake-up.
    */
    if(CY_SYSPM_SUCCESS != Cy_SysPm_CpuEnterSleep(CY_SYSPM_WAIT_FOR_INTERRUPT))
    {
    /* You can place error handler code here. */
    }
    /*
    * Insert here code to perform after Sleep mode operations, e.g. to disable IDACs.
    */
    }

    Deep Sleep mode
    - To use the CSDIDAC middleware in CPU / System Deep Sleep mode, the user configures a wake-up source (e.g. a pin, WDT, LPC or another entities, that are active in CPU / System Deep Sleep mode), configures the CSDIDAC middleware as described in Configuration Considerations, configures CSDIDAC and other drivers' and middleware's (if presented) Deep Sleep Callback structures, registers callbacks, and updates the main() routine with the following code:

    /* CSDIDAC DeepSleep Callback parameters structure */
    cy_stc_syspm_callback_params_t CSDIDAC_deepSleepParamStr =
    {
    CSDIDAC_HW, /* Points to the CSD HW block base */
    &csdidac_context, /* Points to the CSDIDAC context structure */
    };
    /* CSDIDAC DeepSleep Callback structure */
    cy_stc_syspm_callback_t CSDIDAC_deepSleepCallbackStr =
    {
    &Cy_CSDIDAC_DeepSleepCallback, /* Points to the CSDIDAC Callback function */
    CY_SYSPM_DEEPSLEEP, /* The Callback type */
    0u, /* The skip modes mask */
    &CSDIDAC_deepSleepParamStr, /* Points to the Callback parameters structure */
    NULL, /* Reserved */
    NULL, /* Reserved */
    10u, /* The callback priority, can be from 1 (the highest) to 255 (the lowest)*/
    };
    /*
    * Scenario: There is a need to generate two output currents and use them for some operations,
    * and then go to Deep Sleep with wake-up on some event.
    */
    /* ... */
    /* Registers CSDADC DeepSleep Callback. */
    if (true != Cy_SysPm_RegisterCallback(&CSDIDAC_deepSleepCallbackStr))
    {
    /* You can place error handler code here. */
    }
    /* ... */
    for (;;)
    {
    /* Starts CSDIDAC generation of two output currents. */
    if (CY_CSDIDAC_SUCCESS != Cy_CSDIDAC_OutputEnable(CY_CSDIDAC_A, 50000, &csdidac_context))
    {
    /* You can place error handler code here. */
    }
    if (CY_CSDIDAC_SUCCESS != Cy_CSDIDAC_OutputEnable(CY_CSDIDAC_B, -500, &csdidac_context))
    {
    /* You can place error handler code here. */
    }
    /*
    * Insert here code to use generated currents.
    */
    /* Disables CSDIDAC generation to allow a Deep Sleep transition. */
    if (CY_CSDIDAC_SUCCESS != Cy_CSDIDAC_OutputDisable(CY_CSDIDAC_AB, &csdidac_context))
    {
    /* You can place error handler code here. */
    }
    /*
    * Then CPU goes to Deep Sleep and waits for an interrupt (or another wake-up event).
    * It is the user's responsibility to provide an interrupt source for a reliable CPU wake-up.
    */
    if(CY_SYSPM_SUCCESS != Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT))
    {
    /* You can place error handler code here. */
    }
    /* Wakes up CSDIDAC after a successful exit from Deep Sleep. */
    if (CY_CSDIDAC_SUCCESS != Cy_CSDIDAC_Wakeup(&csdidac_context))
    {
    /* You can place error handler code here. */
    }
    /*
    * After Deep Sleep, CPU and CSD HW block wake-up, CSDIDAC can generate
    * two output currents, as it was configured before transitions.
    */
    /* ... */
    }

    + The CSD HW block can operate in CPU sleep mode. The user can start CSDIDAC and move CPU into sleep mode to reduce power consumption. After wake-up CPU from sleep, the user can perform other operations, e.g. disable IDACs. Then, the user configures the CSDIDAC middleware as described in Configuration Considerations, and updates the main() routine with the following code:

    /* Scenario: There is a need to generate two output currents while CPU is in Sleep mode. */
    /* ... */
    for (;;)
    {
    /* Starts CSDIDAC generation of two output currents. */
    if (CY_CSDIDAC_SUCCESS != Cy_CSDIDAC_OutputEnable(CY_CSDIDAC_A, 50000, &csdidac_context))
    {
    /* You can place error handler code here. */
    }
    if (CY_CSDIDAC_SUCCESS != Cy_CSDIDAC_OutputEnable(CY_CSDIDAC_B, -500, &csdidac_context))
    {
    /* You can place error handler code here. */
    }
    /*
    * Goes to CPU Sleep mode and waits for an interrupt (or another wake-up event).
    * It is the user's responsibility to provide an interrupt source for a reliable CPU wake-up.
    */
    if(CY_SYSPM_SUCCESS != Cy_SysPm_CpuEnterSleep(CY_SYSPM_WAIT_FOR_INTERRUPT))
    {
    /* You can place error handler code here. */
    }
    /*
    * Insert here code to perform after Sleep mode operations, e.g. to disable IDACs.
    */
    }

    Deep Sleep mode
    + To use the CSDIDAC middleware in CPU / System Deep Sleep mode, the user configures a wake-up source (e.g. a pin, WDT, LPC or another entities, that are active in CPU / System Deep Sleep mode), configures the CSDIDAC middleware as described in Configuration Considerations, configures CSDIDAC and other drivers' and middleware's (if present) Deep Sleep Callback structures, registers callbacks, and updates the main() routine with the following code:

    /* CSDIDAC DeepSleep Callback parameters structure */
    cy_stc_syspm_callback_params_t CSDIDAC_deepSleepParamStr =
    {
    CSDIDAC_HW, /* Points to the CSD HW block base */
    &csdidac_context, /* Points to the CSDIDAC context structure */
    };
    /* CSDIDAC DeepSleep Callback structure */
    cy_stc_syspm_callback_t CSDIDAC_deepSleepCallbackStr =
    {
    &Cy_CSDIDAC_DeepSleepCallback, /* Points to the CSDIDAC Callback function */
    CY_SYSPM_DEEPSLEEP, /* The Callback type */
    0u, /* The skip modes mask */
    &CSDIDAC_deepSleepParamStr, /* Points to the Callback parameters structure */
    NULL, /* Reserved */
    NULL, /* Reserved */
    10u, /* The callback priority, can be from 1 (the highest) to 255 (the lowest)*/
    };
    /*
    * Scenario: There is a need to generate two output currents and use them for some operations,
    * and then go to Deep Sleep with wake-up on some event.
    */
    /* ... */
    /* Registers CSDIDAC DeepSleep Callback. */
    if (true != Cy_SysPm_RegisterCallback(&CSDIDAC_deepSleepCallbackStr))
    {
    /* You can place error handler code here. */
    }
    /* ... */
    for (;;)
    {
    /* Starts CSDIDAC generation of two output currents. */
    if (CY_CSDIDAC_SUCCESS != Cy_CSDIDAC_OutputEnable(CY_CSDIDAC_A, 50000, &csdidac_context))
    {
    /* You can place error handler code here. */
    }
    if (CY_CSDIDAC_SUCCESS != Cy_CSDIDAC_OutputEnable(CY_CSDIDAC_B, -500, &csdidac_context))
    {
    /* You can place error handler code here. */
    }
    /*
    * Insert here code to use generated currents.
    */
    /* Disables CSDIDAC generation to allow a Deep Sleep transition. */
    if (CY_CSDIDAC_SUCCESS != Cy_CSDIDAC_OutputDisable(CY_CSDIDAC_AB, &csdidac_context))
    {
    /* You can place error handler code here. */
    }
    /*
    * Then CPU goes to Deep Sleep and waits for an interrupt (or another wake-up event).
    * It is the user's responsibility to provide an interrupt source for a reliable CPU wake-up.
    */
    #if defined(CY_IP_MXCSDV2)
    if(CY_SYSPM_SUCCESS != Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT))
    {
    /* You can place error handler code here. */
    }
    #elif defined(CY_IP_M0S8CSDV2)
    if(CY_SYSPM_SUCCESS != Cy_SysPm_SystemEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT))
    {
    /* You can place error handler code here. */
    }
    #else
    #error Not supported device
    #endif /* CY_IP_MXCSDV2 */
    /* Wakes up CSDIDAC after a successful exit from Deep Sleep. */
    if (CY_CSDIDAC_SUCCESS != Cy_CSDIDAC_Wakeup(&csdidac_context))
    {
    /* You can place error handler code here. */
    }
    /*
    * After Deep Sleep, CPU and CSD HW block wake-up, CSDIDAC can generate
    * two output currents, as it was configured before transitions.
    */
    /* ... */
    }

    Time-multiplexing operation

    Refer to the CapSense Middleware API Reference Guide for implementation of the time-multiplexing operation by using common CSD HW block.

    @@ -231,13 +235,17 @@

- + + + + + - + - + - + @@ -245,7 +253,7 @@

- +
-
Cypress CSDIDAC Middleware Library 2.0
+
CSDIDAC Middleware Library 2.10
Software and Tools Version
ModusToolbox Software Environment 2.0
ModusToolbox Software Environment 2.1
- ModusToolbox Device Configurator 2.1
- ModusToolbox CSD Personality for PSoC4 devices in Device Configurator 1.0
- ModusToolbox Device Configurator 2.0
- ModusToolbox CSD Personality for PSoC6 devices in Device Configurator 2.0
- ModusToolbox CSD Personality in Device Configurator 2.0
PSoC4 Peripheral Driver Library (PDL) 1.0.0
PSoC6 Peripheral Driver Library (PDL) 1.2.0
PSoC6 Peripheral Driver Library (PDL) 1.5.0
GCC Compiler 7.2.1
Arm Compiler 6 6.11
MBED OS 5.13.1
MBED OS (only for PSoC6) 5.15.1
FreeRTOS 10.0.1
@@ -276,6 +284,10 @@

VersionChangesReason for Change +2.10 Added the support of PSoC 4 CapSense Forth Generation devices Devices support + +Minor documentation update Documentation cleanup + 2.0 The joining two IDAC channels option is added to increase the maximum CSDIDAC output current Feature enchancement The cy_stc_csdidac_config_t structure is changed: the periClk field replaced with cpuClk, busOnlyA and busOnlyB fields replaced with configA and configB fields respectively, the field order is changed. The cy_en_csdidac_channel_config_t enumeration type is added. User experience improvement @@ -290,27 +302,49 @@

More Information

+

Important information about the CapSense-technology overview, appropriate device for the design, CapSense system and sensor design guidelines, different interfaces and tuning guidelines necessary for a successful design of a CapSense system is available in the Getting Started with CapSense document and the product-specific CapSense design guide. It is highly recommended to start with these documents. They can be found at www.cypress.com.

For more information, refer to the following documents:

+
Note
The links to another software component's documentation (middleware and PDL) point to GitHub to the latest available version of the software. To get documentation of the specified version, download from GitHub and unzip the component archive. The documentation is available in the docs folder.