Engineering student based in Germany. I explore the intersection of wireless communication, cybersecurity, and hardware design — from baseband algorithms to FPGA bitstreams.

• Wireless Communication — SDR, channel estimation, signal processing with MATLAB & Python
• FPGA & Digital Design — RTL development in SystemVerilog, hardware-software co-design
• Cybersecurity — network security research, protocol analysis
• Backend Engineering — building robust systems and tooling

MATLAB Python C/C++ SystemVerilog Cython FPGA GNU Radio UHD Linux

• 🤝 Contributor to UHD — the open-source driver & framework for Ettus USRP software defined radios
• 📡 Co-maintainer of PicoScenes-Python-Toolbox — parsing CSI data for WiFi sensing research
• 📘 Author of CythonTutorial — a hands-on guide to boosting Python performance with Cython

"The best way to understand a system is to build one."