initial

Author: HardwareLevel

NRF24.c

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+#include <stdio.h>
+#include "stm32f1xx_hal.h"
+#include "NRF24_conf.h"
+#include "NRF24_reg_addresses.h"
+#include "NRF24.h"
+
+extern SPI_HandleTypeDef hspiX;
+
+
+void csn_high(void){
+	HAL_GPIO_WritePin(csn_gpio_port, csn_gpio_pin, 1);
+}
+
+void csn_low(void){
+	HAL_GPIO_WritePin(csn_gpio_port, csn_gpio_pin, 0);
+}
+
+void ce_high(void){
+	HAL_GPIO_WritePin(ce_gpio_port, ce_gpio_pin, 1);
+}
+
+void ce_low(void){
+	HAL_GPIO_WritePin(ce_gpio_port, ce_gpio_pin, 0);
+}
+
+void nrf24_w_reg(uint8_t reg, uint8_t *data, uint8_t size){
+
+	uint8_t cmd = W_REGISTER | reg;
+
+	csn_low();
+
+	HAL_SPI_Transmit(&hspiX, &cmd, 1, spi_w_timeout);
+	HAL_SPI_Transmit(&hspiX, data, size, spi_w_timeout);
+
+	csn_high();
+}
+
+uint8_t nrf24_r_reg(uint8_t reg, uint8_t size){
+	uint8_t cmd = R_REGISTER | reg;
+	uint8_t data = 0;
+
+	csn_low();
+
+	HAL_SPI_Transmit(&hspiX, &cmd, 1, spi_w_timeout);
+	HAL_SPI_Receive(&hspiX, &data, size, spi_r_timeout);
+
+	csn_high();
+
+	return data;
+}
+
+void nrf24_w_spec_cmd(uint8_t cmd){
+	HAL_SPI_Transmit(&hspiX, &cmd, 1, spi_w_timeout);
+}
+
+void nrf24_w_spec_reg(uint8_t *data, uint8_t size){
+	HAL_SPI_Transmit(&hspiX, data, size, spi_w_timeout);
+}
+
+void nrf24_r_spec_reg(uint8_t *data, uint8_t size){
+	HAL_SPI_Receive(&hspiX, data, size, spi_r_timeout);
+}
+
+void nrf24_pwr_up(void){
+	uint8_t data = 0;
+
+	data = nrf24_r_reg(CONFIG, 1);
+
+	data |= (1 << PWR_UP);
+
+	nrf24_w_reg(CONFIG, &data, 1);
+}
+
+void nrf24_pwr_dwn(void){
+	uint8_t data = 0;
+
+	data = nrf24_r_reg(CONFIG, 1);
+
+	data &= ~(1 << PWR_UP);
+
+	nrf24_w_reg(CONFIG, &data, 1);
+}
+
+void nrf24_tx_pwr(uint8_t pwr){
+	uint8_t data = 0;
+
+	data = nrf24_r_reg(RF_SETUP, 1);
+
+	data &= 184;
+
+	data |= (pwr << RF_PWR);
+
+	nrf24_w_reg(RF_SETUP, &data, 1);
+}
+
+void nrf24_data_rate(uint8_t bps){
+	uint8_t data = 0;
+
+	data = nrf24_r_reg(RF_SETUP, 1);
+
+	data &= ~(1 << RF_DR_LOW) & ~(1 << RF_DR_HIGH);
+
+	if(bps == _2Mbps){
+		data |= (1 << RF_DR_HIGH);
+	}else if(bps == _250kbps){
+		data |= (1 << RF_DR_LOW);
+	}
+
+	nrf24_w_reg(RF_SETUP, &data, 1);
+}
+
+void nrf24_set_channel(uint8_t ch){
+	nrf24_w_reg(RF_CH, &ch, 1);
+}
+
+void nrf24_open_tx_pipe(uint8_t *addr){
+	nrf24_w_reg(TX_ADDR, addr, 5);
+}
+
+void nrf24_pld_size(uint8_t size){
+	if(size > 32){
+		size = 32;
+	}else if(size < 0){
+		size = 0;
+	}
+
+	nrf24_w_reg(RX_PW_P0, &size, 1);
+	nrf24_w_reg(RX_PW_P1, &size, 1);
+	nrf24_w_reg(RX_PW_P2, &size, 1);
+	nrf24_w_reg(RX_PW_P3, &size, 1);
+	nrf24_w_reg(RX_PW_P4, &size, 1);
+	nrf24_w_reg(RX_PW_P5, &size, 1);
+}
+
+void nrf24_open_rx_pipe(uint8_t pipe, uint8_t *addr){
+
+	uint8_t data = 0;
+
+	data = nrf24_r_reg(EN_RXADDR, 1);
+
+	switch(pipe){
+	case 0:
+		nrf24_w_reg(RX_ADDR_P0, addr, 5);
+
+		data |= (1 << ERX_P0);
+		break;
+	case 1:
+		nrf24_w_reg(RX_ADDR_P1, addr, 5);
+
+		data |= (1 << ERX_P1);
+		break;
+	case 2:
+		nrf24_w_reg(RX_ADDR_P2, addr, 1);
+
+		data |= (1 << ERX_P2);
+		break;
+	case 3:
+		nrf24_w_reg(RX_ADDR_P3, addr, 1);
+
+		data |= (1 << ERX_P3);
+		break;
+	case 4:
+		nrf24_w_reg(RX_ADDR_P4, addr, 1);
+
+		data |= (1 << ERX_P4);
+		break;
+	case 5:
+		nrf24_w_reg(RX_ADDR_P5, addr, 1);
+
+		data |= (1 << ERX_P5);
+		break;
+	}
+
+	nrf24_w_reg(EN_RXADDR, &data, 1);
+}
+
+void nrf24_cls_rx_pipe(uint8_t pipe){
+	uint8_t data = nrf24_r_reg(EN_RXADDR, 1);
+
+	data &= ~(1 << pipe);
+
+	nrf24_w_reg(EN_RXADDR, &data, 1);
+}
+
+void nrf24_set_crc(uint8_t en_crc, uint8_t crc0){
+	uint8_t data = nrf24_r_reg(CONFIG, 1);
+
+	data &= ~(1 << EN_CRC) & ~(1 << CRCO);
+
+	data |= (en_crc << EN_CRC) | (crc0 << CRCO);
+
+	nrf24_w_reg(CONFIG, &data, 1);
+}
+
+void nrf24_set_addr_width(uint8_t bytes){
+	bytes -= 2;
+	nrf24_w_reg(SETUP_AW, &bytes, 1);
+}
+
+void nrf24_flush_tx(void){
+	csn_low();
+	nrf24_w_spec_cmd(FLUSH_TX);
+	csn_high();
+}
+
+void nrf24_flush_rx(void){
+	csn_low();
+	nrf24_w_spec_cmd(FLUSH_RX);
+	csn_high();
+}
+
+void nrf24_clear_rx_dr(void){
+	uint8_t data = 0;
+
+	data = nrf24_r_reg(STATUS, 1);
+
+	data |= (1 << RX_DR);
+
+	nrf24_w_reg(STATUS, &data, 1);
+}
+
+void nrf24_clear_tx_ds(void){
+	uint8_t data = 0;
+
+	data = nrf24_r_reg(STATUS, 1);
+
+	data |= (1 << TX_DS);
+
+    nrf24_w_reg(STATUS, &data, 1);
+}
+
+void nrf24_clear_max_rt(void){
+	uint8_t data = 0;
+
+	data = nrf24_r_reg(STATUS, 1);
+
+	data |= (1 << MAX_RT);
+
+    nrf24_w_reg(STATUS, &data, 1);
+}
+
+uint8_t nrf24_r_pld_wid(void){
+	uint8_t width = 0;
+
+	csn_low();
+	nrf24_w_spec_cmd(R_RX_PL_WID);
+	nrf24_r_spec_reg(&width, 1);
+	csn_high();
+
+	return width;
+}
+
+void nrf24_listen(void){
+	uint8_t data = 0;
+
+	data = nrf24_r_reg(CONFIG, 1);
+
+	data |= (1 << PRIM_RX);
+
+	nrf24_w_reg(CONFIG, &data, 1);
+}
+
+void nrf24_stop_listen(void){
+	uint8_t data = 0;
+
+	data = nrf24_r_reg(CONFIG, 1);
+
+	data &= ~(1 << PRIM_RX);
+
+	nrf24_w_reg(CONFIG, &data, 1);
+}
+
+void nrf24_ack(uint8_t ack){
+
+}
+
+void nrf24_transmit(uint8_t *data, uint8_t size){
+
+	ce_low();
+
+	nrf24_flush_tx();
+
+	nrf24_clear_tx_ds();
+
+	csn_low();
+	nrf24_w_spec_cmd(W_TX_PAYLOAD);//W_TX_PAYLOAD_NOACK
+	nrf24_w_spec_reg(data, size);
+	csn_high();
+
+	ce_high();
+	HAL_Delay(1);
+	ce_low();
+}
+
+uint8_t nrf24_data_available(void){
+
+ 	uint8_t reg_dt = nrf24_r_reg(FIFO_STATUS, 1);
+
+	if(!(reg_dt & (1 << RX_EMPTY))){
+		return 1;
+	}
+
+	return 0;
+}
+
+void nrf24_flush_on_full_rx(void){
+	uint8_t reg_dt = nrf24_r_reg(FIFO_STATUS, 1);
+
+	if((reg_dt & (1 << RX_FULL))){
+		nrf24_flush_rx();
+	}
+}
+
+void nrf24_receive(uint8_t *data, uint8_t size){
+	ce_high();
+
+	uint8_t reg_dt = nrf24_r_reg(STATUS, 1);
+
+	if((reg_dt & (1 << RX_DR))){
+
+		uint8_t wid = nrf24_r_pld_wid();
+
+		if(wid > 32){
+			nrf24_flush_rx();
+		}else{
+			csn_low();
+			nrf24_w_spec_cmd(R_RX_PAYLOAD);
+			nrf24_r_spec_reg(data, size);
+			csn_high();
+		}
+		nrf24_clear_rx_dr();
+	}
+
+}
+
+