@@ -113,7 +113,7 @@ void nrf24_set_channel(uint8_t ch){
113113 nrf24_w_reg (RF_CH , & ch , 1 );
114114}
115115
116- void nrf24_open_tx_pipe (const uint8_t * addr ){
116+ void nrf24_open_tx_pipe (uint8_t * addr ){
117117 nrf24_w_reg (TX_ADDR , addr , 5 );
118118}
119119
@@ -150,7 +150,7 @@ void nrf24_pipe_pld_size(uint8_t pipe, uint8_t size){
150150 }
151151}
152152
153- void nrf24_open_rx_pipe (uint8_t pipe , const uint8_t * addr ){
153+ void nrf24_open_rx_pipe (uint8_t pipe , uint8_t * addr ){
154154
155155 uint8_t data = 0 ;
156156
@@ -264,7 +264,7 @@ uint8_t nrf24_max_rt_flag(void){
264264
265265 data &= (1 << MAX_RT );
266266
267- if (data > 0 ){
267+ if (data ){
268268 return 1 ;
269269 }
270270
@@ -315,80 +315,70 @@ void nrf24_dpl(uint8_t en){
315315}
316316
317317void nrf24_set_rx_dpl (uint8_t pipe , uint8_t en ){
318- uint8_t enaa = nrf24_r_reg ( EN_AA , 1 );
318+
319319 uint8_t dynpd = nrf24_r_reg (DYNPD , 1 );
320320
321321 if (pipe > 5 ){
322322 pipe = 5 ;
323323 }
324324
325- if (en == enable ){
326- switch (pipe ){
327- case 0 :
328- enaa |= (1 << ENAA_P0 );
329- dynpd |= (1 << DPL_P0 );
330- break ;
331- case 1 :
332- enaa |= (1 << ENAA_P1 );
333- dynpd |= (1 << DPL_P1 );
334- break ;
335- case 2 :
336- enaa |= (1 << ENAA_P2 );
337- dynpd |= (1 << DPL_P2 );
338- break ;
339- case 3 :
340- enaa |= (1 << ENAA_P3 );
341- dynpd |= (1 << DPL_P3 );
342- break ;
343- case 4 :
344- enaa |= (1 << ENAA_P4 );
345- dynpd |= (1 << DPL_P4 );
346- break ;
347- case 5 :
348- enaa |= (1 << ENAA_P5 );
349- dynpd |= (1 << DPL_P5 );
350- break ;
351- }
325+ if (en ){
326+ dynpd |= (1 << pipe );
327+ }else {
328+ dynpd &= ~(1 << pipe );
329+ }
330+
331+ nrf24_w_reg (DYNPD , & dynpd , 1 );
332+ }
333+
334+ void nrf24_auto_ack (uint8_t pipe , uint8_t ack ){
335+
336+ if (pipe > 5 ){
337+ pipe = 5 ;
338+ }
339+
340+ uint8_t enaa = nrf24_r_reg (EN_AA , 1 );
352341
342+ if (ack ){
343+ enaa |= (1 << pipe );
353344 }else {
354- switch (pipe ){
355- case 0 :
356- enaa &= ~(1 << ENAA_P0 );
357- dynpd &= ~(1 << DPL_P0 );
358- break ;
359- case 1 :
360- enaa &= ~(1 << ENAA_P1 );
361- dynpd &= ~(1 << DPL_P1 );
362- break ;
363- case 2 :
364- enaa &= ~(1 << ENAA_P2 );
365- dynpd &= ~(1 << DPL_P2 );
366- break ;
367- case 3 :
368- enaa &= ~(1 << ENAA_P3 );
369- dynpd &= ~(1 << DPL_P3 );
370- break ;
371- case 4 :
372- enaa &= ~(1 << ENAA_P4 );
373- dynpd &= ~(1 << DPL_P4 );
374- break ;
375- case 5 :
376- enaa &= ~(1 << ENAA_P5 );
377- dynpd &= ~(1 << DPL_P5 );
378- break ;
379- }
345+ enaa &= ~(1 << pipe );
380346 }
347+
381348 nrf24_w_reg (EN_AA , & enaa , 1 );
382- nrf24_w_reg (DYNPD , & dynpd , 1 );
383349}
384350
385- void nrf24_auto_ack (uint8_t ack ){
351+ void nrf24_auto_ack_all (uint8_t ack ){
352+ uint8_t enaa = nrf24_r_reg (EN_AA , 1 );
353+
354+ if (ack ){
355+ enaa = 63 ;
356+ }else {
357+ enaa = 0 ;
358+ }
359+
360+ nrf24_w_reg (EN_AA , & enaa , 1 );
361+ }
362+
363+ void nrf24_en_ack_pld (uint8_t en ){
364+ uint8_t feature = nrf24_r_reg (FEATURE , 1 );
365+
366+ if (en ){
367+ feature |= (1 << EN_ACK_PAY );
368+ }else {
369+ feature &= ~(1 << EN_ACK_PAY );
370+ }
371+
372+ nrf24_w_reg (FEATURE , & feature , 1 );
373+ }
374+
375+ void nrf24_en_dyn_ack (uint8_t en ){
386376 uint8_t feature = nrf24_r_reg (FEATURE , 1 );
387377
388- if (ack == auto_ack ){
389- feature |= (1 << EN_ACK_PAY ) | ( 1 << EN_DYN_ACK );
390- }else if ( ack == no_auto_ack ) {
391- feature &= ~(1 << EN_ACK_PAY ) & ~( 1 << EN_DYN_ACK );
378+ if (en ){
379+ feature |= (1 << EN_DYN_ACK );
380+ }else {
381+ feature &= ~(1 << EN_DYN_ACK );
392382 }
393383
394384 nrf24_w_reg (FEATURE , & feature , 1 );
@@ -509,9 +499,43 @@ void nrf24_receive(uint8_t *data, uint8_t size){
509499 nrf24_r_spec_reg (data , size );
510500 csn_high ();
511501 }
502+
503+ HAL_Delay (1 );
504+
512505 nrf24_clear_rx_dr ();
513506 }
514507}
515508
509+ void nrf24_defaults (void ){
510+ ce_low ();
511+
512+ nrf24_pwr_dwn ();
513+ nrf24_tx_pwr (3 );
514+ nrf24_data_rate (_1mbps );
515+ nrf24_set_channel (2 );
516+ nrf24_set_crc (no_crc , _1byte );
517+ nrf24_set_addr_width (5 );
518+ nrf24_flush_tx ();
519+ nrf24_flush_rx ();
520+ nrf24_clear_rx_dr ();
521+ nrf24_clear_tx_ds ();
522+ nrf24_clear_max_rt ();
523+ nrf24_stop_listen ();
524+ nrf24_dpl (disable );
525+ nrf24_en_ack_pld (disable );
526+ nrf24_en_dyn_ack (disable );
527+ nrf24_auto_retr_delay (0 );
528+ nrf24_auto_retr_limit (3 );
529+
530+
531+ for (uint8_t i = 0 ; i <= 5 ; i ++ ){
532+ nrf24_pipe_pld_size (i , 0 );
533+ nrf24_cls_rx_pipe (i );
534+ nrf24_set_rx_dpl (i , disable );
535+ nrf24_auto_ack (i , enable );
536+ }
537+
538+ ce_high ();
539+ }
516540
517541
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