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BU4830.LIB
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BU4830.LIB
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*******************************************************************************************
*[Disclaimer]
* This model file is made by typical data,
* and the manufacturing dispersions are not included.
* Moreover, it does not guarantee all of the simulation
* result of execution by using this.
* This model is being supplied as a aid to confirm the validity of
* a design approach and help to select surrounding component values
* While it reflects reasonably close to similarity to the actual
* device in terms of performance, it is not suggested as a
* replacement for breadboarding.
* Simulation should be used as a forerunner or a supplement
* to a traditional lab testing.
*
*[Copyright]
*Copyright 2010 ROHM Co., Ltd.
*
*[Component] BU48xx series
*
*[Manufacturer] ROHM Co., Ltd.
*
*******************************************************************************************
* OrCAD Model Editor - Version 9.1
*******************VERSION HYSTORY*************************************
*1.0 - 06/26/09: Created by Ryan Ordiales from indications of Sho Sai
*1.1 - 10/24/09: Modified by Ryan Ordiales. Removed all connection to 0
* and connected to GND. Created GND pin to comp1, comp2 and comp3
* subcircuit. Removed connection to "Global 0".
*$
*******************comp1 block*****************************************
* VDD
* out |
* in2 | |
* in1 | | |
* | | | |
.subckt comp1 11 10 18 17 GND
.model DZ D(Is=0.05n rs=0.001 bv=10 Ibv=1)
E1 12 GND 11 10 10k
R1 12 13 100k
C1 13 GND 100p
D1 GND 13 DZ
M4 18 13 17 17 PMOS2 l=.6u w=8000u
Rpd 18 GND 30k
***vto is set for the computation of VOLP=0.7V
***gate voltage swings from -0.5V to 10V
.MODEL PMOS2 PMOS (level=1 vto=-1.2145)
.ends comp1
*$
*******************comp2 block*****************************************
* VDD
* out |
* in2 | |
* in1 | | |
* | | | |
.subckt comp2 11 10 18 17 GND
* in1 in2 out VDD
.model DZ D(Is=0.05n rs=0.001 bv=7 Ibv=1)
E1 12 GND 11 10 100k
R1 12 13 100k
C1 13 GND 100p
D1 GND 13 DZ
M6 18 13 17 17 PMOS20 l=1u w=10000u
M7 18 13 GND GND NMOS20 l=1u w=10000u
.MODEL PMOS20 PMOS (level=1 vto=0)
.MODEL NMOS20 NMOS (level=1 vto=0)
.ends comp2
*$
.subckt bu4830 VOUT VDD GND
****************VDET, Hysteresis and Release Block*********************
Cct CT GND 5.1p
X1 11 10 18 29 GND comp2
Vref 10 GND 1
R1b 29 11 20meg
R100 11 16 9.302338meg
R101 16 GND 0.69767meg
M3 16 18 GND GND NMOS2 l=1u w=1000u
.MODEL NMOS2 NMOS (level=1 vto=.1)
.MODEL PMOS1 PMOS (level=1)
.MODEL NMOS1 NMOS (level=1)
*****************TPLH delay block***************************************
M6 15 18 29 29 PMOS22 l=1u w=10000u
M7 14 18 GND GND NMOS22 l=1u w=10000u
.MODEL PMOS22 PMOS (level=1 vto=0)
.MODEL NMOS22 NMOS (level=1 vto=0)
Rct 15 14 9.99875meg
Rct3 14 CT 1.246k
****VCTH circuit****
Rdet1 29 19 10meg
Rdet2 19 GND 10meg
*****************TPHL delay block***************************************
X52 CT 19 20 29 GND comp1
T1 20 GND 222 GND Z0=1meg TD=212u
R500 222 GND 1meg
E500 333 GND poly(2) 20 GND 222 GND 0 0 0 0 2
*****************driver stage block************************************
Mdrv 29 333 334 GND NMOS10 l=1u w=8000u
Rdrv 334 GND 100k
.MODEL NMOS10 NMOS (level=1 vto=0)
******************Open drain NMOS output block*************************
Mout VOUT 334 GND GND NMOS3 l=10u w=4326u
.MODEL NMOS3 NMOS (level=1 vto=.5)
**circuit current
M1cc 65 65 VDD VDD PMOS10 l=10u w=100u
R2cc VDD 65 10meg
D1cc GND 65 DZ2
D2cc 65 66 DZ3
R1cc 66 GND 4.56meg
.model DZ2 D(Is=0.207u Rs=10)
.model DZ3 D(Is=.4u Rs=10meg bv=20 )
.MODEL PMOS10 PMOS (level=1 vto=-0.58)
Evdd 29 GND VDD GND 1
.ends bu4830
*$