diff --git a/llvm/test/CodeGen/ARM/big-endian-vmov.ll b/llvm/test/CodeGen/ARM/big-endian-vmov.ll
index 2cb22b4d5fbc26..1cb7a030d58c26 100644
--- a/llvm/test/CodeGen/ARM/big-endian-vmov.ll
+++ b/llvm/test/CodeGen/ARM/big-endian-vmov.ll
@@ -134,3 +134,103 @@ define arm_aapcs_vfpcc <1 x i64> @vmov_i64_b() {
 ; CHECK-NEXT:    bx lr
   ret <1 x i64> <i64 72056498804490495>
 }
+
+define arm_aapcs_vfpcc <2 x i64> @vmov_v2i64_b() {
+; CHECK-LABEL: vmov_v2i64_b:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmov.i64 q0, #0xffff00ff0000ff
+; CHECK-NEXT:    bx lr
+  ret <2 x i64> <i64 72056498804490495, i64 72056498804490495>
+}
+
+define arm_aapcs_vfpcc <4 x i32> @vmov_v4i32_b() {
+; CHECK-LE-LABEL: vmov_v4i32_b:
+; CHECK-LE:       @ %bb.0:
+; CHECK-LE-NEXT:    vmov.i64 q0, #0xff0000ff00ffff00
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: vmov_v4i32_b:
+; CHECK-BE:       @ %bb.0:
+; CHECK-BE-NEXT:    vmov.i64 q0, #0xffff00ff0000ff
+; CHECK-BE-NEXT:    bx lr
+  ret <4 x i32> <i32 u0xffff00, i32 u0xff0000ff, i32 u0xffff00, i32 u0xff0000ff>
+}
+
+define arm_aapcs_vfpcc <2 x i64> @and_v2i64_b(<2 x i64> %a) {
+; CHECK-LABEL: and_v2i64_b:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmov.i64 q8, #0xffff00ff0000ff
+; CHECK-NEXT:    vand q0, q0, q8
+; CHECK-NEXT:    bx lr
+  %b = and <2 x i64> %a, <i64 72056498804490495, i64 72056498804490495>
+  ret <2 x i64> %b
+}
+
+define arm_aapcs_vfpcc <4 x i32> @and_v4i32_b(<4 x i32> %a) {
+; CHECK-LE-LABEL: and_v4i32_b:
+; CHECK-LE:       @ %bb.0:
+; CHECK-LE-NEXT:    vmov.i64 q8, #0xff0000ff00ffff00
+; CHECK-LE-NEXT:    vand q0, q0, q8
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: and_v4i32_b:
+; CHECK-BE:       @ %bb.0:
+; CHECK-BE-NEXT:    vmov.i64 q8, #0xffff00ff0000ff
+; CHECK-BE-NEXT:    vrev64.32 q9, q0
+; CHECK-BE-NEXT:    vrev64.32 q8, q8
+; CHECK-BE-NEXT:    vand q8, q9, q8
+; CHECK-BE-NEXT:    vrev64.32 q0, q8
+; CHECK-BE-NEXT:    bx lr
+  %b = and <4 x i32> %a, <i32 u0xffff00, i32 u0xff0000ff, i32 u0xffff00, i32 u0xff0000ff>
+  ret <4 x i32> %b
+}
+
+define arm_aapcs_vfpcc <8 x i16> @vmvn_v16i8_m1() {
+; CHECK-LE-LABEL: vmvn_v16i8_m1:
+; CHECK-LE:       @ %bb.0:
+; CHECK-LE-NEXT:    vmvn.i32 q0, #0x10000
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: vmvn_v16i8_m1:
+; CHECK-BE:       @ %bb.0:
+; CHECK-BE-NEXT:    vmvn.i32 q0, #0x1
+; CHECK-BE-NEXT:    bx lr
+  ret <8 x i16> <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
+}
+
+; FIXME: This is incorrect for BE
+define arm_aapcs_vfpcc <8 x i16> @and_v8i16_m1(<8 x i16> %a) {
+; CHECK-LE-LABEL: and_v8i16_m1:
+; CHECK-LE:       @ %bb.0:
+; CHECK-LE-NEXT:    vbic.i32 q0, #0x10000
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: and_v8i16_m1:
+; CHECK-BE:       @ %bb.0:
+; CHECK-BE-NEXT:    vrev64.32 q8, q0
+; CHECK-BE-NEXT:    vbic.i32 q8, #0x10000
+; CHECK-BE-NEXT:    vrev64.32 q0, q8
+; CHECK-BE-NEXT:    bx lr
+  %b = and <8 x i16> %a, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
+  ret <8 x i16> %b
+}
+
+; FIXME: This is incorrect for BE
+define arm_aapcs_vfpcc <8 x i16> @xor_v8i16_m1(<8 x i16> %a) {
+; CHECK-LE-LABEL: xor_v8i16_m1:
+; CHECK-LE:       @ %bb.0:
+; CHECK-LE-NEXT:    vmvn.i32 q8, #0x10000
+; CHECK-LE-NEXT:    veor q0, q0, q8
+; CHECK-LE-NEXT:    bx lr
+;
+; CHECK-BE-LABEL: xor_v8i16_m1:
+; CHECK-BE:       @ %bb.0:
+; CHECK-BE-NEXT:    vmvn.i32 q8, #0x10000
+; CHECK-BE-NEXT:    vrev64.16 q9, q0
+; CHECK-BE-NEXT:    vrev32.16 q8, q8
+; CHECK-BE-NEXT:    veor q8, q9, q8
+; CHECK-BE-NEXT:    vrev64.16 q0, q8
+; CHECK-BE-NEXT:    bx lr
+  %b = xor <8 x i16> %a, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
+  ret <8 x i16> %b
+}
diff --git a/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll b/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
index 97abc539557131..729e4c5e89c75e 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
@@ -12,6 +12,25 @@ entry:
   ret <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
 }
 
+define arm_aapcs_vfpcc <16 x i8> @xor_int8_1(<16 x i8> %a) {
+; CHECKLE-LABEL: xor_int8_1:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i8 q1, #0x1
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int8_1:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i8 q1, #0x1
+; CHECKBE-NEXT:    vrev64.8 q2, q0
+; CHECKBE-NEXT:    veor q1, q2, q1
+; CHECKBE-NEXT:    vrev64.8 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %b
+}
+
 define arm_aapcs_vfpcc <16 x i8> @mov_int8_m1() {
 ; CHECK-LABEL: mov_int8_m1:
 ; CHECK:       @ %bb.0: @ %entry
@@ -21,6 +40,23 @@ entry:
   ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
 }
 
+define arm_aapcs_vfpcc <16 x i8> @xor_int8_m1(<16 x i8> %a) {
+; CHECKLE-LABEL: xor_int8_m1:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmvn q0, q0
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int8_m1:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vrev64.8 q1, q0
+; CHECKBE-NEXT:    vmvn q1, q1
+; CHECKBE-NEXT:    vrev64.8 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <16 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  ret <16 x i8> %b
+}
+
 ; This has 0x01020304 or 0x04030201 vdup.32'd to q reg depending on endianness.
 ; The big endian is different as there is an implicit vrev64.8 out of the
 ; function, which gets constant folded away.
@@ -42,6 +78,98 @@ entry:
   ret <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>
 }
 
+define arm_aapcs_vfpcc <16 x i8> @xor_int8_1234(<16 x i8> %a) {
+; CHECKLE-LABEL: xor_int8_1234:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    movw r0, #513
+; CHECKLE-NEXT:    movt r0, #1027
+; CHECKLE-NEXT:    vdup.32 q1, r0
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int8_1234:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    movw r0, #513
+; CHECKBE-NEXT:    vrev64.8 q1, q0
+; CHECKBE-NEXT:    movt r0, #1027
+; CHECKBE-NEXT:    vdup.32 q0, r0
+; CHECKBE-NEXT:    veor q1, q1, q0
+; CHECKBE-NEXT:    vrev64.8 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <16 x i8> %a, <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>
+  ret <16 x i8> %b
+}
+
+define arm_aapcs_vfpcc <16 x i8> @mov_int8_32() {
+; CHECKLE-LABEL: mov_int8_32:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i32 q0, #0x1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: mov_int8_32:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i32 q0, #0x1000000
+; CHECKBE-NEXT:    bx lr
+entry:
+  ret <16 x i8> <i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0>
+}
+
+; FIXME: This is incorrect for BE
+define arm_aapcs_vfpcc <16 x i8> @xor_int8_32(<16 x i8> %a) {
+; CHECKLE-LABEL: xor_int8_32:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i32 q1, #0x1
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int8_32:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i32 q1, #0x1
+; CHECKBE-NEXT:    vrev64.8 q2, q0
+; CHECKBE-NEXT:    vrev32.8 q1, q1
+; CHECKBE-NEXT:    veor q1, q2, q1
+; CHECKBE-NEXT:    vrev64.8 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <16 x i8> %a, <i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0>
+  ret <16 x i8> %b
+}
+
+define arm_aapcs_vfpcc <16 x i8> @mov_int8_64() {
+; CHECKLE-LABEL: mov_int8_64:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i64 q0, #0xffff00ffff0000ff
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: mov_int8_64:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i64 q0, #0xff0000ffff00ffff
+; CHECKBE-NEXT:    bx lr
+entry:
+  ret <16 x i8> <i8 255, i8 0, i8 0, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 0, i8 255, i8 255, i8 0, i8 255, i8 255>
+}
+
+define arm_aapcs_vfpcc <16 x i8> @xor_int8_64(<16 x i8> %a) {
+; CHECKLE-LABEL: xor_int8_64:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i64 q1, #0xffff00ffff0000ff
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int8_64:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i64 q1, #0xff0000ffff00ffff
+; CHECKBE-NEXT:    vrev64.8 q2, q1
+; CHECKBE-NEXT:    vrev64.8 q1, q0
+; CHECKBE-NEXT:    veor q1, q1, q2
+; CHECKBE-NEXT:    vrev64.8 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <16 x i8> %a, <i8 255, i8 0, i8 0, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 0, i8 255, i8 255, i8 0, i8 255, i8 255>
+  ret <16 x i8> %b
+}
+
 define arm_aapcs_vfpcc <8 x i16> @mov_int16_1() {
 ; CHECK-LABEL: mov_int16_1:
 ; CHECK:       @ %bb.0: @ %entry
@@ -51,6 +179,25 @@ entry:
   ret <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
 }
 
+define arm_aapcs_vfpcc <8 x i16> @xor_int16_1(<8 x i16> %a) {
+; CHECKLE-LABEL: xor_int16_1:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i16 q1, #0x1
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int16_1:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i16 q1, #0x1
+; CHECKBE-NEXT:    vrev64.16 q2, q0
+; CHECKBE-NEXT:    veor q1, q2, q1
+; CHECKBE-NEXT:    vrev64.16 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <8 x i16> %a, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %b
+}
+
 define arm_aapcs_vfpcc <8 x i16> @mov_int16_m1() {
 ; CHECK-LABEL: mov_int16_m1:
 ; CHECK:       @ %bb.0: @ %entry
@@ -60,6 +207,24 @@ entry:
   ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
 }
 
+define arm_aapcs_vfpcc <8 x i16> @xor_int16_m1(<8 x i16> %a) {
+; CHECKLE-LABEL: xor_int16_m1:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmvn q0, q0
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int16_m1:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i8 q1, #0xff
+; CHECKBE-NEXT:    vrev64.16 q2, q0
+; CHECKBE-NEXT:    veor q1, q2, q1
+; CHECKBE-NEXT:    vrev64.16 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <8 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+  ret <8 x i16> %b
+}
+
 define arm_aapcs_vfpcc <8 x i16> @mov_int16_256() {
 ; CHECK-LABEL: mov_int16_256:
 ; CHECK:       @ %bb.0: @ %entry
@@ -69,6 +234,25 @@ entry:
   ret <8 x i16> <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
 }
 
+define arm_aapcs_vfpcc <8 x i16> @xor_int16_256(<8 x i16> %a) {
+; CHECKLE-LABEL: xor_int16_256:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i16 q1, #0x100
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int16_256:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i16 q1, #0x100
+; CHECKBE-NEXT:    vrev64.16 q2, q0
+; CHECKBE-NEXT:    veor q1, q2, q1
+; CHECKBE-NEXT:    vrev64.16 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <8 x i16> %a, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
+  ret <8 x i16> %b
+}
+
 define arm_aapcs_vfpcc <8 x i16> @mov_int16_257() {
 ; CHECK-LABEL: mov_int16_257:
 ; CHECK:       @ %bb.0: @ %entry
@@ -78,6 +262,25 @@ entry:
   ret <8 x i16> <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>
 }
 
+define arm_aapcs_vfpcc <8 x i16> @xor_int16_257(<8 x i16> %a) {
+; CHECKLE-LABEL: xor_int16_257:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i8 q1, #0x1
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int16_257:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i8 q1, #0x1
+; CHECKBE-NEXT:    vrev64.16 q2, q0
+; CHECKBE-NEXT:    veor q1, q2, q1
+; CHECKBE-NEXT:    vrev64.16 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <8 x i16> %a, <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>
+  ret <8 x i16> %b
+}
+
 define arm_aapcs_vfpcc <8 x i16> @mov_int16_258() {
 ; CHECK-LABEL: mov_int16_258:
 ; CHECK:       @ %bb.0: @ %entry
@@ -88,6 +291,97 @@ entry:
   ret <8 x i16> <i16 258, i16 258, i16 258, i16 258, i16 258, i16 258, i16 258, i16 258>
 }
 
+define arm_aapcs_vfpcc <8 x i16> @xor_int16_258(<8 x i16> %a) {
+; CHECKLE-LABEL: xor_int16_258:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    mov.w r0, #258
+; CHECKLE-NEXT:    vdup.16 q1, r0
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int16_258:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    mov.w r0, #258
+; CHECKBE-NEXT:    vrev64.16 q2, q0
+; CHECKBE-NEXT:    vdup.16 q1, r0
+; CHECKBE-NEXT:    veor q1, q2, q1
+; CHECKBE-NEXT:    vrev64.16 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <8 x i16> %a, <i16 258, i16 258, i16 258, i16 258, i16 258, i16 258, i16 258, i16 258>
+  ret <8 x i16> %b
+}
+
+define arm_aapcs_vfpcc <8 x i16> @mov_int16_32() {
+; CHECKLE-LABEL: mov_int16_32:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    movw r0, #257
+; CHECKLE-NEXT:    movt r0, #256
+; CHECKLE-NEXT:    vdup.32 q0, r0
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: mov_int16_32:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    movw r0, #256
+; CHECKBE-NEXT:    movt r0, #257
+; CHECKBE-NEXT:    vdup.32 q0, r0
+; CHECKBE-NEXT:    bx lr
+entry:
+  ret <8 x i16> <i16 257, i16 256, i16 257, i16 256, i16 257, i16 256, i16 257, i16 256>
+}
+
+define arm_aapcs_vfpcc <8 x i16> @xor_int16_32(<8 x i16> %a) {
+; CHECKLE-LABEL: xor_int16_32:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    movw r0, #257
+; CHECKLE-NEXT:    movt r0, #256
+; CHECKLE-NEXT:    vdup.32 q1, r0
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int16_32:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    movw r0, #257
+; CHECKBE-NEXT:    vrev64.16 q1, q0
+; CHECKBE-NEXT:    movt r0, #256
+; CHECKBE-NEXT:    vdup.32 q0, r0
+; CHECKBE-NEXT:    veor q1, q1, q0
+; CHECKBE-NEXT:    vrev64.16 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <8 x i16> %a, <i16 257, i16 256, i16 257, i16 256, i16 257, i16 256, i16 257, i16 256>
+  ret <8 x i16> %b
+}
+
+define arm_aapcs_vfpcc <8 x i16> @mov_int16_64() {
+; CHECK-LABEL: mov_int16_64:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.i64 q0, #0xff0000000000ff
+; CHECK-NEXT:    bx lr
+entry:
+  ret <8 x i16> <i16 255, i16 0, i16 0, i16 255, i16 255, i16 0, i16 0, i16 255>
+}
+
+define arm_aapcs_vfpcc <8 x i16> @xor_int16_64(<8 x i16> %a) {
+; CHECKLE-LABEL: xor_int16_64:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i64 q1, #0xff0000000000ff
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int16_64:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i64 q1, #0xff0000000000ff
+; CHECKBE-NEXT:    vrev64.16 q2, q1
+; CHECKBE-NEXT:    vrev64.16 q1, q0
+; CHECKBE-NEXT:    veor q1, q1, q2
+; CHECKBE-NEXT:    vrev64.16 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <8 x i16> %a, <i16 255, i16 0, i16 0, i16 255, i16 255, i16 0, i16 0, i16 255>
+  ret <8 x i16> %b
+}
+
 define arm_aapcs_vfpcc <4 x i32> @mov_int32_1() {
 ; CHECK-LABEL: mov_int32_1:
 ; CHECK:       @ %bb.0: @ %entry
@@ -97,6 +391,25 @@ entry:
   ret <4 x i32> <i32 1, i32 1, i32 1, i32 1>
 }
 
+define arm_aapcs_vfpcc <4 x i32> @xor_int32_1(<4 x i32> %a) {
+; CHECKLE-LABEL: xor_int32_1:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i32 q1, #0x1
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int32_1:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i32 q1, #0x1
+; CHECKBE-NEXT:    vrev64.32 q2, q0
+; CHECKBE-NEXT:    veor q1, q2, q1
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <4 x i32> %a, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %b
+}
+
 define arm_aapcs_vfpcc <4 x i32> @mov_int32_256() {
 ; CHECK-LABEL: mov_int32_256:
 ; CHECK:       @ %bb.0: @ %entry
@@ -106,6 +419,25 @@ entry:
   ret <4 x i32> <i32 256, i32 256, i32 256, i32 256>
 }
 
+define arm_aapcs_vfpcc <4 x i32> @xor_int32_256(<4 x i32> %a) {
+; CHECKLE-LABEL: xor_int32_256:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i32 q1, #0x100
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int32_256:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i32 q1, #0x100
+; CHECKBE-NEXT:    vrev64.32 q2, q0
+; CHECKBE-NEXT:    veor q1, q2, q1
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <4 x i32> %a, <i32 256, i32 256, i32 256, i32 256>
+  ret <4 x i32> %b
+}
+
 define arm_aapcs_vfpcc <4 x i32> @mov_int32_65536() {
 ; CHECK-LABEL: mov_int32_65536:
 ; CHECK:       @ %bb.0: @ %entry
@@ -115,6 +447,25 @@ entry:
   ret <4 x i32> <i32 65536, i32 65536, i32 65536, i32 65536>
 }
 
+define arm_aapcs_vfpcc <4 x i32> @xor_int32_65536(<4 x i32> %a) {
+; CHECKLE-LABEL: xor_int32_65536:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i32 q1, #0x10000
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int32_65536:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i32 q1, #0x10000
+; CHECKBE-NEXT:    vrev64.32 q2, q0
+; CHECKBE-NEXT:    veor q1, q2, q1
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <4 x i32> %a, <i32 65536, i32 65536, i32 65536, i32 65536>
+  ret <4 x i32> %b
+}
+
 define arm_aapcs_vfpcc <4 x i32> @mov_int32_16777216() {
 ; CHECK-LABEL: mov_int32_16777216:
 ; CHECK:       @ %bb.0: @ %entry
@@ -124,6 +475,25 @@ entry:
   ret <4 x i32> <i32 16777216, i32 16777216, i32 16777216, i32 16777216>
 }
 
+define arm_aapcs_vfpcc <4 x i32> @xor_int32_16777216(<4 x i32> %a) {
+; CHECKLE-LABEL: xor_int32_16777216:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i32 q1, #0x1000000
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int32_16777216:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i32 q1, #0x1000000
+; CHECKBE-NEXT:    vrev64.32 q2, q0
+; CHECKBE-NEXT:    veor q1, q2, q1
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <4 x i32> %a, <i32 16777216, i32 16777216, i32 16777216, i32 16777216>
+  ret <4 x i32> %b
+}
+
 define arm_aapcs_vfpcc <4 x i32> @mov_int32_16777217() {
 ; CHECK-LABEL: mov_int32_16777217:
 ; CHECK:       @ %bb.0: @ %entry
@@ -135,6 +505,29 @@ entry:
   ret <4 x i32> <i32 16777217, i32 16777217, i32 16777217, i32 16777217>
 }
 
+define arm_aapcs_vfpcc <4 x i32> @xor_int32_16777217(<4 x i32> %a) {
+; CHECKLE-LABEL: xor_int32_16777217:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    movs r0, #1
+; CHECKLE-NEXT:    movt r0, #256
+; CHECKLE-NEXT:    vdup.32 q1, r0
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int32_16777217:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    movs r0, #1
+; CHECKBE-NEXT:    vrev64.32 q1, q0
+; CHECKBE-NEXT:    movt r0, #256
+; CHECKBE-NEXT:    vdup.32 q0, r0
+; CHECKBE-NEXT:    veor q1, q1, q0
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <4 x i32> %a, <i32 16777217, i32 16777217, i32 16777217, i32 16777217>
+  ret <4 x i32> %b
+}
+
 define arm_aapcs_vfpcc <4 x i32> @mov_int32_17919() {
 ; CHECK-LABEL: mov_int32_17919:
 ; CHECK:       @ %bb.0: @ %entry
@@ -144,6 +537,25 @@ entry:
   ret <4 x i32> <i32 17919, i32 17919, i32 17919, i32 17919>
 }
 
+define arm_aapcs_vfpcc <4 x i32> @xor_int32_17919(<4 x i32> %a) {
+; CHECKLE-LABEL: xor_int32_17919:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i32 q1, #0x45ff
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int32_17919:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i32 q1, #0x45ff
+; CHECKBE-NEXT:    vrev64.32 q2, q0
+; CHECKBE-NEXT:    veor q1, q2, q1
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <4 x i32> %a, <i32 17919, i32 17919, i32 17919, i32 17919>
+  ret <4 x i32> %b
+}
+
 define arm_aapcs_vfpcc <4 x i32> @mov_int32_4587519() {
 ; CHECK-LABEL: mov_int32_4587519:
 ; CHECK:       @ %bb.0: @ %entry
@@ -153,6 +565,25 @@ entry:
   ret <4 x i32> <i32 4587519, i32 4587519, i32 4587519, i32 4587519>
 }
 
+define arm_aapcs_vfpcc <4 x i32> @xor_int32_4587519(<4 x i32> %a) {
+; CHECKLE-LABEL: xor_int32_4587519:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i32 q1, #0x45ffff
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int32_4587519:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i32 q1, #0x45ffff
+; CHECKBE-NEXT:    vrev64.32 q2, q0
+; CHECKBE-NEXT:    veor q1, q2, q1
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <4 x i32> %a, <i32 4587519, i32 4587519, i32 4587519, i32 4587519>
+  ret <4 x i32> %b
+}
+
 define arm_aapcs_vfpcc <4 x i32> @mov_int32_m1() {
 ; CHECK-LABEL: mov_int32_m1:
 ; CHECK:       @ %bb.0: @ %entry
@@ -162,6 +593,24 @@ entry:
   ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
 }
 
+define arm_aapcs_vfpcc <4 x i32> @xor_int32_m1(<4 x i32> %a) {
+; CHECKLE-LABEL: xor_int32_m1:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmvn q0, q0
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int32_m1:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i8 q1, #0xff
+; CHECKBE-NEXT:    vrev64.32 q2, q0
+; CHECKBE-NEXT:    veor q1, q2, q1
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
+  ret <4 x i32> %b
+}
+
 define arm_aapcs_vfpcc <4 x i32> @mov_int32_4294901760() {
 ; CHECK-LABEL: mov_int32_4294901760:
 ; CHECK:       @ %bb.0: @ %entry
@@ -171,6 +620,25 @@ entry:
   ret <4 x i32> <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
 }
 
+define arm_aapcs_vfpcc <4 x i32> @xor_int32_4294901760(<4 x i32> %a) {
+; CHECKLE-LABEL: xor_int32_4294901760:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmvn.i32 q1, #0xffff
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int32_4294901760:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmvn.i32 q1, #0xffff
+; CHECKBE-NEXT:    vrev64.32 q2, q0
+; CHECKBE-NEXT:    veor q1, q2, q1
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <4 x i32> %a, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
+  ret <4 x i32> %b
+}
+
 define arm_aapcs_vfpcc <4 x i32> @mov_int32_4278190335() {
 ; CHECK-LABEL: mov_int32_4278190335:
 ; CHECK:       @ %bb.0: @ %entry
@@ -182,6 +650,29 @@ entry:
   ret <4 x i32> <i32 4278190335, i32 4278190335, i32 4278190335, i32 4278190335>
 }
 
+define arm_aapcs_vfpcc <4 x i32> @xor_int32_4278190335(<4 x i32> %a) {
+; CHECKLE-LABEL: xor_int32_4278190335:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    movs r0, #255
+; CHECKLE-NEXT:    movt r0, #65280
+; CHECKLE-NEXT:    vdup.32 q1, r0
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int32_4278190335:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    movs r0, #255
+; CHECKBE-NEXT:    vrev64.32 q1, q0
+; CHECKBE-NEXT:    movt r0, #65280
+; CHECKBE-NEXT:    vdup.32 q0, r0
+; CHECKBE-NEXT:    veor q1, q1, q0
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <4 x i32> %a, <i32 4278190335, i32 4278190335, i32 4278190335, i32 4278190335>
+  ret <4 x i32> %b
+}
+
 define arm_aapcs_vfpcc <4 x i32> @mov_int32_4278255615() {
 ; CHECK-LABEL: mov_int32_4278255615:
 ; CHECK:       @ %bb.0: @ %entry
@@ -191,6 +682,25 @@ entry:
   ret <4 x i32> <i32 4278255615, i32 4278255615, i32 4278255615, i32 4278255615>
 }
 
+define arm_aapcs_vfpcc <4 x i32> @xor_int32_4278255615(<4 x i32> %a) {
+; CHECKLE-LABEL: xor_int32_4278255615:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmvn.i32 q1, #0xff0000
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int32_4278255615:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmvn.i32 q1, #0xff0000
+; CHECKBE-NEXT:    vrev64.32 q2, q0
+; CHECKBE-NEXT:    veor q1, q2, q1
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <4 x i32> %a, <i32 4278255615, i32 4278255615, i32 4278255615, i32 4278255615>
+  ret <4 x i32> %b
+}
+
 define arm_aapcs_vfpcc <4 x i32> @mov_int32_16908546() {
 ; CHECK-LABEL: mov_int32_16908546:
 ; CHECK:       @ %bb.0: @ %entry
@@ -201,15 +711,70 @@ entry:
   ret <4 x i32> <i32 16908546, i32 16908546, i32 16908546, i32 16908546>
 }
 
+define arm_aapcs_vfpcc <4 x i32> @xor_int32_16908546(<4 x i32> %a) {
+; CHECKLE-LABEL: xor_int32_16908546:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    mov.w r0, #258
+; CHECKLE-NEXT:    vdup.16 q1, r0
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int32_16908546:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    mov.w r0, #258
+; CHECKBE-NEXT:    vrev64.32 q2, q0
+; CHECKBE-NEXT:    vdup.16 q1, r0
+; CHECKBE-NEXT:    veor q1, q2, q1
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <4 x i32> %a, <i32 16908546, i32 16908546, i32 16908546, i32 16908546>
+  ret <4 x i32> %b
+}
+
+define arm_aapcs_vfpcc <4 x i32> @mov_int32_64() {
+; CHECKLE-LABEL: mov_int32_64:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i64 q0, #0xff00ffff00ff00
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: mov_int32_64:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i64 q0, #0xff00ff0000ff00ff
+; CHECKBE-NEXT:    bx lr
+entry:
+  ret <4 x i32> <i32 u0xff00ff00, i32 u0x00ff00ff, i32 u0xff00ff00, i32 u0x00ff00ff>
+}
+
+define arm_aapcs_vfpcc <4 x i32> @xor_int32_64(<4 x i32> %a) {
+; CHECKLE-LABEL: xor_int32_64:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i64 q1, #0xff00ffff00ff00
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int32_64:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i64 q1, #0xff00ff0000ff00ff
+; CHECKBE-NEXT:    vrev64.32 q2, q1
+; CHECKBE-NEXT:    vrev64.32 q1, q0
+; CHECKBE-NEXT:    veor q1, q1, q2
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <4 x i32> %a, <i32 u0xff00ff00, i32 u0x00ff00ff, i32 u0xff00ff00, i32 u0x00ff00ff>
+  ret <4 x i32> %b
+}
+
 define arm_aapcs_vfpcc <2 x i64> @mov_int64_1() {
 ; CHECKLE-LABEL: mov_int64_1:
 ; CHECKLE:       @ %bb.0: @ %entry
-; CHECKLE-NEXT:    adr r0, .LCPI20_0
+; CHECKLE-NEXT:    adr r0, .LCPI50_0
 ; CHECKLE-NEXT:    vldrw.u32 q0, [r0]
 ; CHECKLE-NEXT:    bx lr
 ; CHECKLE-NEXT:    .p2align 4
 ; CHECKLE-NEXT:  @ %bb.1:
-; CHECKLE-NEXT:  .LCPI20_0:
+; CHECKLE-NEXT:  .LCPI50_0:
 ; CHECKLE-NEXT:    .long 1 @ double 4.9406564584124654E-324
 ; CHECKLE-NEXT:    .long 0
 ; CHECKLE-NEXT:    .long 1 @ double 4.9406564584124654E-324
@@ -217,13 +782,13 @@ define arm_aapcs_vfpcc <2 x i64> @mov_int64_1() {
 ;
 ; CHECKBE-LABEL: mov_int64_1:
 ; CHECKBE:       @ %bb.0: @ %entry
-; CHECKBE-NEXT:    adr r0, .LCPI20_0
+; CHECKBE-NEXT:    adr r0, .LCPI50_0
 ; CHECKBE-NEXT:    vldrb.u8 q1, [r0]
 ; CHECKBE-NEXT:    vrev64.8 q0, q1
 ; CHECKBE-NEXT:    bx lr
 ; CHECKBE-NEXT:    .p2align 4
 ; CHECKBE-NEXT:  @ %bb.1:
-; CHECKBE-NEXT:  .LCPI20_0:
+; CHECKBE-NEXT:  .LCPI50_0:
 ; CHECKBE-NEXT:    .long 0 @ double 4.9406564584124654E-324
 ; CHECKBE-NEXT:    .long 1
 ; CHECKBE-NEXT:    .long 0 @ double 4.9406564584124654E-324
@@ -232,13 +797,58 @@ entry:
   ret <2 x i64> <i64 1, i64 1>
 }
 
+define arm_aapcs_vfpcc <2 x i64> @xor_int64_1(<2 x i64> %a) {
+; CHECKLE-LABEL: xor_int64_1:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    adr r0, .LCPI51_0
+; CHECKLE-NEXT:    vldrw.u32 q1, [r0]
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+; CHECKLE-NEXT:    .p2align 4
+; CHECKLE-NEXT:  @ %bb.1:
+; CHECKLE-NEXT:  .LCPI51_0:
+; CHECKLE-NEXT:    .long 1 @ 0x1
+; CHECKLE-NEXT:    .long 0 @ 0x0
+; CHECKLE-NEXT:    .long 1 @ 0x1
+; CHECKLE-NEXT:    .long 0 @ 0x0
+;
+; CHECKBE-LABEL: xor_int64_1:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    adr r0, .LCPI51_0
+; CHECKBE-NEXT:    vldrb.u8 q1, [r0]
+; CHECKBE-NEXT:    vrev64.8 q2, q1
+; CHECKBE-NEXT:    veor q0, q0, q2
+; CHECKBE-NEXT:    bx lr
+; CHECKBE-NEXT:    .p2align 4
+; CHECKBE-NEXT:  @ %bb.1:
+; CHECKBE-NEXT:  .LCPI51_0:
+; CHECKBE-NEXT:    .long 0 @ 0x0
+; CHECKBE-NEXT:    .long 1 @ 0x1
+; CHECKBE-NEXT:    .long 0 @ 0x0
+; CHECKBE-NEXT:    .long 1 @ 0x1
+entry:
+  %b = xor <2 x i64> %a, <i64 1, i64 1>
+  ret <2 x i64> %b
+}
+
 define arm_aapcs_vfpcc <2 x i64> @mov_int64_ff() {
 ; CHECK-LABEL: mov_int64_ff:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmov.i64 q0, #0xff
 ; CHECK-NEXT:    bx lr
 entry:
-  ret <2 x i64> < i64 255, i64 255 >
+  ret <2 x i64> <i64 255, i64 255>
+}
+
+define arm_aapcs_vfpcc <2 x i64> @xor_int64_ff(<2 x i64> %a) {
+; CHECK-LABEL: xor_int64_ff:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.i64 q1, #0xff
+; CHECK-NEXT:    veor q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %b = xor <2 x i64> %a, <i64 255, i64 255>
+  ret <2 x i64> %b
 }
 
 define arm_aapcs_vfpcc <2 x i64> @mov_int64_m1() {
@@ -247,7 +857,23 @@ define arm_aapcs_vfpcc <2 x i64> @mov_int64_m1() {
 ; CHECK-NEXT:    vmov.i8 q0, #0xff
 ; CHECK-NEXT:    bx lr
 entry:
-  ret <2 x i64> < i64 -1, i64 -1 >
+  ret <2 x i64> <i64 -1, i64 -1>
+}
+
+define arm_aapcs_vfpcc <2 x i64> @xor_int64_m1(<2 x i64> %a) {
+; CHECKLE-LABEL: xor_int64_m1:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmvn q0, q0
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int64_m1:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i8 q1, #0xff
+; CHECKBE-NEXT:    veor q0, q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <2 x i64> %a, <i64 -1, i64 -1>
+  ret <2 x i64> %b
 }
 
 define arm_aapcs_vfpcc <2 x i64> @mov_int64_ff0000ff0000ffff() {
@@ -256,18 +882,29 @@ define arm_aapcs_vfpcc <2 x i64> @mov_int64_ff0000ff0000ffff() {
 ; CHECK-NEXT:    vmov.i64 q0, #0xff0000ff0000ffff
 ; CHECK-NEXT:    bx lr
 entry:
-  ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
+  ret <2 x i64> <i64 18374687574888349695, i64 18374687574888349695>
+}
+
+define arm_aapcs_vfpcc <2 x i64> @xor_int64_ff0000ff0000ffff(<2 x i64> %a) {
+; CHECK-LABEL: xor_int64_ff0000ff0000ffff:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmov.i64 q1, #0xff0000ff0000ffff
+; CHECK-NEXT:    veor q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %b = xor <2 x i64> %a, <i64 18374687574888349695, i64 18374687574888349695>
+  ret <2 x i64> %b
 }
 
 define arm_aapcs_vfpcc <2 x i64> @mov_int64_f_0() {
 ; CHECKLE-LABEL: mov_int64_f_0:
 ; CHECKLE:       @ %bb.0: @ %entry
-; CHECKLE-NEXT:    adr r0, .LCPI24_0
+; CHECKLE-NEXT:    adr r0, .LCPI58_0
 ; CHECKLE-NEXT:    vldrw.u32 q0, [r0]
 ; CHECKLE-NEXT:    bx lr
 ; CHECKLE-NEXT:    .p2align 4
 ; CHECKLE-NEXT:  @ %bb.1:
-; CHECKLE-NEXT:  .LCPI24_0:
+; CHECKLE-NEXT:  .LCPI58_0:
 ; CHECKLE-NEXT:    .long 255 @ double 1.2598673968951787E-321
 ; CHECKLE-NEXT:    .long 0
 ; CHECKLE-NEXT:    .long 0 @ double 0
@@ -275,19 +912,53 @@ define arm_aapcs_vfpcc <2 x i64> @mov_int64_f_0() {
 ;
 ; CHECKBE-LABEL: mov_int64_f_0:
 ; CHECKBE:       @ %bb.0: @ %entry
-; CHECKBE-NEXT:    adr r0, .LCPI24_0
+; CHECKBE-NEXT:    adr r0, .LCPI58_0
 ; CHECKBE-NEXT:    vldrb.u8 q1, [r0]
 ; CHECKBE-NEXT:    vrev64.8 q0, q1
 ; CHECKBE-NEXT:    bx lr
 ; CHECKBE-NEXT:    .p2align 4
 ; CHECKBE-NEXT:  @ %bb.1:
-; CHECKBE-NEXT:  .LCPI24_0:
+; CHECKBE-NEXT:  .LCPI58_0:
 ; CHECKBE-NEXT:    .long 0 @ double 1.2598673968951787E-321
 ; CHECKBE-NEXT:    .long 255
 ; CHECKBE-NEXT:    .long 0 @ double 0
 ; CHECKBE-NEXT:    .long 0
 entry:
-  ret <2 x i64> < i64 255, i64 0 >
+  ret <2 x i64> <i64 255, i64 0>
+}
+
+define arm_aapcs_vfpcc <2 x i64> @xor_int64_f_0(<2 x i64> %a) {
+; CHECKLE-LABEL: xor_int64_f_0:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    adr r0, .LCPI59_0
+; CHECKLE-NEXT:    vldrw.u32 q1, [r0]
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+; CHECKLE-NEXT:    .p2align 4
+; CHECKLE-NEXT:  @ %bb.1:
+; CHECKLE-NEXT:  .LCPI59_0:
+; CHECKLE-NEXT:    .long 255 @ 0xff
+; CHECKLE-NEXT:    .long 0 @ 0x0
+; CHECKLE-NEXT:    .long 0 @ 0x0
+; CHECKLE-NEXT:    .long 0 @ 0x0
+;
+; CHECKBE-LABEL: xor_int64_f_0:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    adr r0, .LCPI59_0
+; CHECKBE-NEXT:    vldrb.u8 q1, [r0]
+; CHECKBE-NEXT:    vrev64.8 q2, q1
+; CHECKBE-NEXT:    veor q0, q0, q2
+; CHECKBE-NEXT:    bx lr
+; CHECKBE-NEXT:    .p2align 4
+; CHECKBE-NEXT:  @ %bb.1:
+; CHECKBE-NEXT:  .LCPI59_0:
+; CHECKBE-NEXT:    .long 0 @ 0x0
+; CHECKBE-NEXT:    .long 255 @ 0xff
+; CHECKBE-NEXT:    .long 0 @ 0x0
+; CHECKBE-NEXT:    .long 0 @ 0x0
+entry:
+  %b = xor <2 x i64> %a, <i64 255, i64 0>
+  ret <2 x i64> %b
 }
 
 define arm_aapcs_vfpcc <16 x i8> @mov_int64_0f000f0f() {
@@ -304,6 +975,26 @@ entry:
   ret <16 x i8> <i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0>
 }
 
+define arm_aapcs_vfpcc <16 x i8> @xor_int64_0f000f0f(<16 x i8> %a) {
+; CHECKLE-LABEL: xor_int64_0f000f0f:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i64 q1, #0xff000000ff00ff
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int64_0f000f0f:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i64 q1, #0xff00ff000000ff00
+; CHECKBE-NEXT:    vrev64.8 q2, q1
+; CHECKBE-NEXT:    vrev64.8 q1, q0
+; CHECKBE-NEXT:    veor q1, q1, q2
+; CHECKBE-NEXT:    vrev64.8 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <16 x i8> %a, <i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0>
+  ret <16 x i8> %b
+}
+
 define arm_aapcs_vfpcc <8 x i16> @mov_int64_ff00ffff() {
 ; CHECKLE-LABEL: mov_int64_ff00ffff:
 ; CHECKLE:       @ %bb.0: @ %entry
@@ -318,6 +1009,26 @@ entry:
   ret <8 x i16> <i16 -1, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1>
 }
 
+define arm_aapcs_vfpcc <8 x i16> @xor_int64_ff00ffff(<8 x i16> %a) {
+; CHECKLE-LABEL: xor_int64_ff00ffff:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i64 q1, #0xffffffff0000ffff
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int64_ff00ffff:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i64 q1, #0xffff0000ffffffff
+; CHECKBE-NEXT:    vrev64.16 q2, q1
+; CHECKBE-NEXT:    vrev64.16 q1, q0
+; CHECKBE-NEXT:    veor q1, q1, q2
+; CHECKBE-NEXT:    vrev64.16 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <8 x i16> %a, <i16 -1, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1>
+  ret <8 x i16> %b
+}
+
 define arm_aapcs_vfpcc <16 x i8> @mov_int64_0f0f0f0f0f0f0f0f() {
 ; CHECKLE-LABEL: mov_int64_0f0f0f0f0f0f0f0f:
 ; CHECKLE:       @ %bb.0: @ %entry
@@ -332,6 +1043,27 @@ entry:
   ret <16 x i8> <i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0>
 }
 
+; FIXME: This is incorrect for BE
+define arm_aapcs_vfpcc <16 x i8> @xor_int64_0f0f0f0f0f0f0f0f(<16 x i8> %a) {
+; CHECKLE-LABEL: xor_int64_0f0f0f0f0f0f0f0f:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    vmov.i16 q1, #0xff
+; CHECKLE-NEXT:    veor q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: xor_int64_0f0f0f0f0f0f0f0f:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i16 q1, #0xff
+; CHECKBE-NEXT:    vrev64.8 q2, q0
+; CHECKBE-NEXT:    vrev16.8 q1, q1
+; CHECKBE-NEXT:    veor q1, q2, q1
+; CHECKBE-NEXT:    vrev64.8 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = xor <16 x i8> %a, <i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0>
+  ret <16 x i8> %b
+}
+
 define arm_aapcs_vfpcc <4 x float> @mov_float_1() {
 ; CHECK-LABEL: mov_float_1:
 ; CHECK:       @ %bb.0: @ %entry
@@ -342,6 +1074,19 @@ entry:
   ret <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
 }
 
+define arm_aapcs_vfpcc <4 x float> @fadd_float_1(<4 x float> %a) {
+; CHECKBE-LABEL: fadd_float_1:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.f32 q1, #1.000000e+00
+; CHECKBE-NEXT:    vrev64.32 q2, q0
+; CHECKBE-NEXT:    vadd.f32 q1, q2, q1
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = fadd <4 x float> %a, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
+  ret <4 x float> %b
+}
+
 define arm_aapcs_vfpcc <4 x float> @mov_float_m3() {
 ; CHECK-LABEL: mov_float_m3:
 ; CHECK:       @ %bb.0: @ %entry
@@ -353,35 +1098,72 @@ entry:
   ret <4 x float> <float -3.000000e+00, float -3.000000e+00, float -3.000000e+00, float -3.000000e+00>
 }
 
+define arm_aapcs_vfpcc <4 x float> @fadd_float_m3(<4 x float> %a) {
+; CHECKBE-LABEL: fadd_float_m3:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.f32 q1, #-3.000000e+00
+; CHECKBE-NEXT:    vrev64.32 q2, q0
+; CHECKBE-NEXT:    vadd.f32 q1, q2, q1
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = fadd <4 x float> %a, <float -3.000000e+00, float -3.000000e+00, float -3.000000e+00, float -3.000000e+00>
+  ret <4 x float> %b
+}
+
 define arm_aapcs_vfpcc <8 x half> @mov_float16_1() {
 ; CHECK-LABEL: mov_float16_1:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmov.i16 q0, #0x3c00
 ; CHECK-NEXT:    bx lr
-
 entry:
   ret <8 x half> <half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00>
 }
 
+define arm_aapcs_vfpcc <8 x half> @fadd_float16_1(<8 x half> %a) {
+; CHECKBE-LABEL: fadd_float16_1:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i16 q1, #0x3c00
+; CHECKBE-NEXT:    vrev64.16 q2, q0
+; CHECKBE-NEXT:    vadd.f16 q1, q2, q1
+; CHECKBE-NEXT:    vrev64.16 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = fadd <8 x half> %a, <half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00, half 1.000000e+00>
+  ret <8 x half> %b
+}
+
 define arm_aapcs_vfpcc <8 x half> @mov_float16_m3() {
 ; CHECK-LABEL: mov_float16_m3:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vmov.i16 q0, #0xc200
 ; CHECK-NEXT:    bx lr
-
 entry:
   ret <8 x half> <half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00>
 }
 
+define arm_aapcs_vfpcc <8 x half> @fadd_float16_m3(<8 x half> %a) {
+; CHECKBE-LABEL: fadd_float16_m3:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    vmov.i16 q1, #0xc200
+; CHECKBE-NEXT:    vrev64.16 q2, q0
+; CHECKBE-NEXT:    vadd.f16 q1, q2, q1
+; CHECKBE-NEXT:    vrev64.16 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %b = fadd <8 x half> %a, <half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00, half -3.000000e+00>
+  ret <8 x half> %b
+}
+
 define arm_aapcs_vfpcc <2 x double> @mov_double_1() {
 ; CHECKLE-LABEL: mov_double_1:
 ; CHECKLE:       @ %bb.0: @ %entry
-; CHECKLE-NEXT:    adr r0, .LCPI32_0
+; CHECKLE-NEXT:    adr r0, .LCPI74_0
 ; CHECKLE-NEXT:    vldrw.u32 q0, [r0]
 ; CHECKLE-NEXT:    bx lr
 ; CHECKLE-NEXT:    .p2align 4
 ; CHECKLE-NEXT:  @ %bb.1:
-; CHECKLE-NEXT:  .LCPI32_0:
+; CHECKLE-NEXT:  .LCPI74_0:
 ; CHECKLE-NEXT:    .long 0 @ double 1
 ; CHECKLE-NEXT:    .long 1072693248
 ; CHECKLE-NEXT:    .long 0 @ double 1
@@ -389,13 +1171,13 @@ define arm_aapcs_vfpcc <2 x double> @mov_double_1() {
 ;
 ; CHECKBE-LABEL: mov_double_1:
 ; CHECKBE:       @ %bb.0: @ %entry
-; CHECKBE-NEXT:    adr r0, .LCPI32_0
+; CHECKBE-NEXT:    adr r0, .LCPI74_0
 ; CHECKBE-NEXT:    vldrb.u8 q1, [r0]
 ; CHECKBE-NEXT:    vrev64.8 q0, q1
 ; CHECKBE-NEXT:    bx lr
 ; CHECKBE-NEXT:    .p2align 4
 ; CHECKBE-NEXT:  @ %bb.1:
-; CHECKBE-NEXT:  .LCPI32_0:
+; CHECKBE-NEXT:  .LCPI74_0:
 ; CHECKBE-NEXT:    .long 1072693248 @ double 1
 ; CHECKBE-NEXT:    .long 0
 ; CHECKBE-NEXT:    .long 1072693248 @ double 1