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Handle interrupt acknowledge register in Cortex-A53 SRE port #392

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sviaunxp
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Description

Let the FreeRTOS IRQ handler properly store and restore the ICCIAR register value around the vApplicationIRQHandler() call.

This pull request is essentially created so that the "SRE" port matches the original ("MMIO") port [1] so that vApplicationIRQHandler() does not depend on the port being used.

[1] https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/portable/GCC/ARM_CA53_64_BIT/portASM.S#L310

Test Steps

Tested with an application - with the same implementation of vApplicationIRQHandler() - for both A53 ports.

By submitting this pull request, I confirm that you can use, modify, copy, and redistribute this contribution, under the terms of your choice.

Let the FreeRTOS IRQ handler properly store and restore the ICCIAR
register value around the vApplicationIRQHandler() call.

Signed-off-by: Stephane Viau <stephane.viau@oss.nxp.com>
@sviaunxp sviaunxp requested a review from a team as a code owner September 12, 2021 20:46
@aggarg
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aggarg commented Sep 12, 2021

Whether to use ICC_IAR1_EL1 and ICC_IAR0_EL1 depends on whether the interrupt being handled is configured as Group 1 or Group 0 interrupt. This information is best known to the application and therefore, the application interrupt handler should acknowledge and mark completion of the interrupt. What do you think?

@sviaunxp
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sviaunxp commented Sep 13, 2021

Group 0 interrupts are always signaled as FIQs [2].
Since we are in FreeRTOS_IRQ_Handler(), we are only handling IRQs (as opposed to FIQs).
Hence, there is no reason to access ICC_IAR0_EL1 here, IMO.

[2] https://developer.arm.com/documentation/198123/0300/Arm-CoreLink-GIC-fundamentals

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Codecov Report

Merging #392 (0949268) into main (a030d0a) will not change coverage.
The diff coverage is n/a.

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@@           Coverage Diff           @@
##             main     #392   +/-   ##
=======================================
  Coverage   92.13%   92.13%           
=======================================
  Files           4        4           
  Lines        1272     1272           
  Branches      342      342           
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  Hits         1172     1172           
  Misses         53       53           
  Partials       47       47           
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@sviaunxp
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Hi @aggarg
Any feedback on this?
We should at least align both implementations of the Cortex-A53 ports in order to run the same application seamlessly on one or the other...

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aggarg commented Sep 27, 2021

Hi @sviaunxp , Apologies for missing your earlier reply. You are right that Group 0 interrupts are always signaled as FIQs. Though, in its current form, the same function can be used as both IRQ and FIQ handler? What is your motivation to do these operations in the port layer?

My motivation was to keep the interrupt grouping information out of the port layer. Let me check with others in my team and get back to you.

Thanks.

@sviaunxp
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Hi @aggarg ,

Thank you for your response.

My motivation is the following:

  1. keep the application's IRQ handler as simple as possible
    (assuming FreeRTOS_IRQ_Handler() is only used to handle IRQs)
  2. keep the SRE port behavior similar to the original one ("MMIO" based) in order to keep consistency across both ports.
    (hence have the same application handler to work seamlessly on either)

Feel free to touch base with your team and get back to me when you can.

@sviaunxp
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Hi @aggarg,
Have you got a chance to discuss this internally?

Thank you for your feedback.

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aggarg commented Oct 11, 2021

Hi @sviaunxp,

Yes and we decided to take this change. I will test it and merge it soon. Thank you for your contribution.

-Gaurav

@sviaunxp
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Hi Gaurav,

Thank you for accepting and testing this patch.
Don't hesitate to get back to me if ever you see regressions.

BR,
Stéphane.

@aggarg aggarg merged commit 68ddb32 into FreeRTOS:main Oct 15, 2021
dawood87 added a commit to dawood87/FreeRTOS-Kernel that referenced this pull request Oct 19, 2021
commit 6ab51bb
Author: dawood87 <asifdawood@ethwal.com>
Date:   Tue Oct 19 14:32:34 2021 +0200

    Squashed commit of the following:

    commit d649a77
    Author: Archit Gupta <71798289+archigup@users.noreply.github.com>
    Date:   Sat Oct 16 16:36:44 2021 -0700

        Fix prvWriteMessageToBuffer on big endian (FreeRTOS#391)

        prvWriteMessageToBuffer wrote the first sbBYTES_TO_STORE_MESSAGE_LENGTH
        bytes of the size_t-typed length to the buffer as the data length. While
        this functions on little endian, it copies the wrong bytes on big
        endian. This fix converts the length to configMESSAGE_BUFFER_LENGTH_TYPE
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        Additionally it adds an assert to verify the size is not greater than
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        Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

    commit 06fb777
    Author: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
    Date:   Sat Oct 16 13:45:03 2021 -0700

        Update comments for the ARM_CA53_64_BIT_SRE port (FreeRTOS#403)

        Mention that FreeRTOS_IRQ_Handler should not be used for FIQs and the
        reason for assuming Group 1 for Interrupt Acknowledge and End Of
        Interrupt registers.

        Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

    commit 68ddb32
    Author: Stephane Viau <84857962+sviaunxp@users.noreply.github.com>
    Date:   Fri Oct 15 18:21:56 2021 +0200

        Handle interrupt acknowledge register in Cortex-A53 SRE port (FreeRTOS#392)

        Let the FreeRTOS IRQ handler properly store and restore the ICCIAR
        register value around the vApplicationIRQHandler() call.

        Signed-off-by: Stephane Viau <stephane.viau@oss.nxp.com>

        Co-authored-by: Stephane Viau <stephane.viau@oss.nxp.com>
        Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

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    Author: swaldhoer <34184299+swaldhoer@users.noreply.github.com>
    Date:   Thu Oct 7 00:32:07 2021 +0200

        fix typo (FreeRTOS#399)

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Date:   Tue Oct 19 14:32:04 2021 +0200

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    Merge: 14fddf1 763f1b8
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            Fix the defect that Heap_1.c may waste first portBYTE_ALIGNMENT bytes of ucHeap[] (FreeRTOS#238)

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        commit 99a5a5f
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            * uncrustify with github workflows

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            * Add uncrustify configuration file

            * Uncrustify some files

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            * Use cast to fix warnings.

            * Remove all empty definitions of portCLEAN_UP_TCB( pxTCB ) and
              portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) from ports.
              When these are undefined, the default empty definition is defined
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    Date:   Fri Jun 18 15:48:24 2021 +0000

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    Date:   Wed Jun 9 11:32:17 2021 +0000

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        See FreeRTOS#347

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    Merge: f31a1ac 1d86b97
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    Date:   Sat Jul 17 13:32:47 2021 +0200

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    Date:   Fri Jun 18 15:48:24 2021 +0000

        Change ucHeap[] To Pointer Type

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    Merge: 0780328 6a84f2c
    Author: Lasse Fröhner <finwood@posteo.de>
    Date:   Sat Jun 12 14:56:18 2021 +0200

        Merge branch 'main' into 347-omit-size-in-extern-uint8t-ucHeap

    commit 0780328
    Merge: d687545 bad8f01
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    Date:   Thu Jun 10 23:26:09 2021 +0200

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    Author: Lasse Fröhner <lasse@starcopter.com>
    Date:   Wed Jun 9 11:32:17 2021 +0000

        Omit configTOTAL_HEAP_SIZE with Application Allocated Heap

        See FreeRTOS#347
dawood87 added a commit to dawood87/FreeRTOS-Kernel that referenced this pull request Oct 19, 2021
commit d649a77
Author: Archit Gupta <71798289+archigup@users.noreply.github.com>
Date:   Sat Oct 16 16:36:44 2021 -0700

    Fix prvWriteMessageToBuffer on big endian (FreeRTOS#391)

    prvWriteMessageToBuffer wrote the first sbBYTES_TO_STORE_MESSAGE_LENGTH
    bytes of the size_t-typed length to the buffer as the data length. While
    this functions on little endian, it copies the wrong bytes on big
    endian. This fix converts the length to configMESSAGE_BUFFER_LENGTH_TYPE
    first, and then copies the exact amount, thus fixing the issue.
    Additionally it adds an assert to verify the size is not greater than
    the max value of configMESSAGE_BUFFER_LENGTH_TYPE; previously this would
    truncate silently.

    Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

commit 06fb777
Author: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
Date:   Sat Oct 16 13:45:03 2021 -0700

    Update comments for the ARM_CA53_64_BIT_SRE port (FreeRTOS#403)

    Mention that FreeRTOS_IRQ_Handler should not be used for FIQs and the
    reason for assuming Group 1 for Interrupt Acknowledge and End Of
    Interrupt registers.

    Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

commit 68ddb32
Author: Stephane Viau <84857962+sviaunxp@users.noreply.github.com>
Date:   Fri Oct 15 18:21:56 2021 +0200

    Handle interrupt acknowledge register in Cortex-A53 SRE port (FreeRTOS#392)

    Let the FreeRTOS IRQ handler properly store and restore the ICCIAR
    register value around the vApplicationIRQHandler() call.

    Signed-off-by: Stephane Viau <stephane.viau@oss.nxp.com>

    Co-authored-by: Stephane Viau <stephane.viau@oss.nxp.com>
    Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

commit a030d0a
Author: swaldhoer <34184299+swaldhoer@users.noreply.github.com>
Date:   Thu Oct 7 00:32:07 2021 +0200

    fix typo (FreeRTOS#399)
sviaunxp added a commit to nxp-mcuxpresso/FreeRTOS-Kernel that referenced this pull request Dec 16, 2021
…S#392)

Let the FreeRTOS IRQ handler properly store and restore the ICCIAR
register value around the vApplicationIRQHandler() call.

Signed-off-by: Stephane Viau <stephane.viau@oss.nxp.com>

Co-authored-by: Stephane Viau <stephane.viau@oss.nxp.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
(cherry picked from commit 68ddb32)
laroche pushed a commit to laroche/FreeRTOS-Kernel that referenced this pull request Apr 18, 2024
* Fix wrong comments in shadow_demo_helpers.c

* Fix file brief description in shadow_demo_helpers.c

* Revise the comment for democonfigMQTT_BROKER_ENDPOINT
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4 participants