Add Cortex-A53 port with system register interface for CPU interface access #357
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…access The difference between this port and portable/GCC/ARM_CA53_64_BIT is that this port uses System Register interface to access CPU interface while the other one uses Memory-mapped interface. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
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Coverage 92.13% 92.13%
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Files 4 4
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Branches 342 342
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Misses 53 53
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cobusve
approved these changes
Jun 22, 2021
RichardBarry
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Jun 23, 2021
sviaunxp
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Dec 16, 2021
…access (FreeRTOS#357) The difference between this port and portable/GCC/ARM_CA53_64_BIT is that this port uses System Register interface to access CPU interface while the other one uses Memory-mapped interface. Signed-off-by: Gaurav Aggarwal Co-authored-by: Cobus van Eeden <35851496+cobusve@users.noreply.github.com> (cherry picked from commit 4e3bf0f)
laroche
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to laroche/FreeRTOS-Kernel
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Apr 18, 2024
…rmal parameter (FreeRTOS#357) Fixes build warnings by making the following changes: - Add header file for snprintf to prevent building warning in Visual Studio. - Add for compiler warning about unused parameters.
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Description
The difference between this port and the
portable/GCC/ARM_CA53_64_BITis that this port uses System Register interface to access CPU interface while the other one uses Memory-mapped interface.By submitting this pull request, I confirm that you can use, modify, copy, and redistribute this contribution, under the terms of your choice.