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Ahmed IsmailAhmedIsmail02
Ahmed Ismail
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AhmedIsmail02
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armv8.1-m: Add PACBTI support to kernel non-secure implementation
In this commit, Pointer Authentication, and Branch Target Identification Extension (PACBTI) support is added for Non-Secure and Non-TrustZone variants of Cortex-M85 FreeRTOS-Kernel Port. The PACBTI support is added for Arm Compiler For Embedded, and IAR toolchains only. The support in the kernel is not yet enabled for GNU toolchain due to known issues. Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
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‎.github/.cSpellWords.txt

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@@ -448,6 +448,7 @@ MAINRDY
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MAIR
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Mang
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Mbits
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mbranch
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mcause
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MCFR
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MCKA
@@ -586,6 +587,8 @@ OWATCOM
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OWDR
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OWER
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OWSR
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pacbti
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PACBTI
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PAGEN
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PCDR
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PCER
@@ -900,6 +903,7 @@ TXTEN
900903
TXUBR
901904
TXVC
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TXVDIS
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UBTI
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UDCP
904908
UNACKED
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uncrustify
@@ -915,6 +919,7 @@ UNSUB
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UNSUBACK
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unsubscriptions
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unsuspended
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UPAC
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URAD
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URAT
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URSTEN

‎include/FreeRTOS.h

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@@ -3032,6 +3032,18 @@
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#define configCONTROL_INFINITE_LOOP()
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#endif
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3035+
/* Set configENABLE_PAC and/or configENABLE_BTI to 1 to enable PAC and/or BTI
3036+
* support and 0 to disable them. These are currently used in ARMv8.1-M ports. */
3037+
#if ( portHAS_PACBTI_FEATURE == 1 )
3038+
#ifndef configENABLE_PAC
3039+
#define configENABLE_PAC 0
3040+
#endif
3041+
3042+
#ifndef configENABLE_BTI
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#define configENABLE_BTI 0
3044+
#endif
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#endif
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30353047
/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
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* dynamically allocated RAM, in which case when any task is deleted it is known
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* that both the task's stack and TCB need to be freed. Sometimes the

‎portable/ARMv8M/non_secure/port.c

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@@ -1,6 +1,8 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2024 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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*
@@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
110112
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
111113
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
112114
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
115+
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
113116
/*-----------------------------------------------------------*/
114117

115118
/**
@@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
373376
* any secure calls.
374377
*/
375378
#define portNO_SECURE_CONTEXT 0
379+
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/**
381+
* @brief Constants required to check and configure PACBTI security feature implementation.
382+
*/
383+
#if ( portHAS_PACBTI_FEATURE == 1 )
384+
385+
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
386+
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#define portCONTROL_UPAC_EN ( 1UL << 7UL )
388+
#define portCONTROL_PAC_EN ( 1UL << 6UL )
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#define portCONTROL_UBTI_EN ( 1UL << 5UL )
390+
#define portCONTROL_BTI_EN ( 1UL << 4UL )
391+
392+
#endif /* portHAS_PACBTI_FEATURE */
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/*-----------------------------------------------------------*/
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/**
@@ -410,6 +427,26 @@ static void prvTaskExitError( void );
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static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
411428
#endif /* configENABLE_FPU */
412429

430+
#if ( portHAS_PACBTI_FEATURE == 1 )
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/**
433+
* @brief Configures PACBTI features.
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*
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* This function configures the Pointer Authentication, and Branch Target
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* Identification security features as per the user configuration. It returns
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* the value of the special purpose CONTROL register accordingly, and optionally
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* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
439+
* architecture based) target supports PACBTI security feature.
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*
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* @param xWriteControlRegister Used to control whether the special purpose
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* CONTROL register should be updated or not.
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*
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* @return CONTROL register value according to the configured PACBTI option.
445+
*/
446+
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
447+
448+
#endif /* portHAS_PACBTI_FEATURE */
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/**
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* @brief Setup the timer to generate the tick interrupts.
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*
@@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
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xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
14581495
{
14591496
uint32_t ulIndex = 0;
1497+
uint32_t ulControl = 0x0;
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14611499
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
14621500
ulIndex++;
@@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
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xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
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ulIndex++;
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1544+
#if ( portHAS_PACBTI_FEATURE == 1 )
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{
1546+
/* Check PACBTI security feature configuration before pushing the
1547+
* CONTROL register's value on task's TCB. */
1548+
ulControl = prvConfigurePACBTI( pdFALSE );
1549+
}
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#endif /* portHAS_PACBTI_FEATURE */
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if( xRunPrivileged == pdTRUE )
15071553
{
15081554
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
1509-
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
1555+
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
15101556
ulIndex++;
15111557
}
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else
15131559
{
15141560
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
1515-
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
1561+
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
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ulIndex++;
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}
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@@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
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portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
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portNVIC_SHPR2_REG = 0;
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#if ( portHAS_PACBTI_FEATURE == 1 )
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{
1791+
/* Set the CONTROL register value based on PACBTI security feature
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* configuration before starting the first task. */
1793+
( void) prvConfigurePACBTI( pdTRUE );
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}
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#endif /* portHAS_PACBTI_FEATURE */
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#if ( configENABLE_MPU == 1 )
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{
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/* Setup the Memory Protection Unit (MPU). */
@@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
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21592213
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
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/*-----------------------------------------------------------*/
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#if ( portHAS_PACBTI_FEATURE == 1 )
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2218+
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
2219+
{
2220+
uint32_t ulControl = 0x0;
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2222+
/* Ensure that PACBTI is implemented. */
2223+
configASSERT( portID_ISAR5_REG != 0x0 );
2224+
2225+
/* Enable UsageFault exception if PAC or BTI is enabled. */
2226+
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
2227+
{
2228+
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
2229+
}
2230+
#endif
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#if( configENABLE_PAC == 1 )
2233+
{
2234+
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
2235+
}
2236+
#endif
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2238+
#if( configENABLE_BTI == 1 )
2239+
{
2240+
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
2241+
}
2242+
#endif
2243+
2244+
if( xWriteControlRegister == pdTRUE )
2245+
{
2246+
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
2247+
}
2248+
2249+
return ulControl;
2250+
}
2251+
2252+
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
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/*-----------------------------------------------------------*/

‎portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h

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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2024 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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*
@@ -51,6 +53,7 @@
5153
#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portHAS_PACBTI_FEATURE 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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‎portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h

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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2024 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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*
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#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
5355
#define portARMV8M_MINOR_VERSION 0
56+
#define portHAS_PACBTI_FEATURE 0
5457
#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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‎portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h

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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2024 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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*
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#define portARCH_NAME "Cortex-M33"
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#define portHAS_ARMV8M_MAIN_EXTENSION 1
5355
#define portARMV8M_MINOR_VERSION 0
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#define portHAS_PACBTI_FEATURE 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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‎portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h

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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2024 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
68
*
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5153
#define portARCH_NAME "Cortex-M33"
5254
#define portHAS_ARMV8M_MAIN_EXTENSION 1
5355
#define portARMV8M_MINOR_VERSION 0
56+
#define portHAS_PACBTI_FEATURE 0
5457
#define portDONT_DISCARD __attribute__( ( used ) )
5558
/*-----------------------------------------------------------*/
5659

‎portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h

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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4+
* Copyright 2024 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
46
*
57
* SPDX-License-Identifier: MIT
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*
@@ -51,6 +53,7 @@
5153
#define portARCH_NAME "Cortex-M35P"
5254
#define portHAS_ARMV8M_MAIN_EXTENSION 1
5355
#define portARMV8M_MINOR_VERSION 0
56+
#define portHAS_PACBTI_FEATURE 0
5457
#define portDONT_DISCARD __attribute__( ( used ) )
5558
/*-----------------------------------------------------------*/
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‎portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h

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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
33
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2024 Arm Limited and/or its affiliates
5+
* <open-source-office@arm.com>
46
*
57
* SPDX-License-Identifier: MIT
68
*
@@ -56,6 +58,7 @@
5658
#define portARCH_NAME "Cortex-M55"
5759
#define portHAS_ARMV8M_MAIN_EXTENSION 1
5860
#define portARMV8M_MINOR_VERSION 1
61+
#define portHAS_PACBTI_FEATURE 0
5962
#define portDONT_DISCARD __attribute__( ( used ) )
6063
/*-----------------------------------------------------------*/
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‎portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h

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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2024 Arm Limited and/or its affiliates
5+
* <open-source-office@arm.com>
46
*
57
* SPDX-License-Identifier: MIT
68
*
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5658
#define portARCH_NAME "Cortex-M85"
5759
#define portHAS_ARMV8M_MAIN_EXTENSION 1
5860
#define portARMV8M_MINOR_VERSION 1
61+
#define portHAS_PACBTI_FEATURE 1
5962
#define portDONT_DISCARD __attribute__( ( used ) )
6063
/*-----------------------------------------------------------*/
6164

‎portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h

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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
33
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4+
* Copyright 2024 Arm Limited and/or its affiliates
5+
* <open-source-office@arm.com>
46
*
57
* SPDX-License-Identifier: MIT
68
*
@@ -51,6 +53,7 @@
5153
#define portARCH_NAME "Cortex-M23"
5254
#define portHAS_ARMV8M_MAIN_EXTENSION 0
5355
#define portARMV8M_MINOR_VERSION 0
56+
#define portHAS_PACBTI_FEATURE 0
5457
#define portDONT_DISCARD __root
5558
/*-----------------------------------------------------------*/
5659

‎portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h

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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4+
* Copyright 2024 Arm Limited and/or its affiliates
5+
* <open-source-office@arm.com>
46
*
57
* SPDX-License-Identifier: MIT
68
*
@@ -51,6 +53,7 @@
5153
#define portARCH_NAME "Cortex-M23"
5254
#define portHAS_ARMV8M_MAIN_EXTENSION 0
5355
#define portARMV8M_MINOR_VERSION 0
56+
#define portHAS_PACBTI_FEATURE 0
5457
#define portDONT_DISCARD __root
5558
/*-----------------------------------------------------------*/
5659

‎portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h

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@@ -1,6 +1,8 @@
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/*
22
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
33
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4+
* Copyright 2024 Arm Limited and/or its affiliates
5+
* <open-source-office@arm.com>
46
*
57
* SPDX-License-Identifier: MIT
68
*
@@ -51,6 +53,7 @@
5153
#define portARCH_NAME "Cortex-M33"
5254
#define portHAS_ARMV8M_MAIN_EXTENSION 1
5355
#define portARMV8M_MINOR_VERSION 0
56+
#define portHAS_PACBTI_FEATURE 0
5457
#define portDONT_DISCARD __root
5558
/*-----------------------------------------------------------*/
5659

‎portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h

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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
33
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4+
* Copyright 2024 Arm Limited and/or its affiliates
5+
* <open-source-office@arm.com>
46
*
57
* SPDX-License-Identifier: MIT
68
*
@@ -51,6 +53,7 @@
5153
#define portARCH_NAME "Cortex-M33"
5254
#define portHAS_ARMV8M_MAIN_EXTENSION 1
5355
#define portARMV8M_MINOR_VERSION 0
56+
#define portHAS_PACBTI_FEATURE 0
5457
#define portDONT_DISCARD __root
5558
/*-----------------------------------------------------------*/
5659

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