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Fix build error for MSP430 and Cortex A with IAR (#937)
* fix whitespace in asm macros * Revert formatting ARM_CA5_No_GIC and ARM_CA9
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‎portable/IAR/ARM_CA5_No_GIC/portASM.h

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; /*
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* ; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* ; *
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* ; * SPDX-License-Identifier: MIT
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* ; *
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* ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
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* ; * this software and associated documentation files (the "Software"), to deal in
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* ; * the Software without restriction, including without limitation the rights to
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* ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* ; * the Software, and to permit persons to whom the Software is furnished to do so,
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* ; * subject to the following conditions:
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* ; *
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* ; * The above copyright notice and this permission notice shall be included in all
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* ; * copies or substantial portions of the Software.
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* ; *
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* ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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* ; *
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* ; * https://www.FreeRTOS.org
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* ; * https://github.com/FreeRTOS
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* ; *
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* ; */
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EXTERN vTaskSwitchContext
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EXTERN ulCriticalNesting
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EXTERN pxCurrentTCB
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EXTERN ulPortTaskHasFPUContext
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EXTERN ulAsmAPIPriorityMask
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;/*
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; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
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; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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; *
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; * SPDX-License-Identifier: MIT
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; *
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; * Permission is hereby granted, free of charge, to any person obtaining a copy of
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; * this software and associated documentation files (the "Software"), to deal in
9+
; * the Software without restriction, including without limitation the rights to
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; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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; * the Software, and to permit persons to whom the Software is furnished to do so,
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; * subject to the following conditions:
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; *
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; * The above copyright notice and this permission notice shall be included in all
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; * copies or substantial portions of the Software.
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; *
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; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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; *
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; * https://www.FreeRTOS.org
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; * https://github.com/FreeRTOS
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; *
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; */
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EXTERN vTaskSwitchContext
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EXTERN ulCriticalNesting
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EXTERN pxCurrentTCB
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EXTERN ulPortTaskHasFPUContext
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EXTERN ulAsmAPIPriorityMask
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portSAVE_CONTEXT macro
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;
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Save the LR and SPSR onto the system mode stack before switching to
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;
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system mode to save the remaining system mode registers
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SRSDB sp !, # SYS_MODE
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CPS # SYS_MODE
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PUSH {
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R0 - R12, R14
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}
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;
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Push the critical nesting count
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LDR R2, = ulCriticalNesting
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LDR R1, [ R2 ]
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PUSH {
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R1
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}
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;
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Does the task have a floating point context that needs saving ? If
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;
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ulPortTaskHasFPUContext is 0 then no.
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LDR R2, = ulPortTaskHasFPUContext
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LDR R3, [ R2 ]
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CMP R3, # 0
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;
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Save the floating point context,
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if any
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FMRXNE R1, FPSCR
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VPUSHNE {
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D0 - D15
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}
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; Save the LR and SPSR onto the system mode stack before switching to
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; system mode to save the remaining system mode registers
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SRSDB sp!, #SYS_MODE
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CPS #SYS_MODE
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PUSH {R0-R12, R14}
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; Push the critical nesting count
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LDR R2, =ulCriticalNesting
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LDR R1, [R2]
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PUSH {R1}
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; Does the task have a floating point context that needs saving? If
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; ulPortTaskHasFPUContext is 0 then no.
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LDR R2, =ulPortTaskHasFPUContext
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LDR R3, [R2]
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CMP R3, #0
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; Save the floating point context, if any
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FMRXNE R1, FPSCR
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VPUSHNE {D0-D15}
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#if configFPU_D32 == 1
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VPUSHNE {
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D16 - D31
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}
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#endif; configFPU_D32
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PUSHNE {
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R1
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}
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;
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Save ulPortTaskHasFPUContext itself
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PUSH {
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R3
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}
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;
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Save the stack pointer in the TCB
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LDR R0, = pxCurrentTCB
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LDR R1, [ R0 ]
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STR SP, [ R1 ]
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endm
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VPUSHNE {D16-D31}
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#endif ; configFPU_D32
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PUSHNE {R1}
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; Save ulPortTaskHasFPUContext itself
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PUSH {R3}
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; Save the stack pointer in the TCB
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LDR R0, =pxCurrentTCB
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LDR R1, [R0]
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STR SP, [R1]
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endm
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; /**********************************************************************/
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portRESTORE_CONTEXT macro
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;
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Set the SP to point to the stack of the task being restored.
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LDR R0, = pxCurrentTCB
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LDR R1, [ R0 ]
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LDR SP, [ R1 ]
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;
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Is there a floating point context to restore ? If the restored
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;
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ulPortTaskHasFPUContext is zero then no.
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LDR R0, = ulPortTaskHasFPUContext
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POP {
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R1
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}
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STR R1, [ R0 ]
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CMP R1, # 0
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;
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Restore the floating point context,
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if any
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POPNE {
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R0
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}
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; Set the SP to point to the stack of the task being restored.
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LDR R0, =pxCurrentTCB
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LDR R1, [R0]
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LDR SP, [R1]
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; Is there a floating point context to restore? If the restored
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; ulPortTaskHasFPUContext is zero then no.
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LDR R0, =ulPortTaskHasFPUContext
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POP {R1}
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STR R1, [R0]
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CMP R1, #0
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; Restore the floating point context, if any
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POPNE {R0}
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#if configFPU_D32 == 1
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VPOPNE {
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D16 - D31
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}
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#endif; configFPU_D32
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VPOPNE {
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D0 - D15
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}
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VMSRNE FPSCR, R0
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;
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Restore the critical section nesting depth
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LDR R0, = ulCriticalNesting
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POP {
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R1
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}
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STR R1, [ R0 ]
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;
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Restore all system mode registers other than the SP( which is already
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;
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being used )
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POP
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{
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R0 - R12, R14
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}
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Return to the task code, loading CPSR on the way.CPSR has the interrupt
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;
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enable bit set appropriately
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for the task about to execute.
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RFEIA sp !
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endm
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VPOPNE {D16-D31}
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#endif ; configFPU_D32
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VPOPNE {D0-D15}
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VMSRNE FPSCR, R0
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; Restore the critical section nesting depth
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LDR R0, =ulCriticalNesting
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POP {R1}
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STR R1, [R0]
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; Restore all system mode registers other than the SP (which is already
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; being used)
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POP {R0-R12, R14}
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; Return to the task code, loading CPSR on the way. CPSR has the interrupt
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; enable bit set appropriately for the task about to execute.
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RFEIA sp!
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endm

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